Changes between Version 4 and Version 5 of boot_loader
- Timestamp:
- Nov 5, 2014, 4:59:12 PM (10 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
boot_loader
v4 v5 29 29 30 30 === '''boot_schedulers init()''' === 31 This function makes the schedulers initialisation, as specified in the mapping, withthe following principles.31 This function makes the schedulers initialisation, as specified in the mapping, respecting the following principles. 32 32 * There is one scheduler per processor. 33 33 * Any task defined in any application can be allocated to any processor. 34 34 * The allocation of task to processors is fully static (no task migration). 35 35 * One single processor cannot schedule more than 14 tasks. 36 One scheduler occupies 8 Kbytes, and contains the contexts of all tasks allocated to the processor (256 bytes per task).36 * One scheduler occupies 8 Kbytes, and contains the contexts of all tasks allocated to the processor (256 bytes per task). 37 37 38 38 === '''boot_peripherals_init()''' === 39 39 This function makes the external peripherals and coprocessors initialisation. 40 40 41 42 41 === '''''boot_elf_load()''' === 43 42 This function load into memory the kernel code (''kernel.elf'' file), and the user code for all applications specified in the mapping. 44 45 43 46 44 Finally, processor(0,0,0) starts all other processors, using an inter-processor interrupt (WTI). … … 48 46 to the ''kernel_init()'' function. 49 47 50 == __Phase 2__ == 48 == __Phase 2 : Kernel__ == 49 50 This phase is executed by all processors in parallel. All processors enter the same [source:soft/giet_vm/giet_kernel/kernel_init.c kernel_init() function. 51 The main steps are the following: 52 53 * Step 1 : each processor get its scheduler virtual address from CP0_SCHED register and contributes to _schedulers[] array initialisation 54 * step 2 : each processor loops on all allocated tasks to build the _ptabs_vaddr[] & _ptabs_ptprs[] arrays from the tasks contexts. 55 * step 3 : each processor computes and set the XCU masks, as specified in the HWI, PTI, and WTI interrupt vectors. 56 * step 4 : each processor starts its TICK timer if it has at least at least one task allocated 57 * step 5 : each processor updates the idle_task context (CTX_SP, CTX_RA, CTX_EPC). 58 * step 6 : when all processors reach the synchronisation barrier, each processor set registers SP, SR, PTPR, EPC, with the values corresponding to the first allocated task, and jump to user code 51 59 52 60