Changes between Version 13 and Version 14 of cma_driver

Timestamp:

Feb 9, 2015, 7:14:52 PM (10 years ago)

Author:

alain

Comment:

--

cma_driver

@@ -9 +9 @@
 
 A single CMA channel transfers a stream of data from a set of chained buffers (source ''chbuf'') to another set of chained buffers (destination ''chbuf'').  This controller implements two modes to scan the source and destination chbufs:
- * '''IN_ORDER_FIFO''' : The chained buffers are read and write in strict order, with a blocking polling policy to access both the expected source chbuf and the expected destination chbuf. The waiting delay between two accesses is defined, for each channel, by the CHBUF_PERIOD addressable register, and must be non zero to activate this mode.
- * '''OUT OF ORDER''' : The controller scan the source buffers, and the first full buffer found is read. Similarly, the controller scan the destination buffers, and the first empty buffer found is written, with a round robin priority for the search. This mode is activated when the CHBUF_PERIOD value is zero (default value).
+ * '''IN_ORDER''' : The chained buffers are handled as a software FIFO: The buffers are read and written in strict order, with a blocking polling policy to access both the expected source buffer and the expected destination buffer. The waiting delay between two accesses is defined, for each channel, by the CHBUF_PERIOD addressable register, and must be non zero to activate this mode.
+ * '''OUT OF ORDER''' : The controller scan all the source buffers, and the first full buffer found is read. Similarly, the controller scan all the destination buffers, and the first empty buffer found is written, with a round robin priority for the search. This mode is activated when the CHBUF_PERIOD value is zero (default value).
 
 A ''chbuf'' descriptor is a variable size circular array of 64 bits entries. Each entry is a single buffer descriptor, and