12 | | Takes a lock with a blocking ll/sc atomic access. If the cache coherence is granted by the hardware, |
13 | | the first read is a standard (cacheable) lw, as the local copy can be polled when the lock is already taken by another task, reducing trafic on the interconnect. When the lock is released by the owner task, the local copy is updated or invalidated by the coherence protocol. If there is no hardware cache coherence a pseudo random delay is introduced between two successive retry. |
| 12 | Takes a lock with a blocking ll/sc atomic access. |
| 13 | * If the cache coherence is granted by the hardware, |
| 14 | the first read is a standard (cacheable) lw, as the local copy can be polled when the lock is already taken by another task, reducing trafic on the interconnect. When the lock is released by the owner task, the local copy is updated or invalidated by the coherence protocol. |
| 15 | * If there is no hardware cache coherence a pseudo random delay is introduced between two successive retry. |