Version 4 (modified by 9 years ago) (diff) | ,
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Virtual to Physical Address Translation
The vmem.c and vmem.h files define the data structures and functions used by the boot-loader and the kernel to implement the paged virtual memory.
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Virtual to Physical Address Translation
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- unsigned long long _v2p_translate( unsigned int vaddr , …
- void _v2p_add_pte1( unsigned int vspace_id , unsigned int x , …
- void _v2p_add_pte2( unsigned int vspace_id , unsigned int x , …
- void _v2p_del_pte1( unsigned int vspace_id , unsigned int x , …
- void _v2p_del_pte2( unsigned int vspace_id , unsigned int x , …
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The page table initialisation is statically done by the boot-loader. There is one page table for each vspace defined in the mapping. When the architecture is clusterised (X_WIDTH > 1 or Y_WIDTH > 1), for each vspace, the page table is replicated in each cluster.
The virtual address format is 32 bits: structured in 3 fields:
11 | 9 | 12 |
IX1 | IX2 | OFFSET |
- The IX1 field is the index in the first level page table
- The IX2 field is the index in the second level page table.
- The |IX1|IX2| concatenation defines the VPN (Virtual Page Number).
Two page sizes are supported:
- BPP : Big Physical Page / 2 Mbytes
- SPP : Small Physical pages / 4 Kbytes
unsigned long long _v2p_translate( unsigned int vaddr , unsigned int* flags )
This function returns the physical address from the virtual address. The MMU is supposed to be activated, and it uses the page table defined by the CP0_PTPR register. It supports both small (4 Kbytes) & big (2 Mbytes) pages.
- vaddr: virtual address.
- flags: page flags are returned in this variable.
Exit if PTE1 or PTE2 unmapped.
void _v2p_add_pte1( unsigned int vspace_id , unsigned int x , unsigned int y , unsigned int vpn , unsigned int flags , unsigned int ppn , unsigned int ident )
This function registers a new PTE1 (BPP)vin the page table defined by the <vspace_id> argument, and the <x,y> coordinates. The value is defined by the <flags> and <ppn> arguments. It updates only the first level PT1. As each vseg is mapped by a different processor, the PT1 entry cannot be concurrently accessed, and we don't need to take any lock.