Changes between Version 78 and Version 79 of library_stdio

Timestamp:

Apr 13, 2015, 9:33:09 AM (10 years ago)

Author:

alain

Comment:

--

library_stdio

@@ -49 +49 @@
 The '''vci_mwmr_dma''' component provide to coprocessor a variable number of TO_COPROC or FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to transfer one or several bursts of 32 bits words, without address. The burst size (generally a cache line), the number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port are hardware parameters, depending on the coprocessor type. Each port define a private communication channel between the coprocessor and a user memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes.
 
-The '''vci_mwmr_dma''' component implements two transfer modes that can be defined by the user application through dedicate system calls.
 The user application must use the ''giet_coproc_alloc()'' system call to get a private hardware coprocessor. Then it must use the ''giet_coproc_channel_init()'' system call to configure the TO_COPROC/FROM_COPROC channels. Finally, the coprocessor and the communication channels are activated by the ''giet_coproc_run()'' system call. 
- * In '''MODE_MWMR''', each channel FSM  implements the 7 steps MWMR protocol, and transfer an "infinite" data stream, between one coprocessor port and a MWMR software FIFO in memory. The ''giet_coproc_run()'' system call is non blocking, as the synchronisation is done through the MWMR FIFOs (no transfer completion event). The MWR IRQ is only asserted if a VCI error is reported in memory access. 
+
+The '''vci_mwmr_dma''' component implements two transfer modes:
+ * In '''MODE_MWMR''', each channel FSM  implements the 7 steps MWMR protocol, and transfer an "infinite" data stream, between one coprocessor port and a MWMR software FIFO in memory. The ''giet_coproc_run()'' system call is non blocking, as the synchronisation is done through the MWMR FIFOs (no transfer completion event). The MWR IRQ is only asserted if a VCI error is reported in a memory access. 
  * In '''MODE_DMA_IRQ''' or '''MODE_DMA_NO_IRQ''', each channel FSM transfers a single buffer between one coprocessor port and the memory, and keep blocked when the transfer is completed. 
    - In '''MODE_DMA_IRQ''', the calling task is descheduled, after coprocessor activation, in the ''giet_coproc_run()'' system call. It is rescheduled by the MWR IRQ signaling the global completion. The _mwr_isr() scan all channels status registers to report possible addressing errors, and reset the communication channels.