Changes between Version 2 and Version 3 of mmc_driver


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Timestamp:
Jan 20, 2015, 7:05:11 PM (10 years ago)
Author:
alain
Comment:

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  • mmc_driver

    v2 v3  
    77
    88The ''vci_mem_cache'' component is a L2 cache controller specifically designed for the TSAR architecture.
    9 It contains several addressable registers that can be used to support software based cache coherence between L2 and L3 caches.
     9It contains 3 types of addressable registers:
     10 * '''configuration registers''' support software based cache coherence between L2 and L3 caches.
     11 * '''instrumentation registers''' define various hardware event counters
     12 * '''error report registers''' contains various informations on address errors reported by the L2 cache.
    1013
    1114The MMC component is a replicated peripheral, as it exist one MMC component per cluster.
     
    1821The addressable registers map and command codes are defined [source:soft/giet_vm/giet_drivers/mmc_driver.h here].
    1922
     23 == Configuration registers access functions ==
    2024
    2125 === void '''_mmc_inval'''( unsigned long long buf_paddr,   unsigned int buf_length ) ===
     
    2529This function copies to external RAM all cache lines covering a memory buffer defined by the physical base address, and the length, if they are dirty. The buffer address MSB are used to compute the cluster index.
    2630
     31 ==Instrumentation registers access functions ==
     32
     33 === unsigned int '''_mmc_get_instrument'''( unsigned int x,  unsigned int y,  unsigned int reg ) ===
     34This function returns the value contained in a specific register of a specific L2 cache.
     35 * '''x''' cluster X coordinate
     36 * '''y''' cluster Y coordinate
     37 * '''reg''' register index
     38
     39 == Error registers access functions ==
     40
    2741 === void '''_mmc_isr'''( unsigned int irq_type,   unsigned int irq_id,   unsigned int channel ) ===
    2842This Interrupt Service Routine access the vci_mem_cache component to get
    2943 the faulty physical address and the associated SRCID. It acknowledges the IRQ.
    30  Not implemented yet...
     44 Not fully implemented yet...
     45
    3146