= GIET_VM / MMC Driver =

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The [source:soft/giet_vm/giet_drivers/mmc_driver.c mmc_driver.c] and [source:soft/giet_vm/giet_drivers/mmc_driver.h mmc_driver.h] files define the MMC driver.

The ''vci_mem_cache'' component is a L2 cache controller specifically designed for the TSAR architecture.
It contains several addressable registers that can be used to support software based cache coherence between L2 and L3 caches. 

The MMC component is a replicated peripheral, as it exist one MMC component per cluster.

The virtual base address of the segment associated to the component is:
    vbase =  SEG_MMC_BASE + cluster_xy * PERI_CLUSTER_INCREMENT

The SEG_MMC_BASE and PERI_CLUSTER_INCREMENT variables must be defined in the hard_config.h file.

The addressable registers map and command codes are defined [source:soft/giet_vm/giet_drivers/mmc_driver.h here].


 === void '''_mmc_inval'''( unsigned long long buf_paddr,   unsigned int buf_length ) ===
This function invalidates all cache lines covering a memory buffer defined by the physical base address, and the length. The buffer address MSB are used to compute the cluster index.

 ===  void '''_mmc_sync'''(  unsigned long long buf_paddr,    unsigned int buf_length) ===
This function copies to external RAM all cache lines covering a memory buffer defined by the physical base address, and the length, if they are dirty. The buffer address MSB are used to compute the cluster index.

 === void '''_mmc_isr'''( unsigned int irq_type,   unsigned int irq_id,   unsigned int channel ) ===
This Interrupt Service Routine access the vci_mem_cache component to get 
 the faulty physical address and the associated SRCID. It acknowledges the IRQ.
 Not implemented yet...