8 | | The vci_mwmr_controller is a multi-channels hardware component that can be used to connect an hardware coprocesseur to one or several MWMR channels (software FIFOs implemented in memory). |
9 | | * On the VCI side, it implements the five steps MWMR communication protocol. |
10 | | * On the coprocessor side, it implements as many FIFOs interfaces as the number of MWMR channels. |
| 8 | The vci_mwmr_dma component is a multi-channels hardware component that can be used to connect an hardware coprocesseur to a VCI interconnect. |
| 9 | This component provides the coprocessor one or several TO_COPROC or FROM_COPROC FIFO type communication channels, without address. |
| 10 | Each T0_COPROC/FROM coproc port contains an hardware FIFO interface (data, r_wok, w_rok signals), plus three signals (REQ, ACK, BURSTS) allowing the coprocessor |
| 11 | to request an integer number of data burst. Each burst contains a fixed number of 32 bits words. Each channel implements two running modes: |
| 12 | * in '''MWMR''' mode the channel FSM transfer an infinite" stream of data to or from a MWMR software FIFO, implementing the 7 steps MWMR protocol. |
| 13 | * in '''DMA''' mode the channel FSM transfer a fixed size chunk of data to or from a memory buffer, with a completion signaling interrupt. |