[80] | 1 | #ifndef ENVIRONMENT_CACHE_PARAMETERS_H |
---|
| 2 | #define ENVIRONMENT_CACHE_PARAMETERS_H |
---|
[78] | 3 | |
---|
| 4 | #include <iostream> |
---|
| 5 | #include <math.h> |
---|
| 6 | |
---|
| 7 | #include "Cache_MultiLevel_Parameters.h" |
---|
| 8 | |
---|
[80] | 9 | namespace environment { |
---|
[78] | 10 | namespace cache { |
---|
| 11 | |
---|
| 12 | class Parameters |
---|
| 13 | { |
---|
| 14 | public : uint32_t nb_cache_dedicated; |
---|
| 15 | public : uint32_t nb_iport; |
---|
| 16 | |
---|
| 17 | public : cache_multilevel::Parameters ** param_icache_dedicated; |
---|
| 18 | public : cache_multilevel::Parameters ** param_dcache_dedicated; |
---|
| 19 | public : cache_multilevel::Parameters * param_cache_shared; |
---|
| 20 | |
---|
| 21 | public : Parameters (uint32_t nb_cache_dedicated , |
---|
| 22 | uint32_t * icache_dedicated_nb_level , |
---|
| 23 | uint32_t * icache_dedicated_nb_port , |
---|
| 24 | uint32_t ** icache_dedicated_nb_line , |
---|
| 25 | uint32_t ** icache_dedicated_size_line , |
---|
| 26 | uint32_t ** icache_dedicated_size_word , |
---|
| 27 | uint32_t ** icache_dedicated_associativity, |
---|
| 28 | uint32_t ** icache_dedicated_hit_latence , |
---|
| 29 | uint32_t ** icache_dedicated_miss_penality, |
---|
| 30 | uint32_t * dcache_dedicated_nb_level , |
---|
| 31 | uint32_t * dcache_dedicated_nb_port , |
---|
| 32 | uint32_t ** dcache_dedicated_nb_line , |
---|
| 33 | uint32_t ** dcache_dedicated_size_line , |
---|
| 34 | uint32_t ** dcache_dedicated_size_word , |
---|
| 35 | uint32_t ** dcache_dedicated_associativity, |
---|
| 36 | uint32_t ** dcache_dedicated_hit_latence , |
---|
| 37 | uint32_t ** dcache_dedicated_miss_penality, |
---|
| 38 | uint32_t cache_shared_nb_level , |
---|
| 39 | // uint32_t cache_shared_nb_port , |
---|
| 40 | uint32_t * cache_shared_nb_line , |
---|
| 41 | uint32_t * cache_shared_size_line , |
---|
| 42 | uint32_t * cache_shared_size_word , |
---|
| 43 | uint32_t * cache_shared_associativity , |
---|
| 44 | uint32_t * cache_shared_hit_latence , |
---|
| 45 | uint32_t * cache_shared_miss_penality ) |
---|
| 46 | { |
---|
| 47 | this->nb_cache_dedicated = nb_cache_dedicated; |
---|
| 48 | |
---|
| 49 | uint32_t cache_shared_nb_port = 0; |
---|
| 50 | uint32_t nb_iport = 0; |
---|
| 51 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
---|
| 52 | { |
---|
| 53 | nb_iport += icache_dedicated_nb_port [i]; |
---|
| 54 | cache_shared_nb_port += icache_dedicated_nb_port [i]; |
---|
| 55 | cache_shared_nb_port += dcache_dedicated_nb_port [i]; |
---|
| 56 | } |
---|
| 57 | |
---|
| 58 | param_cache_shared = new cache_multilevel::Parameters |
---|
| 59 | (cache_shared_nb_level , |
---|
| 60 | cache_shared_nb_port , |
---|
| 61 | cache_shared_nb_line , |
---|
| 62 | cache_shared_size_line , |
---|
| 63 | cache_shared_size_word , |
---|
| 64 | cache_shared_associativity , |
---|
| 65 | cache_shared_hit_latence , |
---|
| 66 | cache_shared_miss_penality ); |
---|
| 67 | |
---|
| 68 | param_icache_dedicated = new cache_multilevel::Parameters * [nb_cache_dedicated]; |
---|
| 69 | param_dcache_dedicated = new cache_multilevel::Parameters * [nb_cache_dedicated]; |
---|
| 70 | |
---|
| 71 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
---|
| 72 | { |
---|
| 73 | param_icache_dedicated [i] = new cache_multilevel::Parameters |
---|
| 74 | (icache_dedicated_nb_level [i], |
---|
| 75 | icache_dedicated_nb_port [i], |
---|
| 76 | icache_dedicated_nb_line [i], |
---|
| 77 | icache_dedicated_size_line [i], |
---|
| 78 | icache_dedicated_size_word [i], |
---|
| 79 | icache_dedicated_associativity [i], |
---|
| 80 | icache_dedicated_hit_latence [i], |
---|
| 81 | icache_dedicated_miss_penality [i]); |
---|
| 82 | |
---|
| 83 | param_dcache_dedicated [i] = new cache_multilevel::Parameters |
---|
| 84 | (dcache_dedicated_nb_level [i], |
---|
| 85 | dcache_dedicated_nb_port [i], |
---|
| 86 | dcache_dedicated_nb_line [i], |
---|
| 87 | dcache_dedicated_size_line [i], |
---|
| 88 | dcache_dedicated_size_word [i], |
---|
| 89 | dcache_dedicated_associativity [i], |
---|
| 90 | dcache_dedicated_hit_latence [i], |
---|
| 91 | dcache_dedicated_miss_penality [i]); |
---|
| 92 | } |
---|
| 93 | } |
---|
| 94 | |
---|
| 95 | public : ~Parameters (void) |
---|
| 96 | { |
---|
| 97 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
---|
| 98 | { |
---|
| 99 | delete param_icache_dedicated [i]; |
---|
| 100 | delete param_dcache_dedicated [i]; |
---|
| 101 | } |
---|
| 102 | delete [] param_icache_dedicated; |
---|
| 103 | delete [] param_dcache_dedicated; |
---|
| 104 | delete param_cache_shared; |
---|
| 105 | } |
---|
| 106 | |
---|
| 107 | public : std::string print (uint32_t depth) |
---|
| 108 | { |
---|
| 109 | std::string tab (depth,'\t'); |
---|
| 110 | std::stringstream str; |
---|
| 111 | |
---|
| 112 | str << tab << "* Nb Cache dedicated : " << nb_cache_dedicated << std::endl |
---|
| 113 | << tab << "* Nb iport : " << nb_iport << std::endl; |
---|
| 114 | |
---|
| 115 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
---|
| 116 | str << tab << " * ICACHE DEDICATED " << i << std::endl |
---|
| 117 | << param_icache_dedicated [i]->print(depth+1) << std::endl; |
---|
| 118 | |
---|
| 119 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
---|
| 120 | str << tab << " * DCACHE DEDICATED " << i << std::endl |
---|
| 121 | << param_dcache_dedicated [i]->print(depth+1) << std::endl; |
---|
| 122 | |
---|
| 123 | str << tab << " * CACHE SHARED" << std::endl; |
---|
| 124 | str << param_cache_shared->print(depth+1) << std::endl; |
---|
| 125 | |
---|
| 126 | return str.str(); |
---|
| 127 | } |
---|
| 128 | |
---|
| 129 | friend std::ostream& operator<< (std::ostream& output, Parameters &x) |
---|
| 130 | { |
---|
| 131 | output << x.print(0); |
---|
| 132 | return output; |
---|
| 133 | } |
---|
| 134 | }; |
---|
| 135 | |
---|
| 136 | }; |
---|
| 137 | }; |
---|
| 138 | #endif |
---|