[81] | 1 | #include "../include/Cache.h" |
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[78] | 2 | #include <iostream> |
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| 3 | |
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| 4 | using namespace std; |
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[80] | 5 | using namespace environment; |
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| 6 | using namespace environment::cache; |
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[78] | 7 | |
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[81] | 8 | #define TEST(x,y) \ |
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| 9 | { \ |
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| 10 | if (x==y) \ |
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| 11 | { \ |
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| 12 | cout << "Line " << __LINE__ << " : " << "Test OK" << endl; \ |
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| 13 | } \ |
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| 14 | else \ |
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| 15 | { \ |
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| 16 | cout << "Line " << __LINE__ << " : " << "Test KO" << endl; \ |
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| 17 | exit (EXIT_FAILURE); \ |
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| 18 | } \ |
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[78] | 19 | } while (0) |
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| 20 | |
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| 21 | |
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| 22 | |
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[81] | 23 | #ifdef SYSTEMC |
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| 24 | int sc_main (int argc, char * argv[]) |
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| 25 | #else |
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| 26 | int main (int argc, char * argv[]) |
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| 27 | #endif |
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[78] | 28 | { |
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| 29 | cout << "<main> Begin" << endl; |
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| 30 | |
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| 31 | { |
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| 32 | cache_onelevel::Parameters * param = new cache_onelevel::Parameters |
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| 33 | ( |
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| 34 | 4, // nb_port |
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| 35 | 32, // nb_line |
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| 36 | 8, // size_line |
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| 37 | 4,// size_word |
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| 38 | 4, // associativity |
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| 39 | 2, // hit_latence |
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| 40 | 3 // miss_penality |
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| 41 | ); |
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| 42 | |
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[81] | 43 | // cout << *param << endl; |
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[78] | 44 | |
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| 45 | cache_onelevel::Cache_OneLevel * cache = new cache_onelevel::Cache_OneLevel ("my_cache",param); |
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| 46 | cache->reset(); |
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| 47 | |
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[81] | 48 | // cout << *cache << endl; |
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[78] | 49 | |
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| 50 | cache->transition(); |
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| 51 | cache->transition(); |
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| 52 | |
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[81] | 53 | // cout << *cache << endl; |
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[78] | 54 | |
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| 55 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), MISS); |
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| 56 | TEST(cache->latence(0), 5); |
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| 57 | cache->transition(); // miss cycle 1 |
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| 58 | |
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| 59 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_WRITE_BUFFER); |
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| 60 | TEST(cache->latence(0), 4); |
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| 61 | cache->transition(); // miss cycle 2 |
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| 62 | |
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| 63 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_WRITE_BUFFER); |
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| 64 | TEST(cache->latence(0), 3); |
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| 65 | cache->transition(); // miss cycle 3 |
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| 66 | |
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| 67 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE); //word 0 |
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| 68 | TEST(cache->latence(0), 2); |
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| 69 | |
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| 70 | TEST(cache->access(0, 0x104, 0, CACHED, WRITE), HIT_CACHE); //word 1 |
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| 71 | TEST(cache->access(0, 0x108, 0, CACHED, WRITE), HIT_CACHE); //word 2 |
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| 72 | TEST(cache->access(0, 0x10c, 0, CACHED, WRITE), HIT_CACHE); //word 3 |
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| 73 | TEST(cache->access(0, 0x110, 0, CACHED, WRITE), HIT_CACHE); //word 4 |
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| 74 | TEST(cache->access(0, 0x114, 0, CACHED, WRITE), HIT_CACHE); //word 5 |
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| 75 | TEST(cache->access(0, 0x118, 0, CACHED, WRITE), HIT_CACHE); //word 6 |
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| 76 | TEST(cache->access(0, 0x11c, 0, CACHED, WRITE), HIT_CACHE); //word 7 |
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| 77 | TEST(cache->access(0, 0x120, 0, CACHED, WRITE), MISS ); |
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| 78 | TEST(cache->access(1, 0x140, 0, CACHED, WRITE), MISS ); |
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| 79 | TEST(cache->access(2, 0x160, 0, CACHED, WRITE), MISS ); |
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| 80 | TEST(cache->access(3, 0x144, 0, CACHED, WRITE), HIT_BYPASS); |
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| 81 | |
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| 82 | TEST(cache->latence(0), 5); |
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| 83 | TEST(cache->latence(1), 5); |
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| 84 | TEST(cache->latence(2), 5); |
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| 85 | TEST(cache->latence(3), 5); |
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| 86 | |
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| 87 | cache->transition(); // miss access |
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| 88 | TEST(cache->access(0, 0x180, 0, CACHED, WRITE), MISS ); |
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| 89 | TEST(cache->access(1, 0x1a0, 0, CACHED, WRITE), MISS ); |
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| 90 | TEST(cache->access(2, 0x1c0, 0, CACHED, WRITE), MISS ); |
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| 91 | TEST(cache->access(3, 0x1e0, 0, CACHED, WRITE), MISS ); |
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| 92 | |
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| 93 | cache->transition(); // miss cycle 1 |
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[81] | 94 | // cout << *cache << endl; |
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[78] | 95 | |
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| 96 | TEST(cache->access(0, 0x200, 0, CACHED, WRITE), MISS ); |
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| 97 | TEST(cache->access(1, 0x300, 0, CACHED, WRITE), MISS ); |
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| 98 | TEST(cache->access(2, 0x400, 0, CACHED, WRITE), MISS ); |
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| 99 | |
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| 100 | cache->transition(); // miss cycle 0 |
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| 101 | cache->transition(); // miss cycle 1 |
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| 102 | cache->transition(); // miss cycle 2 |
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| 103 | cache->transition(); // miss cycle 3 |
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[81] | 104 | // cout << *cache << endl; |
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[78] | 105 | |
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| 106 | // line 0 : all way is use |
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| 107 | TEST(cache->access(0, 0x118, 0, CACHED, WRITE), HIT_CACHE ); |
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| 108 | TEST(cache->access(1, 0x204, 0, CACHED, WRITE), HIT_CACHE ); |
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| 109 | TEST(cache->access(2, 0x100, 0,UNCACHED, WRITE), MISS ); |
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| 110 | TEST(cache->access(3, 0x118, 0, CACHED, WRITE), HIT_BYPASS); |
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| 111 | |
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| 112 | TEST(cache->latence(0), 2); |
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| 113 | TEST(cache->latence(1), 2); |
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| 114 | TEST(cache->latence(2), 5); |
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| 115 | TEST(cache->latence(3), 2); |
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| 116 | |
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| 117 | cache->transition(); |
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[81] | 118 | // cout << *cache << endl; |
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[78] | 119 | |
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| 120 | TEST(cache->access(0, 0x500, 0, CACHED, WRITE), MISS ); |
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| 121 | |
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| 122 | cache->transition(); // miss cycle 1 |
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| 123 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 124 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 125 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 126 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), HIT_CACHE ); |
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| 127 | |
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| 128 | cache->transition(); // miss cycle 2 |
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| 129 | |
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| 130 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 131 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 132 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 133 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), HIT_CACHE ); |
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| 134 | |
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| 135 | cache->transition(); // miss cycle 3 |
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| 136 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 137 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 138 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 139 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), MISS ); |
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| 140 | |
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| 141 | TEST(cache->latence(0), 2); |
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| 142 | TEST(cache->latence(1), 2); |
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| 143 | TEST(cache->latence(2), 2); |
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| 144 | TEST(cache->latence(3), 5); |
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| 145 | |
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[81] | 146 | // cout << *cache << endl; |
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[78] | 147 | |
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| 148 | delete cache; |
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| 149 | delete param; |
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| 150 | } |
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| 151 | |
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| 152 | { |
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| 153 | uint32_t * nb_line = new uint32_t [3]; |
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| 154 | uint32_t * size_line = new uint32_t [3]; |
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| 155 | uint32_t * size_word = new uint32_t [3]; |
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| 156 | uint32_t * associativity = new uint32_t [3]; |
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| 157 | uint32_t * hit_latence = new uint32_t [3]; |
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| 158 | uint32_t * miss_penality = new uint32_t [3]; |
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| 159 | |
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| 160 | nb_line [0] = 4 ; nb_line [1] = 4 ; nb_line [2] = 4 ; |
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| 161 | size_line [0] = 8 ; size_line [1] = 8 ; size_line [2] = 8 ; |
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| 162 | size_word [0] = 4 ; size_word [1] = 4 ; size_word [2] = 4 ; |
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| 163 | associativity [0] = 1 ; associativity [1] = 2 ; associativity [2] = 4 ; |
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| 164 | hit_latence [0] = 1 ; hit_latence [1] = 2 ; hit_latence [2] = 2 ; |
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| 165 | miss_penality [0] = 3 ; miss_penality [1] = 5 ; miss_penality [2] = 7 ; |
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| 166 | |
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| 167 | cache_multilevel::Parameters * param = new cache_multilevel::Parameters |
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| 168 | ( |
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| 169 | 3, // nb_level |
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| 170 | 4, // nb_port |
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| 171 | nb_line , |
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| 172 | size_line , |
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| 173 | size_word , |
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| 174 | associativity, |
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| 175 | hit_latence , |
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| 176 | miss_penality |
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| 177 | ); |
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| 178 | |
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[81] | 179 | // cout << *param << endl; |
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[78] | 180 | |
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| 181 | cache_multilevel::Cache_MultiLevel * cache = new cache_multilevel::Cache_MultiLevel ("my_cache",param); |
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| 182 | |
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| 183 | cache->reset(); |
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[81] | 184 | // cout << *cache << endl; |
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[78] | 185 | |
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| 186 | cache_multilevel::Access access; |
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| 187 | |
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| 188 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 189 | cache->update_access(access); |
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| 190 | |
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| 191 | TEST(access.num_port , 0); |
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| 192 | TEST(access.hit , MISS); |
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| 193 | TEST(access.latence , 20); |
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| 194 | TEST(access.last_nb_level, 2); |
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| 195 | |
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| 196 | cache->transition(); //19 |
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| 197 | cache->transition(); //18 |
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| 198 | cache->transition(); //17 |
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| 199 | cache->transition(); //16 |
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| 200 | cache->transition(); //15 |
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| 201 | cache->transition(); //14 |
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| 202 | cache->transition(); //13 |
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| 203 | cache->transition(); //12 |
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| 204 | cache->transition(); //11 |
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| 205 | cache->transition(); //10 |
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[81] | 206 | // cout << *cache << endl; |
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[78] | 207 | |
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| 208 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 209 | cache->update_access(access); |
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| 210 | |
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| 211 | TEST(access.num_port , 0); |
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| 212 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 213 | TEST(access.latence , 10); |
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| 214 | TEST(access.last_nb_level, 0); |
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| 215 | |
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| 216 | cache->transition(); // 9 |
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| 217 | cache->transition(); // 8 |
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| 218 | cache->transition(); // 7 |
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| 219 | cache->transition(); // 6 |
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| 220 | cache->transition(); // 5 |
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| 221 | cache->transition(); // 4 |
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| 222 | cache->transition(); // 3 |
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| 223 | cache->transition(); // 2 |
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| 224 | |
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| 225 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 226 | cache->update_access(access); |
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| 227 | |
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| 228 | TEST(access.num_port , 0); |
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| 229 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 230 | TEST(access.latence , 2); |
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| 231 | TEST(access.last_nb_level, 0); |
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| 232 | |
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| 233 | cache->transition(); // 1 |
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| 234 | |
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| 235 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 236 | cache->update_access(access); |
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| 237 | |
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| 238 | TEST(access.num_port , 0); |
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| 239 | TEST(access.hit , HIT_CACHE); |
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| 240 | TEST(access.latence , 1); |
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| 241 | TEST(access.last_nb_level, 0); |
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[81] | 242 | // cout << *cache << endl; |
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[78] | 243 | |
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| 244 | cache->transition(); |
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| 245 | |
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| 246 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 247 | cache->update_access(access); |
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| 248 | |
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| 249 | TEST(access.num_port , 0); |
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| 250 | TEST(access.hit , HIT_CACHE); |
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| 251 | TEST(access.latence , 1); |
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| 252 | TEST(access.last_nb_level, 0); |
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| 253 | |
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| 254 | |
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| 255 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 256 | cache->update_access(access); |
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| 257 | |
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| 258 | TEST(access.num_port , 0); |
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| 259 | TEST(access.hit , HIT_CACHE); |
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| 260 | TEST(access.latence , 1); |
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| 261 | TEST(access.last_nb_level, 0); |
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| 262 | |
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| 263 | access = cache->access (1, 0x200, 0, CACHED, WRITE); |
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| 264 | cache->update_access(access); |
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| 265 | |
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| 266 | TEST(access.num_port , 1); |
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| 267 | TEST(access.hit , MISS); |
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| 268 | TEST(access.latence , 20); |
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| 269 | TEST(access.last_nb_level, 2); |
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| 270 | |
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| 271 | access = cache->access (2, 0x100, 0, CACHED, WRITE); |
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| 272 | cache->update_access(access); |
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| 273 | |
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| 274 | TEST(access.num_port , 2); |
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| 275 | TEST(access.hit , HIT_BYPASS); |
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| 276 | TEST(access.latence , 1); |
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| 277 | TEST(access.last_nb_level, 0); |
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| 278 | |
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| 279 | access = cache->access (3, 0x200, 0, CACHED, WRITE); |
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| 280 | cache->update_access(access); |
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| 281 | |
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| 282 | TEST(access.num_port , 3); |
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| 283 | TEST(access.hit , HIT_BYPASS); |
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| 284 | TEST(access.latence , 20); |
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| 285 | TEST(access.last_nb_level, 0); |
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| 286 | |
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| 287 | cache->transition(); //19 |
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| 288 | cache->transition(); //18 |
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| 289 | cache->transition(); //17 |
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| 290 | cache->transition(); //16 |
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| 291 | cache->transition(); //15 |
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| 292 | |
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| 293 | |
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| 294 | // access = cache->access (1, 0x300, 0, CACHED, WRITE); |
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| 295 | // cache->update_access(access); |
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| 296 | |
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| 297 | // TEST(access.num_port , 1); |
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| 298 | // TEST(access.hit , MISS); |
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| 299 | // TEST(access.latence , 20); |
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| 300 | // TEST(access.last_nb_level, 2); |
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| 301 | |
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| 302 | cache->transition(); //14 |
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| 303 | cache->transition(); //13 |
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| 304 | cache->transition(); //12 |
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| 305 | cache->transition(); //11 |
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| 306 | cache->transition(); //10 |
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[81] | 307 | // cout << *cache << endl; |
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[78] | 308 | |
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| 309 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 310 | cache->update_access(access); |
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| 311 | |
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| 312 | TEST(access.num_port , 0); |
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| 313 | TEST(access.hit , HIT_CACHE); |
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| 314 | TEST(access.latence , 1); |
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| 315 | TEST(access.last_nb_level, 0); |
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| 316 | |
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| 317 | access = cache->access (1, 0x200, 0, CACHED, WRITE); |
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| 318 | cache->update_access(access); |
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| 319 | |
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| 320 | TEST(access.num_port , 1); |
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| 321 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 322 | TEST(access.latence , 10); |
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| 323 | TEST(access.last_nb_level, 0); |
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| 324 | |
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| 325 | access = cache->access (2, 0x100, 0, CACHED, WRITE); |
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| 326 | cache->update_access(access); |
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| 327 | |
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| 328 | TEST(access.num_port , 2); |
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| 329 | TEST(access.hit , HIT_BYPASS); |
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| 330 | TEST(access.latence , 1); |
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| 331 | TEST(access.last_nb_level, 0); |
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| 332 | |
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| 333 | access = cache->access (3, 0x200, 0, CACHED, WRITE); |
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| 334 | cache->update_access(access); |
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| 335 | |
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| 336 | TEST(access.num_port , 3); |
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| 337 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 338 | TEST(access.latence , 10); |
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| 339 | TEST(access.last_nb_level, 0); |
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| 340 | |
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| 341 | cache->transition(); //9 |
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| 342 | |
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| 343 | access = cache->access (1, 0x400, 0, CACHED, WRITE); |
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| 344 | cache->update_access(access); |
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| 345 | |
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| 346 | TEST(access.num_port , 1); |
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| 347 | TEST(access.hit , MISS); |
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| 348 | TEST(access.latence , 20); |
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| 349 | TEST(access.last_nb_level, 2); |
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| 350 | |
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| 351 | cache->transition(); //8 |
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| 352 | cache->transition(); //7 |
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| 353 | cache->transition(); //6 |
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| 354 | cache->transition(); //5 |
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| 355 | cache->transition(); //4 |
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| 356 | cache->transition(); //3 |
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| 357 | cache->transition(); //2 |
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| 358 | cache->transition(); //1 |
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| 359 | cache->transition(); //0 |
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| 360 | |
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| 361 | access = cache->access (1, 0x100, 0, CACHED, WRITE); |
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[81] | 362 | // cout << access<< endl; |
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[78] | 363 | |
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| 364 | cache->update_access(access); |
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| 365 | |
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| 366 | TEST(access.num_port , 1); |
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| 367 | TEST(access.hit , HIT_CACHE); |
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| 368 | TEST(access.latence , 6 ); |
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| 369 | TEST(access.last_nb_level, 1); |
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| 370 | |
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[81] | 371 | // cout << *cache << endl; |
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[78] | 372 | delete cache; |
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| 373 | delete param; |
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| 374 | delete [] nb_line ; |
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| 375 | delete [] size_line ; |
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| 376 | delete [] size_word ; |
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| 377 | delete [] associativity; |
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| 378 | delete [] hit_latence ; |
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| 379 | delete [] miss_penality; |
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| 380 | } |
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| 381 | |
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| 382 | { |
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| 383 | uint32_t * cache_shared_nb_line = new uint32_t [1]; |
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| 384 | uint32_t * cache_shared_size_line = new uint32_t [1]; |
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| 385 | uint32_t * cache_shared_size_word = new uint32_t [1]; |
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| 386 | uint32_t * cache_shared_associativity = new uint32_t [1]; |
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| 387 | uint32_t * cache_shared_hit_latence = new uint32_t [1]; |
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| 388 | uint32_t * cache_shared_miss_penality = new uint32_t [1]; |
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| 389 | |
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| 390 | cache_shared_nb_line [0] = 8 ; |
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| 391 | cache_shared_size_line [0] = 8 ; |
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| 392 | cache_shared_size_word [0] = 4 ; |
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[81] | 393 | cache_shared_associativity [0] = 8 ; |
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[78] | 394 | cache_shared_hit_latence [0] = 2 ; |
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| 395 | cache_shared_miss_penality [0] = 5 ; |
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| 396 | |
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| 397 | uint32_t * icache_nb_level = new uint32_t [2]; |
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| 398 | uint32_t * icache_nb_port = new uint32_t [2]; |
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| 399 | uint32_t ** icache_nb_line = new uint32_t * [2]; |
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| 400 | uint32_t ** icache_size_line = new uint32_t * [2]; |
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| 401 | uint32_t ** icache_size_word = new uint32_t * [2]; |
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| 402 | uint32_t ** icache_associativity = new uint32_t * [2]; |
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| 403 | uint32_t ** icache_hit_latence = new uint32_t * [2]; |
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| 404 | uint32_t ** icache_miss_penality = new uint32_t * [2]; |
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| 405 | |
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| 406 | icache_nb_level [0] = 1; |
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| 407 | icache_nb_port [0] = 2; |
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| 408 | icache_nb_line [0] = new uint32_t [1]; |
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| 409 | icache_size_line [0] = new uint32_t [1]; |
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| 410 | icache_size_word [0] = new uint32_t [1]; |
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| 411 | icache_associativity [0] = new uint32_t [1]; |
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| 412 | icache_hit_latence [0] = new uint32_t [1]; |
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| 413 | icache_miss_penality [0] = new uint32_t [1]; |
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| 414 | |
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| 415 | icache_nb_line [0][0] = 8; |
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| 416 | icache_size_line [0][0] = 8; |
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| 417 | icache_size_word [0][0] = 4; |
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| 418 | icache_associativity [0][0] = 1; |
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| 419 | icache_hit_latence [0][0] = 1; |
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| 420 | icache_miss_penality [0][0] = 3; |
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| 421 | |
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| 422 | icache_nb_level [1] = 2; |
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| 423 | icache_nb_port [1] = 2; |
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| 424 | icache_nb_line [1] = new uint32_t [2]; |
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| 425 | icache_size_line [1] = new uint32_t [2]; |
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| 426 | icache_size_word [1] = new uint32_t [2]; |
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| 427 | icache_associativity [1] = new uint32_t [2]; |
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| 428 | icache_hit_latence [1] = new uint32_t [2]; |
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| 429 | icache_miss_penality [1] = new uint32_t [2]; |
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| 430 | |
---|
| 431 | icache_nb_line [1][0] = 4; |
---|
| 432 | icache_size_line [1][0] = 8; |
---|
| 433 | icache_size_word [1][0] = 4; |
---|
| 434 | icache_associativity [1][0] = 1; |
---|
| 435 | icache_hit_latence [1][0] = 1; |
---|
| 436 | icache_miss_penality [1][0] = 3; |
---|
| 437 | |
---|
| 438 | icache_nb_line [1][1] = 4; |
---|
| 439 | icache_size_line [1][1] = 8; |
---|
| 440 | icache_size_word [1][1] = 4; |
---|
| 441 | icache_associativity [1][1] = 4; |
---|
| 442 | icache_hit_latence [1][1] = 1; |
---|
| 443 | icache_miss_penality [1][1] = 4; |
---|
| 444 | |
---|
| 445 | uint32_t * dcache_nb_level = new uint32_t [2]; |
---|
| 446 | uint32_t * dcache_nb_port = new uint32_t [2]; |
---|
| 447 | uint32_t ** dcache_nb_line = new uint32_t * [2]; |
---|
| 448 | uint32_t ** dcache_size_line = new uint32_t * [2]; |
---|
| 449 | uint32_t ** dcache_size_word = new uint32_t * [2]; |
---|
| 450 | uint32_t ** dcache_associativity = new uint32_t * [2]; |
---|
| 451 | uint32_t ** dcache_hit_latence = new uint32_t * [2]; |
---|
| 452 | uint32_t ** dcache_miss_penality = new uint32_t * [2]; |
---|
| 453 | |
---|
| 454 | dcache_nb_level [0] = 1; |
---|
| 455 | dcache_nb_port [0] = 2; |
---|
| 456 | dcache_nb_line [0] = new uint32_t [1]; |
---|
| 457 | dcache_size_line [0] = new uint32_t [1]; |
---|
| 458 | dcache_size_word [0] = new uint32_t [1]; |
---|
| 459 | dcache_associativity [0] = new uint32_t [1]; |
---|
| 460 | dcache_hit_latence [0] = new uint32_t [1]; |
---|
| 461 | dcache_miss_penality [0] = new uint32_t [1]; |
---|
| 462 | |
---|
| 463 | dcache_nb_line [0][0] = 8; |
---|
| 464 | dcache_size_line [0][0] = 8; |
---|
| 465 | dcache_size_word [0][0] = 4; |
---|
| 466 | dcache_associativity [0][0] = 1; |
---|
| 467 | dcache_hit_latence [0][0] = 1; |
---|
| 468 | dcache_miss_penality [0][0] = 3; |
---|
| 469 | |
---|
| 470 | dcache_nb_level [1] = 2; |
---|
[81] | 471 | dcache_nb_port [1] = 8; // to test |
---|
[78] | 472 | dcache_nb_line [1] = new uint32_t [2]; |
---|
| 473 | dcache_size_line [1] = new uint32_t [2]; |
---|
| 474 | dcache_size_word [1] = new uint32_t [2]; |
---|
| 475 | dcache_associativity [1] = new uint32_t [2]; |
---|
| 476 | dcache_hit_latence [1] = new uint32_t [2]; |
---|
| 477 | dcache_miss_penality [1] = new uint32_t [2]; |
---|
| 478 | |
---|
| 479 | dcache_nb_line [1][0] = 4; |
---|
| 480 | dcache_size_line [1][0] = 8; |
---|
| 481 | dcache_size_word [1][0] = 4; |
---|
| 482 | dcache_associativity [1][0] = 1; |
---|
| 483 | dcache_hit_latence [1][0] = 1; |
---|
| 484 | dcache_miss_penality [1][0] = 3; |
---|
| 485 | |
---|
| 486 | dcache_nb_line [1][1] = 4; |
---|
| 487 | dcache_size_line [1][1] = 8; |
---|
| 488 | dcache_size_word [1][1] = 4; |
---|
| 489 | dcache_associativity [1][1] = 4; |
---|
| 490 | dcache_hit_latence [1][1] = 1; |
---|
| 491 | dcache_miss_penality [1][1] = 4; |
---|
| 492 | |
---|
| 493 | Parameters * param = new Parameters |
---|
| 494 | (2,//nb_cache_dedicated |
---|
| 495 | |
---|
| 496 | icache_nb_level , |
---|
| 497 | icache_nb_port , |
---|
| 498 | icache_nb_line , |
---|
| 499 | icache_size_line , |
---|
| 500 | icache_size_word , |
---|
| 501 | icache_associativity , |
---|
| 502 | icache_hit_latence , |
---|
| 503 | icache_miss_penality , |
---|
| 504 | |
---|
| 505 | dcache_nb_level , |
---|
| 506 | dcache_nb_port , |
---|
| 507 | dcache_nb_line , |
---|
| 508 | dcache_size_line , |
---|
| 509 | dcache_size_word , |
---|
| 510 | dcache_associativity , |
---|
| 511 | dcache_hit_latence , |
---|
| 512 | dcache_miss_penality , |
---|
| 513 | |
---|
| 514 | 1, // nb_level |
---|
| 515 | cache_shared_nb_line , |
---|
| 516 | cache_shared_size_line , |
---|
| 517 | cache_shared_size_word , |
---|
| 518 | cache_shared_associativity, |
---|
| 519 | cache_shared_hit_latence , |
---|
| 520 | cache_shared_miss_penality |
---|
| 521 | ); |
---|
| 522 | |
---|
[81] | 523 | // cout << *param << endl; |
---|
[78] | 524 | |
---|
| 525 | cache::Cache * cache = new cache::Cache ("my_cache",param); |
---|
| 526 | |
---|
| 527 | cache->reset(); |
---|
[81] | 528 | // cout << *cache << endl; |
---|
[78] | 529 | |
---|
| 530 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16); |
---|
| 531 | cache->transition(); |
---|
| 532 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15); |
---|
| 533 | cache->transition(); |
---|
[81] | 534 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 14); |
---|
| 535 | cache->transition(); |
---|
| 536 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 13); |
---|
| 537 | cache->transition(); |
---|
| 538 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 12); |
---|
| 539 | cache->transition(); |
---|
| 540 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11); |
---|
| 541 | cache->transition(); |
---|
| 542 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10); |
---|
| 543 | cache->transition(); |
---|
| 544 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 9); |
---|
| 545 | cache->transition(); |
---|
| 546 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 8); |
---|
| 547 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 16); // miss thread != |
---|
| 548 | TEST(cache->latence (DATA_CACHE, 0, 0, 0x100, 0, CACHED, WRITE), 6); // miss L1, hit L2 |
---|
| 549 | cache->transition(); |
---|
| 550 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 7); |
---|
| 551 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 15); |
---|
| 552 | cache->transition(); |
---|
| 553 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 6); |
---|
| 554 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 14); |
---|
| 555 | cache->transition(); |
---|
| 556 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); |
---|
| 557 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 13); |
---|
| 558 | cache->transition(); |
---|
| 559 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); |
---|
| 560 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 12); |
---|
| 561 | cache->transition(); |
---|
| 562 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); |
---|
| 563 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 11); |
---|
| 564 | cache->transition(); |
---|
| 565 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); |
---|
| 566 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 10); |
---|
| 567 | cache->transition(); |
---|
| 568 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 569 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 9); |
---|
| 570 | cache->transition(); |
---|
| 571 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 572 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 8); |
---|
| 573 | cache->transition(); |
---|
| 574 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 575 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 7); |
---|
| 576 | cache->transition(); |
---|
| 577 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 578 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 6); |
---|
| 579 | cache->transition(); |
---|
| 580 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 581 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); |
---|
| 582 | cache->transition(); |
---|
| 583 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 584 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); |
---|
| 585 | cache->transition(); |
---|
| 586 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 587 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); |
---|
| 588 | cache->transition(); |
---|
| 589 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 590 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); |
---|
| 591 | cache->transition(); |
---|
[78] | 592 | |
---|
[81] | 593 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); // L1 is direct map, hit L2 |
---|
| 594 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); // write in L1 |
---|
| 595 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 16); |
---|
| 596 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 16); |
---|
| 597 | cache->transition(); |
---|
| 598 | |
---|
| 599 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); |
---|
| 600 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 601 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 15); |
---|
| 602 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 15); |
---|
| 603 | cache->transition(); |
---|
| 604 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); |
---|
| 605 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 606 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 14); |
---|
| 607 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 14); |
---|
| 608 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 16); |
---|
| 609 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 16); |
---|
| 610 | cache->transition(); |
---|
| 611 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); |
---|
| 612 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 613 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 13); |
---|
| 614 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 13); |
---|
| 615 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 15); |
---|
| 616 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 15); |
---|
| 617 | |
---|
| 618 | |
---|
| 619 | cache->transition(); |
---|
| 620 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 621 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); |
---|
| 622 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 12); |
---|
| 623 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 12); |
---|
| 624 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 14); |
---|
| 625 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 14); |
---|
| 626 | |
---|
| 627 | |
---|
| 628 | cache->transition(); |
---|
| 629 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 630 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); |
---|
| 631 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 11); |
---|
| 632 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11); |
---|
| 633 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 13); |
---|
| 634 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 13); |
---|
| 635 | |
---|
| 636 | // in cache L2 : context 0,1,2,3 |
---|
| 637 | |
---|
| 638 | cache->transition(); |
---|
| 639 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 640 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); |
---|
| 641 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 10); |
---|
| 642 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10); |
---|
| 643 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 12); |
---|
| 644 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 12); |
---|
| 645 | |
---|
| 646 | cache->transition(); |
---|
| 647 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 648 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); |
---|
| 649 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 9); |
---|
| 650 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 9); |
---|
| 651 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 11); |
---|
| 652 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 11); |
---|
| 653 | |
---|
| 654 | cache->transition(); |
---|
| 655 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 5); |
---|
| 656 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 657 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 8); |
---|
| 658 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 8); |
---|
| 659 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 10); // write in L2 |
---|
| 660 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 10); // write in L2 |
---|
| 661 | |
---|
| 662 | cache->transition(); |
---|
| 663 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 4); |
---|
| 664 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 665 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 7); |
---|
| 666 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 7); |
---|
| 667 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 9); |
---|
| 668 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 9); |
---|
| 669 | |
---|
| 670 | cache->transition(); |
---|
| 671 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 3); |
---|
| 672 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 673 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 6); |
---|
| 674 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 6); |
---|
| 675 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 8); |
---|
| 676 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 8); |
---|
| 677 | |
---|
| 678 | cache->transition(); |
---|
| 679 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 2); |
---|
| 680 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 681 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 5); |
---|
| 682 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 5); |
---|
| 683 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 7); |
---|
| 684 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 7); |
---|
| 685 | |
---|
| 686 | cache->transition(); |
---|
| 687 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 688 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 5); |
---|
| 689 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 4); |
---|
| 690 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 4); |
---|
| 691 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 6); |
---|
| 692 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 6); |
---|
| 693 | |
---|
| 694 | cache->transition(); |
---|
| 695 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 696 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 4); |
---|
| 697 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 3); |
---|
| 698 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 3); |
---|
| 699 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 5); |
---|
| 700 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 5); |
---|
| 701 | |
---|
| 702 | cache->transition(); |
---|
| 703 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 1); |
---|
| 704 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 3); |
---|
| 705 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 2); |
---|
| 706 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 2); |
---|
| 707 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 4); |
---|
| 708 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 4); |
---|
| 709 | |
---|
[78] | 710 | cout << *cache << endl; |
---|
| 711 | |
---|
[81] | 712 | cache->transition(); |
---|
| 713 | // In L2 : context 1,2,4,5 : also context 0 and 3 miss L1 and L2, hit L3 |
---|
| 714 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 11); |
---|
| 715 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 2); |
---|
| 716 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 1); |
---|
| 717 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 11); |
---|
| 718 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 3); |
---|
| 719 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 3); |
---|
[78] | 720 | |
---|
[81] | 721 | cache->transition(); |
---|
| 722 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 10); |
---|
| 723 | TEST(cache->latence (DATA_CACHE, 1, 1, 0x100, 1, CACHED, WRITE), 1); |
---|
| 724 | TEST(cache->latence (DATA_CACHE, 1, 2, 0x100, 2, CACHED, WRITE), 5); |
---|
| 725 | TEST(cache->latence (DATA_CACHE, 1, 3, 0x100, 3, CACHED, WRITE), 10); |
---|
| 726 | TEST(cache->latence (DATA_CACHE, 1, 4, 0x100, 4, CACHED, WRITE), 2); |
---|
| 727 | TEST(cache->latence (DATA_CACHE, 1, 5, 0x100, 5, CACHED, WRITE), 2); |
---|
| 728 | |
---|
| 729 | // // cout << *cache << endl; |
---|
| 730 | |
---|
[78] | 731 | delete cache; |
---|
[81] | 732 | |
---|
[78] | 733 | delete param; |
---|
| 734 | delete [] cache_shared_nb_line ; |
---|
| 735 | delete [] cache_shared_size_line ; |
---|
| 736 | delete [] cache_shared_size_word ; |
---|
| 737 | delete [] cache_shared_associativity; |
---|
| 738 | delete [] cache_shared_hit_latence ; |
---|
| 739 | delete [] cache_shared_miss_penality; |
---|
| 740 | delete [] icache_nb_level ; |
---|
| 741 | delete [] icache_nb_port ; |
---|
| 742 | delete [] icache_nb_line [0]; |
---|
| 743 | delete [] icache_size_line [0]; |
---|
| 744 | delete [] icache_size_word [0]; |
---|
| 745 | delete [] icache_associativity [0]; |
---|
| 746 | delete [] icache_hit_latence [0]; |
---|
| 747 | delete [] icache_miss_penality [0]; |
---|
| 748 | delete [] icache_nb_line [1]; |
---|
| 749 | delete [] icache_size_line [1]; |
---|
| 750 | delete [] icache_size_word [1]; |
---|
| 751 | delete [] icache_associativity [1]; |
---|
| 752 | delete [] icache_hit_latence [1]; |
---|
| 753 | delete [] icache_miss_penality [1]; |
---|
| 754 | delete [] icache_nb_line ; |
---|
| 755 | delete [] icache_size_line ; |
---|
| 756 | delete [] icache_size_word ; |
---|
| 757 | delete [] icache_associativity ; |
---|
| 758 | delete [] icache_hit_latence ; |
---|
| 759 | delete [] icache_miss_penality ; |
---|
| 760 | delete [] dcache_nb_level ; |
---|
| 761 | delete [] dcache_nb_port ; |
---|
| 762 | delete [] dcache_nb_line [0]; |
---|
| 763 | delete [] dcache_size_line [0]; |
---|
| 764 | delete [] dcache_size_word [0]; |
---|
| 765 | delete [] dcache_associativity [0]; |
---|
| 766 | delete [] dcache_hit_latence [0]; |
---|
| 767 | delete [] dcache_miss_penality [0]; |
---|
| 768 | delete [] dcache_nb_line [1]; |
---|
| 769 | delete [] dcache_size_line [1]; |
---|
| 770 | delete [] dcache_size_word [1]; |
---|
| 771 | delete [] dcache_associativity [1]; |
---|
| 772 | delete [] dcache_hit_latence [1]; |
---|
| 773 | delete [] dcache_miss_penality [1]; |
---|
| 774 | delete [] dcache_nb_line ; |
---|
| 775 | delete [] dcache_size_line ; |
---|
| 776 | delete [] dcache_size_word ; |
---|
| 777 | delete [] dcache_associativity ; |
---|
| 778 | delete [] dcache_hit_latence ; |
---|
| 779 | delete [] dcache_miss_penality ; |
---|
| 780 | } |
---|
| 781 | |
---|
| 782 | cout << "<main> End" << endl; |
---|
| 783 | |
---|
| 784 | return EXIT_SUCCESS; |
---|
| 785 | } |
---|