1 | #include "../include/Cache_OneLevel.h" |
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2 | |
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3 | namespace environment { |
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4 | namespace cache { |
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5 | namespace cache_onelevel { |
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6 | |
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7 | type_rsp_cache_t Cache_OneLevel::access_cached (uint32_t num_port, uint32_t address, uint32_t trdid, direction_req_cache_t dir) |
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8 | { |
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9 | Address address_translate = translate_address(address); |
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10 | uint32_t num_associativity = hit_cache (trdid, address_translate); |
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11 | uint32_t num_access_port = hit_access_port (trdid, address_translate); |
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12 | uint32_t num_write_buffer = hit_write_buffer (trdid, address_translate); |
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13 | |
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14 | if (num_access_port == param->nb_port) |
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15 | num_access_port = num_port; |
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16 | |
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17 | uint32_t latence ; |
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18 | type_rsp_cache_t res = MISS; |
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19 | |
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20 | bool is_in_cache = (num_associativity != param->associativity); |
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21 | bool is_in_access_port = (num_access_port != num_port); |
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22 | bool is_in_write_buffer = false; |
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23 | |
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24 | if (is_in_access_port == true) |
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25 | { |
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26 | res = HIT_BYPASS; |
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27 | latence = access_port[num_access_port].latence; //already compute |
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28 | } |
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29 | else |
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30 | if (is_in_cache == true) |
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31 | { |
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32 | res = HIT_CACHE; |
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33 | latence = 0; // Hit !!! |
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34 | } |
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35 | else |
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36 | { |
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37 | |
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38 | // Search in the write buffer, and test if have a miss |
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39 | if ( num_write_buffer == write_buffer->nb_slot_use()) |
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40 | { |
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41 | res = MISS; |
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42 | latence = param->miss_penality; // miss -> access at down of cache, + respons at the up of cache |
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43 | } |
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44 | else |
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45 | { |
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46 | res = HIT_WRITE_BUFFER; |
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47 | is_in_write_buffer = true; |
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48 | latence = write_buffer->read(num_write_buffer)._delay; |
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49 | } |
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50 | } |
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51 | |
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52 | // access_port valid = there are a new request to update |
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53 | // -> no previous request in the same cycle (hit in a access port) |
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54 | // -> no previous request in the previous cycle (hit in the write buffer) |
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55 | |
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56 | access_port[num_port].valid = ((is_in_access_port || is_in_write_buffer) == false); |
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57 | access_port[num_port].address = address_translate; |
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58 | access_port[num_port].trdid = trdid; |
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59 | access_port[num_port].hit = res; |
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60 | access_port[num_port].num_associativity = num_associativity; |
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61 | access_port[num_port].latence = latence; |
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62 | |
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63 | return res; |
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64 | } |
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65 | |
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66 | }; |
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67 | }; |
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68 | }; |
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