| 1 | |
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| 2 | bin/soft.x: file format elf32-or32 |
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| 3 | |
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| 4 | Disassembly of section .text: |
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| 5 | |
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| 6 | 00000000 <_exception_reset-0x100>: |
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| 7 | 0: 15 00 00 00 l.nop 0x0 |
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| 8 | 4: 15 00 ff ff l.nop 0xffff |
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| 9 | 8: 15 00 ff fe l.nop 0xfffe |
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| 10 | c: 15 00 ff fd l.nop 0xfffd |
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| 11 | 10: 15 00 ff fc l.nop 0xfffc |
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| 12 | 14: 15 00 ff fb l.nop 0xfffb |
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| 13 | 18: 15 00 ff fa l.nop 0xfffa |
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| 14 | 1c: 15 00 ff f9 l.nop 0xfff9 |
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| 15 | 20: 15 00 ff f8 l.nop 0xfff8 |
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| 16 | 24: 15 00 ff f7 l.nop 0xfff7 |
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| 17 | 28: 15 00 ff f6 l.nop 0xfff6 |
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| 18 | 2c: 15 00 ff f5 l.nop 0xfff5 |
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| 19 | 30: 15 00 ff f4 l.nop 0xfff4 |
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| 20 | 34: 15 00 ff f3 l.nop 0xfff3 |
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| 21 | 38: 15 00 ff f2 l.nop 0xfff2 |
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| 22 | 3c: 15 00 ff f1 l.nop 0xfff1 |
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| 23 | 40: 15 00 ff f0 l.nop 0xfff0 |
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| 24 | 44: 15 00 ff ef l.nop 0xffef |
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| 25 | 48: 15 00 ff ee l.nop 0xffee |
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| 26 | 4c: 15 00 ff ed l.nop 0xffed |
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| 27 | 50: 15 00 ff ec l.nop 0xffec |
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| 28 | 54: 15 00 ff eb l.nop 0xffeb |
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| 29 | 58: 15 00 ff ea l.nop 0xffea |
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| 30 | 5c: 15 00 ff e9 l.nop 0xffe9 |
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| 31 | 60: 15 00 ff e8 l.nop 0xffe8 |
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| 32 | 64: 15 00 ff e7 l.nop 0xffe7 |
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| 33 | 68: 15 00 ff e6 l.nop 0xffe6 |
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| 34 | 6c: 15 00 ff e5 l.nop 0xffe5 |
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| 35 | 70: 15 00 ff e4 l.nop 0xffe4 |
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| 36 | 74: 15 00 ff e3 l.nop 0xffe3 |
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| 37 | 78: 15 00 ff e2 l.nop 0xffe2 |
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| 38 | 7c: 15 00 ff e1 l.nop 0xffe1 |
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| 39 | 80: 15 00 ff e0 l.nop 0xffe0 |
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| 40 | 84: 15 00 ff df l.nop 0xffdf |
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| 41 | 88: 15 00 ff de l.nop 0xffde |
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| 42 | 8c: 15 00 ff dd l.nop 0xffdd |
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| 43 | 90: 15 00 ff dc l.nop 0xffdc |
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| 44 | 94: 15 00 ff db l.nop 0xffdb |
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| 45 | 98: 15 00 ff da l.nop 0xffda |
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| 46 | 9c: 15 00 ff d9 l.nop 0xffd9 |
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| 47 | a0: 15 00 ff d8 l.nop 0xffd8 |
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| 48 | a4: 15 00 ff d7 l.nop 0xffd7 |
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| 49 | a8: 15 00 ff d6 l.nop 0xffd6 |
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| 50 | ac: 15 00 ff d5 l.nop 0xffd5 |
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| 51 | b0: 15 00 ff d4 l.nop 0xffd4 |
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| 52 | b4: 15 00 ff d3 l.nop 0xffd3 |
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| 53 | b8: 15 00 ff d2 l.nop 0xffd2 |
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| 54 | bc: 15 00 ff d1 l.nop 0xffd1 |
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| 55 | c0: 15 00 ff d0 l.nop 0xffd0 |
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| 56 | c4: 15 00 ff cf l.nop 0xffcf |
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| 57 | c8: 15 00 ff ce l.nop 0xffce |
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| 58 | cc: 15 00 ff cd l.nop 0xffcd |
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| 59 | d0: 15 00 ff cc l.nop 0xffcc |
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| 60 | d4: 15 00 ff cb l.nop 0xffcb |
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| 61 | d8: 15 00 ff ca l.nop 0xffca |
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| 62 | dc: 15 00 ff c9 l.nop 0xffc9 |
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| 63 | e0: 15 00 ff c8 l.nop 0xffc8 |
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| 64 | e4: 15 00 ff c7 l.nop 0xffc7 |
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| 65 | e8: 15 00 ff c6 l.nop 0xffc6 |
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| 66 | ec: 15 00 ff c5 l.nop 0xffc5 |
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| 67 | f0: 15 00 ff c4 l.nop 0xffc4 |
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| 68 | f4: 15 00 ff c3 l.nop 0xffc3 |
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| 69 | f8: 15 00 ff c2 l.nop 0xffc2 |
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| 70 | fc: 15 00 ff c1 l.nop 0xffc1 |
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| 71 | |
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| 72 | 00000100 <_exception_reset>: |
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| 73 | 100: 18 40 00 00 l.movhi r2,0x0 |
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| 74 | 104: a8 42 20 00 l.ori r2,r2,0x2000 |
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| 75 | 108: 44 00 10 00 l.jr r2 |
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| 76 | 10c: 15 00 00 00 l.nop 0x0 |
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| 77 | ... |
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| 78 | 200: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 79 | 204: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 80 | 208: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 81 | 20c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 82 | 210: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 83 | 214: 00 00 07 88 l.j 2034 <default_exception_handler> |
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| 84 | 218: 15 00 00 00 l.nop 0x0 |
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| 85 | ... |
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| 86 | 300: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 87 | 304: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 88 | 308: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 89 | 30c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 90 | 310: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 91 | 314: 00 00 07 48 l.j 2034 <default_exception_handler> |
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| 92 | 318: 15 00 00 00 l.nop 0x0 |
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| 93 | ... |
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| 94 | 400: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 95 | 404: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 96 | 408: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 97 | 40c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 98 | 410: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 99 | 414: 00 00 07 08 l.j 2034 <default_exception_handler> |
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| 100 | 418: 15 00 00 00 l.nop 0x0 |
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| 101 | ... |
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| 102 | 500: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 103 | 504: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 104 | 508: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 105 | 50c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 106 | 510: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 107 | 514: 00 00 06 c8 l.j 2034 <default_exception_handler> |
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| 108 | 518: 15 00 00 00 l.nop 0x0 |
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| 109 | ... |
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| 110 | 600: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 111 | 604: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 112 | 608: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 113 | 60c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 114 | 610: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 115 | 614: 00 00 06 88 l.j 2034 <default_exception_handler> |
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| 116 | 618: 15 00 00 00 l.nop 0x0 |
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| 117 | ... |
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| 118 | 700: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 119 | 704: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 120 | 708: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 121 | 70c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 122 | 710: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 123 | 714: 00 00 06 48 l.j 2034 <default_exception_handler> |
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| 124 | 718: 15 00 00 00 l.nop 0x0 |
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| 125 | ... |
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| 126 | 800: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 127 | 804: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 128 | 808: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 129 | 80c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 130 | 810: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 131 | 814: 00 00 06 08 l.j 2034 <default_exception_handler> |
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| 132 | 818: 15 00 00 00 l.nop 0x0 |
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| 133 | ... |
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| 134 | 900: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 135 | 904: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 136 | 908: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 137 | 90c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 138 | 910: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 139 | 914: 00 00 05 c8 l.j 2034 <default_exception_handler> |
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| 140 | 918: 15 00 00 00 l.nop 0x0 |
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| 141 | ... |
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| 142 | a00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 143 | a04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 144 | a08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 145 | a0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 146 | a10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 147 | a14: 00 00 05 88 l.j 2034 <default_exception_handler> |
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| 148 | a18: 15 00 00 00 l.nop 0x0 |
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| 149 | ... |
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| 150 | b00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 151 | b04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 152 | b08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 153 | b0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 154 | b10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 155 | b14: 00 00 05 48 l.j 2034 <default_exception_handler> |
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| 156 | b18: 15 00 00 00 l.nop 0x0 |
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| 157 | ... |
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| 158 | c00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 159 | c04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 160 | c08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 161 | c0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 162 | c10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 163 | c14: 00 00 05 08 l.j 2034 <default_exception_handler> |
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| 164 | c18: 15 00 00 00 l.nop 0x0 |
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| 165 | ... |
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| 166 | d00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 167 | d04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 168 | d08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 169 | d0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 170 | d10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 171 | d14: 00 00 04 c8 l.j 2034 <default_exception_handler> |
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| 172 | d18: 15 00 00 00 l.nop 0x0 |
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| 173 | ... |
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| 174 | e00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 175 | e04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 176 | e08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 177 | e0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 178 | e10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 179 | e14: 00 00 04 88 l.j 2034 <default_exception_handler> |
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| 180 | e18: 15 00 00 00 l.nop 0x0 |
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| 181 | ... |
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| 182 | f00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 183 | f04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 184 | f08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 185 | f0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 186 | f10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 187 | f14: 00 00 04 48 l.j 2034 <default_exception_handler> |
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| 188 | f18: 15 00 00 00 l.nop 0x0 |
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| 189 | ... |
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| 190 | 1000: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 191 | 1004: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 192 | 1008: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 193 | 100c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 194 | 1010: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 195 | 1014: 00 00 04 08 l.j 2034 <default_exception_handler> |
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| 196 | 1018: 15 00 00 00 l.nop 0x0 |
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| 197 | ... |
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| 198 | 1100: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 199 | 1104: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 200 | 1108: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 201 | 110c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 202 | 1110: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 203 | 1114: 00 00 03 c8 l.j 2034 <default_exception_handler> |
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| 204 | 1118: 15 00 00 00 l.nop 0x0 |
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| 205 | ... |
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| 206 | 1200: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 207 | 1204: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 208 | 1208: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 209 | 120c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 210 | 1210: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 211 | 1214: 00 00 03 88 l.j 2034 <default_exception_handler> |
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| 212 | 1218: 15 00 00 00 l.nop 0x0 |
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| 213 | ... |
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| 214 | 1300: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 215 | 1304: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 216 | 1308: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 217 | 130c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 218 | 1310: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 219 | 1314: 00 00 03 48 l.j 2034 <default_exception_handler> |
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| 220 | 1318: 15 00 00 00 l.nop 0x0 |
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| 221 | ... |
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| 222 | 1400: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 223 | 1404: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 224 | 1408: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 225 | 140c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 226 | 1410: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 227 | 1414: 00 00 03 08 l.j 2034 <default_exception_handler> |
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| 228 | 1418: 15 00 00 00 l.nop 0x0 |
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| 229 | ... |
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| 230 | 1500: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 231 | 1504: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 232 | 1508: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 233 | 150c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 234 | 1510: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 235 | 1514: 00 00 02 c8 l.j 2034 <default_exception_handler> |
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| 236 | 1518: 15 00 00 00 l.nop 0x0 |
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| 237 | ... |
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| 238 | 1600: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 239 | 1604: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 240 | 1608: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 241 | 160c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 242 | 1610: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 243 | 1614: 00 00 02 88 l.j 2034 <default_exception_handler> |
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| 244 | 1618: 15 00 00 00 l.nop 0x0 |
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| 245 | ... |
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| 246 | 1700: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 247 | 1704: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 248 | 1708: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 249 | 170c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 250 | 1710: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 251 | 1714: 00 00 02 48 l.j 2034 <default_exception_handler> |
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| 252 | 1718: 15 00 00 00 l.nop 0x0 |
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| 253 | ... |
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| 254 | 1800: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 255 | 1804: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 256 | 1808: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 257 | 180c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 258 | 1810: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 259 | 1814: 00 00 02 08 l.j 2034 <default_exception_handler> |
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| 260 | 1818: 15 00 00 00 l.nop 0x0 |
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| 261 | ... |
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| 262 | 1900: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 263 | 1904: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 264 | 1908: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 265 | 190c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 266 | 1910: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 267 | 1914: 00 00 01 c8 l.j 2034 <default_exception_handler> |
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| 268 | 1918: 15 00 00 00 l.nop 0x0 |
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| 269 | ... |
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| 270 | 1a00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 271 | 1a04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 272 | 1a08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 273 | 1a0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 274 | 1a10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 275 | 1a14: 00 00 01 88 l.j 2034 <default_exception_handler> |
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| 276 | 1a18: 15 00 00 00 l.nop 0x0 |
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| 277 | ... |
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| 278 | 1b00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 279 | 1b04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 280 | 1b08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 281 | 1b0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 282 | 1b10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 283 | 1b14: 00 00 01 48 l.j 2034 <default_exception_handler> |
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| 284 | 1b18: 15 00 00 00 l.nop 0x0 |
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| 285 | ... |
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| 286 | 1c00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 287 | 1c04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 288 | 1c08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 289 | 1c0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 290 | 1c10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 291 | 1c14: 00 00 01 08 l.j 2034 <default_exception_handler> |
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| 292 | 1c18: 15 00 00 00 l.nop 0x0 |
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| 293 | ... |
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| 294 | 1d00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 295 | 1d04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 296 | 1d08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 297 | 1d0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 298 | 1d10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 299 | 1d14: 00 00 00 c8 l.j 2034 <default_exception_handler> |
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| 300 | 1d18: 15 00 00 00 l.nop 0x0 |
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| 301 | ... |
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| 302 | 1e00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 303 | 1e04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 304 | 1e08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 305 | 1e0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 306 | 1e10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 307 | 1e14: 00 00 00 88 l.j 2034 <default_exception_handler> |
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| 308 | 1e18: 15 00 00 00 l.nop 0x0 |
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| 309 | ... |
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| 310 | 1f00: 9c 21 ff 80 l.addi r1,r1,0xffffff80 |
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| 311 | 1f04: d4 01 18 04 l.sw 0x4(r1),r3 |
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| 312 | 1f08: d4 01 20 08 l.sw 0x8(r1),r4 |
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| 313 | 1f0c: b4 60 00 10 l.mfspr r3,r0,0x10 |
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| 314 | 1f10: b4 80 00 20 l.mfspr r4,r0,0x20 |
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| 315 | 1f14: 00 00 00 48 l.j 2034 <default_exception_handler> |
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| 316 | 1f18: 15 00 00 00 l.nop 0x0 |
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| 317 | ... |
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| 318 | |
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| 319 | 00002000 <_start>: |
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| 320 | 2000: 18 20 51 ff l.movhi r1,0x51ff |
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| 321 | 2004: a8 21 ff fc l.ori r1,r1,0xfffc |
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| 322 | 2008: 9c 40 ff fd l.addi r2,r0,0xfffffffd |
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| 323 | 200c: 04 00 00 4b l.jal 2138 <_get_cpu_id> |
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| 324 | 2010: e0 21 10 03 l.and r1,r1,r2 |
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| 325 | 2014: 18 80 00 50 l.movhi r4,0x50 |
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| 326 | 2018: a8 84 00 00 l.ori r4,r4,0x0 |
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| 327 | 201c: e0 8b 23 06 l.mul r4,r11,r4 |
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| 328 | 2020: e0 21 20 02 l.sub r1,r1,r4 |
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| 329 | 2024: e0 41 00 04 l.or r2,r1,r0 |
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| 330 | 2028: e0 60 00 03 l.and r3,r0,r0 |
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| 331 | 202c: 04 00 00 51 l.jal 2170 <_main> |
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| 332 | 2030: e0 80 00 03 l.and r4,r0,r0 |
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| 333 | |
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| 334 | 00002034 <default_exception_handler>: |
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| 335 | 2034: d4 01 10 00 l.sw 0x0(r1),r2 |
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| 336 | 2038: d4 01 28 0c l.sw 0xc(r1),r5 |
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| 337 | 203c: d4 01 30 10 l.sw 0x10(r1),r6 |
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| 338 | 2040: d4 01 38 14 l.sw 0x14(r1),r7 |
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| 339 | 2044: d4 01 40 18 l.sw 0x18(r1),r8 |
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| 340 | 2048: d4 01 48 1c l.sw 0x1c(r1),r9 |
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| 341 | 204c: d4 01 50 20 l.sw 0x20(r1),r10 |
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| 342 | 2050: d4 01 58 24 l.sw 0x24(r1),r11 |
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| 343 | 2054: d4 01 60 28 l.sw 0x28(r1),r12 |
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| 344 | 2058: d4 01 68 2c l.sw 0x2c(r1),r13 |
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| 345 | 205c: d4 01 70 30 l.sw 0x30(r1),r14 |
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| 346 | 2060: d4 01 78 34 l.sw 0x34(r1),r15 |
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| 347 | 2064: d4 01 80 38 l.sw 0x38(r1),r16 |
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| 348 | 2068: d4 01 88 3c l.sw 0x3c(r1),r17 |
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| 349 | 206c: d4 01 90 40 l.sw 0x40(r1),r18 |
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| 350 | 2070: d4 01 98 44 l.sw 0x44(r1),r19 |
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| 351 | 2074: d4 01 a0 48 l.sw 0x48(r1),r20 |
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| 352 | 2078: d4 01 a8 4c l.sw 0x4c(r1),r21 |
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| 353 | 207c: d4 01 b0 50 l.sw 0x50(r1),r22 |
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| 354 | 2080: d4 01 b8 54 l.sw 0x54(r1),r23 |
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| 355 | 2084: d4 01 c0 58 l.sw 0x58(r1),r24 |
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| 356 | 2088: d4 01 c8 5c l.sw 0x5c(r1),r25 |
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| 357 | 208c: d4 01 d0 60 l.sw 0x60(r1),r26 |
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| 358 | 2090: d4 01 d8 64 l.sw 0x64(r1),r27 |
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| 359 | 2094: d4 01 e0 68 l.sw 0x68(r1),r28 |
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| 360 | 2098: d4 01 e8 6c l.sw 0x6c(r1),r29 |
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| 361 | 209c: d4 01 f0 70 l.sw 0x70(r1),r30 |
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| 362 | 20a0: d4 01 f8 74 l.sw 0x74(r1),r31 |
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| 363 | 20a4: d4 01 00 78 l.sw 0x78(r1),r0 |
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| 364 | 20a8: 07 ff f7 d6 l.jal 0 <_exception_reset-0x100> |
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| 365 | 20ac: 15 00 00 00 l.nop 0x0 |
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| 366 | 20b0: 84 41 00 00 l.lwz r2,0x0(r1) |
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| 367 | 20b4: 84 61 00 04 l.lwz r3,0x4(r1) |
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| 368 | 20b8: 84 81 00 08 l.lwz r4,0x8(r1) |
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| 369 | 20bc: 84 a1 00 0c l.lwz r5,0xc(r1) |
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| 370 | 20c0: 84 c1 00 10 l.lwz r6,0x10(r1) |
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| 371 | 20c4: 84 e1 00 14 l.lwz r7,0x14(r1) |
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| 372 | 20c8: 85 01 00 18 l.lwz r8,0x18(r1) |
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| 373 | 20cc: 85 21 00 1c l.lwz r9,0x1c(r1) |
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| 374 | 20d0: 85 41 00 20 l.lwz r10,0x20(r1) |
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| 375 | 20d4: 85 61 00 24 l.lwz r11,0x24(r1) |
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| 376 | 20d8: 85 81 00 28 l.lwz r12,0x28(r1) |
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| 377 | 20dc: 85 a1 00 2c l.lwz r13,0x2c(r1) |
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| 378 | 20e0: 85 c1 00 30 l.lwz r14,0x30(r1) |
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| 379 | 20e4: 85 e1 00 34 l.lwz r15,0x34(r1) |
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| 380 | 20e8: 86 01 00 38 l.lwz r16,0x38(r1) |
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| 381 | 20ec: 86 21 00 3c l.lwz r17,0x3c(r1) |
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| 382 | 20f0: 86 41 00 40 l.lwz r18,0x40(r1) |
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| 383 | 20f4: 86 61 00 44 l.lwz r19,0x44(r1) |
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| 384 | 20f8: 86 81 00 48 l.lwz r20,0x48(r1) |
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| 385 | 20fc: 86 a1 00 4c l.lwz r21,0x4c(r1) |
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| 386 | 2100: 86 c1 00 50 l.lwz r22,0x50(r1) |
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| 387 | 2104: 86 e1 00 54 l.lwz r23,0x54(r1) |
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| 388 | 2108: 87 01 00 58 l.lwz r24,0x58(r1) |
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| 389 | 210c: 87 21 00 5c l.lwz r25,0x5c(r1) |
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| 390 | 2110: 87 41 00 60 l.lwz r26,0x60(r1) |
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| 391 | 2114: 87 61 00 64 l.lwz r27,0x64(r1) |
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| 392 | 2118: 87 81 00 68 l.lwz r28,0x68(r1) |
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| 393 | 211c: 87 a1 00 6c l.lwz r29,0x6c(r1) |
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| 394 | 2120: 87 c1 00 70 l.lwz r30,0x70(r1) |
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| 395 | 2124: 87 e1 00 74 l.lwz r31,0x74(r1) |
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| 396 | 2128: 84 01 00 78 l.lwz r0,0x78(r1) |
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| 397 | 212c: 9c 21 00 80 l.addi r1,r1,0x80 |
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| 398 | 2130: 24 00 00 00 l.rfe |
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| 399 | 2134: 15 00 00 00 l.nop 0x0 |
|---|
| 400 | |
|---|
| 401 | 00002138 <_get_cpu_id>: |
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| 402 | 2138: 44 00 48 00 l.jr r9 |
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| 403 | 213c: b5 60 f8 00 l.mfspr r11,r0,0xf800 |
|---|
| 404 | |
|---|
| 405 | 00002140 <_set_cpu_id>: |
|---|
| 406 | 2140: 44 00 48 00 l.jr r9 |
|---|
| 407 | 2144: c3 e0 18 00 l.mtspr r0,r3,0xf800 |
|---|
| 408 | |
|---|
| 409 | 00002148 <_find_first_one>: |
|---|
| 410 | 2148: 44 00 48 00 l.jr r9 |
|---|
| 411 | 214c: e1 63 00 0f l.ff1 r11,r3 |
|---|
| 412 | |
|---|
| 413 | 00002150 <_get_thread_id>: |
|---|
| 414 | 2150: 44 00 48 00 l.jr r9 |
|---|
| 415 | 2154: b5 60 f8 01 l.mfspr r11,r0,0xf801 |
|---|
| 416 | |
|---|
| 417 | 00002158 <_set_thread_id>: |
|---|
| 418 | 2158: 44 00 48 00 l.jr r9 |
|---|
| 419 | 215c: c3 e0 18 01 l.mtspr r0,r3,0xf801 |
|---|
| 420 | |
|---|
| 421 | 00002160 <_get_thread_priority>: |
|---|
| 422 | 2160: 44 00 48 00 l.jr r9 |
|---|
| 423 | 2164: b5 60 f8 02 l.mfspr r11,r0,0xf802 |
|---|
| 424 | |
|---|
| 425 | 00002168 <_set_thread_priority>: |
|---|
| 426 | 2168: 44 00 48 00 l.jr r9 |
|---|
| 427 | 216c: c3 e0 18 02 l.mtspr r0,r3,0xf802 |
|---|
| 428 | |
|---|
| 429 | 00002170 <_main>: |
|---|
| 430 | 2170: 00 00 00 00 l.j 2170 <_main> |
|---|
| 431 | 2174: 15 00 00 00 l.nop 0x0 |
|---|
| 432 | 2178: 44 00 48 00 l.jr r9 |
|---|
| 433 | 217c: 15 00 00 00 l.nop 0x0 |
|---|
