[81] | 1 | #ifndef ENVIRONMENT_PARAMETERS_H |
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| 2 | #define ENVIRONMENT_PARAMETERS_H |
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| 3 | |
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| 4 | #include "../Cache/include/Cache_Parameters.h" |
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| 5 | #include "../Data/include/Data_Parameters.h" |
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| 6 | #include "../Queue/include/Parameters.h" |
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| 7 | #include "../TTY/include/TTY_Parameters.h" |
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| 8 | #include "../RamLock/include/RamLock_Parameters.h" |
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| 9 | #include "../Sim2OS/include/Sim2OS_Parameters.h" |
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| 10 | |
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| 11 | namespace environment { |
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| 12 | |
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| 13 | class Parameters |
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| 14 | { |
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| 15 | public : uint32_t nb_iport; |
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| 16 | public : uint32_t nb_dport; |
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| 17 | public : uint32_t nb_entity; |
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| 18 | public : uint32_t * icache_dedicated_nb_port; |
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| 19 | public : uint32_t * dcache_dedicated_nb_port; |
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| 20 | |
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| 21 | public : uint32_t * iaccess_nb_context ; |
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| 22 | public : uint32_t * iaccess_nb_packet ; |
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| 23 | public : uint32_t * iaccess_size_address ; |
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| 24 | public : uint32_t * iaccess_nb_instruction; |
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| 25 | public : uint32_t * iaccess_size_instruction; |
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| 26 | |
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| 27 | public : uint32_t * daccess_nb_context ; |
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| 28 | public : uint32_t * daccess_nb_packet ; |
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| 29 | public : uint32_t * daccess_size_address ; |
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| 30 | public : uint32_t * daccess_size_data ; |
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| 31 | |
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| 32 | // Parameters cache |
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| 33 | public : cache::Parameters * param_cache; |
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| 34 | // Parameters tty |
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| 35 | public : uint32_t nb_component_tty; |
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| 36 | public : uint32_t * tty_address; |
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| 37 | public : tty::Parameters ** param_tty; |
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| 38 | // Parameters ramlock |
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| 39 | public : uint32_t nb_component_ramlock; |
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| 40 | public : uint32_t * ramlock_address; |
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| 41 | public : ramlock::Parameters ** param_ramlock; |
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| 42 | // Parameters sim2OS |
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| 43 | public : uint32_t sim2os_address; |
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| 44 | public : uint32_t sim2os_size; |
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| 45 | public : sim2os::Parameters * param_sim2os; |
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| 46 | // Parameters data |
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| 47 | public : data::Parameters * param_data; |
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| 48 | |
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| 49 | // Parameters buffer_respons |
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| 50 | public : queue::Parameters ** param_buffer_irsp; |
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| 51 | public : queue::Parameters ** param_buffer_drsp; |
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| 52 | |
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| 53 | public : Parameters (// General |
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| 54 | uint32_t nb_cache_dedicated, |
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| 55 | |
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| 56 | uint32_t * iaccess_nb_context, |
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| 57 | uint32_t * iaccess_nb_instruction, |
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| 58 | uint32_t * iaccess_nb_packet, |
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| 59 | uint32_t * iaccess_size_address, |
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| 60 | uint32_t * iaccess_size_instruction, |
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| 61 | |
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| 62 | uint32_t * daccess_nb_context, |
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| 63 | uint32_t * daccess_nb_packet, |
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| 64 | uint32_t * daccess_size_address, |
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| 65 | uint32_t * daccess_size_data, |
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| 66 | |
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| 67 | // buffer |
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| 68 | uint32_t * buffer_irsp_size, |
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| 69 | uint32_t * buffer_drsp_size, |
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| 70 | |
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| 71 | // Cache |
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| 72 | uint32_t * icache_dedicated_nb_level , |
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| 73 | uint32_t * icache_dedicated_nb_port , |
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| 74 | uint32_t ** icache_dedicated_nb_line , |
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| 75 | uint32_t ** icache_dedicated_size_line , |
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| 76 | uint32_t ** icache_dedicated_size_word , |
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| 77 | uint32_t ** icache_dedicated_associativity, |
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| 78 | uint32_t ** icache_dedicated_hit_latence , |
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| 79 | uint32_t ** icache_dedicated_miss_penality, |
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| 80 | uint32_t * dcache_dedicated_nb_level , |
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| 81 | uint32_t * dcache_dedicated_nb_port , |
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| 82 | uint32_t ** dcache_dedicated_nb_line , |
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| 83 | uint32_t ** dcache_dedicated_size_line , |
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| 84 | uint32_t ** dcache_dedicated_size_word , |
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| 85 | uint32_t ** dcache_dedicated_associativity, |
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| 86 | uint32_t ** dcache_dedicated_hit_latence , |
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| 87 | uint32_t ** dcache_dedicated_miss_penality, |
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| 88 | uint32_t cache_shared_nb_level , |
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| 89 | // uint32_t cache_shared_nb_port , |
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| 90 | uint32_t * cache_shared_nb_line , |
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| 91 | uint32_t * cache_shared_size_line , |
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| 92 | uint32_t * cache_shared_size_word , |
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| 93 | uint32_t * cache_shared_associativity , |
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| 94 | uint32_t * cache_shared_hit_latence , |
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| 95 | uint32_t * cache_shared_miss_penality , |
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| 96 | |
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| 97 | // TTY |
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| 98 | uint32_t nb_component_tty, |
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| 99 | uint32_t * tty_address, |
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| 100 | uint32_t * nb_tty, |
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| 101 | std::string ** name_tty, |
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| 102 | bool with_xtty, |
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| 103 | |
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| 104 | // RAMLOCK |
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| 105 | uint32_t nb_component_ramlock, |
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| 106 | uint32_t * ramlock_address, |
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| 107 | uint32_t * nb_lock, |
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| 108 | |
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| 109 | // SIM2OS |
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| 110 | uint32_t sim2os_address, |
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| 111 | uint32_t sim2os_size, |
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| 112 | SOCLIB_SEGMENT_TABLE * segment_table |
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| 113 | ) |
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| 114 | { |
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| 115 | this->nb_entity = nb_cache_dedicated; |
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| 116 | |
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| 117 | this->icache_dedicated_nb_port = icache_dedicated_nb_port; |
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| 118 | this->dcache_dedicated_nb_port = dcache_dedicated_nb_port; |
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| 119 | |
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| 120 | this->iaccess_nb_context = iaccess_nb_context ; |
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| 121 | this->iaccess_nb_instruction = iaccess_nb_instruction ; |
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| 122 | this->iaccess_nb_packet = iaccess_nb_packet ; |
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| 123 | this->iaccess_size_address = iaccess_size_address ; |
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| 124 | this->iaccess_size_instruction = iaccess_size_instruction; |
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| 125 | this->daccess_nb_context = daccess_nb_context ; |
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| 126 | this->daccess_nb_packet = daccess_nb_packet ; |
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| 127 | this->daccess_size_address = daccess_size_address ; |
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| 128 | this->daccess_size_data = daccess_size_data ; |
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| 129 | |
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| 130 | param_cache = new cache::Parameters |
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| 131 | (nb_cache_dedicated , |
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| 132 | icache_dedicated_nb_level , |
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| 133 | icache_dedicated_nb_port , |
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| 134 | icache_dedicated_nb_line , |
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| 135 | icache_dedicated_size_line , |
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| 136 | icache_dedicated_size_word , |
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| 137 | icache_dedicated_associativity, |
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| 138 | icache_dedicated_hit_latence , |
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| 139 | icache_dedicated_miss_penality, |
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| 140 | dcache_dedicated_nb_level , |
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| 141 | dcache_dedicated_nb_port , |
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| 142 | dcache_dedicated_nb_line , |
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| 143 | dcache_dedicated_size_line , |
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| 144 | dcache_dedicated_size_word , |
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| 145 | dcache_dedicated_associativity, |
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| 146 | dcache_dedicated_hit_latence , |
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| 147 | dcache_dedicated_miss_penality, |
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| 148 | cache_shared_nb_level , |
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| 149 | // cache_shared_nb_port , |
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| 150 | cache_shared_nb_line , |
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| 151 | cache_shared_size_line , |
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| 152 | cache_shared_size_word , |
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| 153 | cache_shared_associativity , |
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| 154 | cache_shared_hit_latence , |
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| 155 | cache_shared_miss_penality |
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| 156 | ); |
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| 157 | |
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| 158 | nb_iport = 0; |
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| 159 | nb_dport = 0; |
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| 160 | for (uint32_t i=0; i<nb_cache_dedicated; i++) |
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| 161 | { |
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| 162 | nb_iport += icache_dedicated_nb_port [i]; |
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| 163 | nb_dport += dcache_dedicated_nb_port [i]; |
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| 164 | } |
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| 165 | |
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| 166 | this->nb_component_tty = nb_component_tty; |
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| 167 | this->tty_address = tty_address; |
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| 168 | |
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| 169 | param_tty = new tty::Parameters * [nb_component_tty]; |
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| 170 | for (uint32_t i=0; i<nb_component_tty; i++) |
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| 171 | { |
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| 172 | uint32_t tty_size = nb_tty [i] * 16; // 4 32bit-register by tty |
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| 173 | |
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| 174 | // std::ostringstream str(""); |
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| 175 | // str << "tty_" << i; |
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| 176 | segment_table->addSegment("tty",tty_address[i],tty_size,0,0,true); |
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| 177 | |
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| 178 | param_tty [i] = new tty::Parameters (nb_tty [i], |
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| 179 | name_tty [i], |
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| 180 | with_xtty ); |
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| 181 | } |
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| 182 | |
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| 183 | this->nb_component_ramlock = nb_component_ramlock; |
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| 184 | this->ramlock_address = ramlock_address; |
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| 185 | |
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| 186 | param_ramlock = new ramlock::Parameters * [nb_component_ramlock]; |
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| 187 | for (uint32_t i=0; i<nb_component_ramlock; i++) |
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| 188 | { |
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| 189 | uint32_t ramlock_size = nb_lock[i]; // registre 8 bits because it's min size access |
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| 190 | // std::ostringstream str (""); |
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| 191 | // str << "ramlock" << i; |
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| 192 | segment_table->addSegment("ramlock",ramlock_address[i],ramlock_size,0,0,true); |
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| 193 | |
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| 194 | param_ramlock [i] = new ramlock::Parameters (nb_lock [i]); |
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| 195 | } |
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| 196 | |
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| 197 | this->sim2os_address = sim2os_address ; |
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| 198 | this->sim2os_size = sim2os_size ; |
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| 199 | |
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| 200 | segment_table->addSegment("sim2os",sim2os_address,sim2os_size,0,0,true); |
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| 201 | param_sim2os = new sim2os::Parameters (segment_table); |
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| 202 | |
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| 203 | param_data = new data::Parameters (16,0,0, segment_table); |
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| 204 | |
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| 205 | param_buffer_irsp = new queue::Parameters * [nb_entity]; |
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| 206 | for (uint32_t i=0; i<nb_entity; i++) |
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| 207 | param_buffer_irsp [i] = new queue::Parameters (buffer_irsp_size [i]); |
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| 208 | |
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| 209 | param_buffer_drsp = new queue::Parameters * [nb_entity]; |
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| 210 | for (uint32_t i=0; i<nb_entity; i++) |
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| 211 | param_buffer_drsp [i] = new queue::Parameters (buffer_drsp_size [i]); |
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| 212 | } |
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| 213 | |
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| 214 | public : ~Parameters (void) |
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| 215 | { |
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| 216 | for (uint32_t i=0; i<nb_entity; i++) |
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| 217 | delete param_buffer_irsp [i]; |
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| 218 | delete [] param_buffer_irsp; |
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| 219 | |
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| 220 | for (uint32_t i=0; i<nb_entity; i++) |
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| 221 | delete param_buffer_drsp [i]; |
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| 222 | delete [] param_buffer_drsp; |
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| 223 | |
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| 224 | delete param_data ; |
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| 225 | delete param_sim2os; |
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| 226 | for (uint32_t i=0; i<nb_component_ramlock; i++) |
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| 227 | delete param_ramlock [i]; |
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| 228 | delete [] param_ramlock; |
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| 229 | for (uint32_t i=0; i<nb_component_tty; i++) |
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| 230 | delete param_tty [i]; |
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| 231 | delete [] param_tty; |
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| 232 | delete param_cache; |
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| 233 | } |
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| 234 | }; |
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| 235 | |
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| 236 | }; |
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| 237 | #endif |
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