source: trunk/IPs/systemC/Environment/include/Environment_Parameters.h@ 130

Last change on this file since 130 was 117, checked in by rosiere, 17 years ago

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
  • Property svn:keywords set to Id
File size: 12.4 KB
Line 
1#ifndef ENVIRONMENT_PARAMETERS_H
2#define ENVIRONMENT_PARAMETERS_H
3
4#include "../Cache/include/Cache_Parameters.h"
5#include "../Data/include/Data_Parameters.h"
6#include "../Queue/include/Parameters.h"
7#include "../TTY/include/TTY_Parameters.h"
8#include "../RamLock/include/RamLock_Parameters.h"
9#include "../Sim2OS/include/Sim2OS_Parameters.h"
10#include "../../processor/Morpheo/Common/include/ToString.h"
11
12namespace environment {
13
14 class Parameters
15 {
16 public : uint32_t nb_thread ;
17 public : uint32_t nb_iport ;
18 public : uint32_t nb_dport ;
19 public : uint32_t nb_entity ;
20 public : uint32_t * icache_dedicated_nb_port; //[nb_entity]
21 public : uint32_t * dcache_dedicated_nb_port; //[nb_entity]
22
23 public : uint32_t * iaccess_nb_context ; //[nb_entity]
24 public : uint32_t * iaccess_nb_packet ; //[nb_entity]
25 public : uint32_t * iaccess_size_address ; //[nb_entity]
26 public : uint32_t * iaccess_nb_instruction ; //[nb_entity]
27 public : uint32_t * iaccess_size_instruction; //[nb_entity]
28
29 public : uint32_t * daccess_nb_context ; //[nb_entity]
30 public : uint32_t * daccess_nb_packet ; //[nb_entity]
31 public : uint32_t * daccess_size_address ; //[nb_entity]
32 public : uint32_t * daccess_size_data ; //[nb_entity]
33
34 // Parameters cache
35 public : cache::Parameters * param_cache ;
36 // Parameters tty
37 public : uint32_t nb_component_tty ;
38 public : uint32_t * tty_address ; //[nb_component_tty]
39 public : tty::Parameters ** param_tty ; //[nb_component_tty]
40 // Parameters ramlock
41 public : uint32_t nb_component_ramlock ;
42 public : uint32_t * ramlock_address ; //[nb_component_ramlock]
43 public : ramlock::Parameters ** param_ramlock ; //[nb_component_ramlock]
44 // Parameters sim2OS
45 public : uint32_t sim2os_address ;
46 public : uint32_t sim2os_size ;
47 public : sim2os::Parameters * param_sim2os ;
48 // Parameters data
49 public : data::Parameters * param_data ;
50
51 // Parameters buffer_respons
52 public : queue::Parameters ** param_buffer_irsp ; //[nb_entity]
53 public : queue::Parameters ** param_buffer_drsp ; //[nb_entity]
54
55 public : Parameters (// General
56 uint32_t nb_thread,
57 uint32_t nb_cache_dedicated,
58
59 uint32_t * iaccess_nb_context,
60 uint32_t * iaccess_nb_instruction,
61 uint32_t * iaccess_nb_packet,
62 uint32_t * iaccess_size_address,
63 uint32_t * iaccess_size_instruction,
64
65 uint32_t * daccess_nb_context,
66 uint32_t * daccess_nb_packet,
67 uint32_t * daccess_size_address,
68 uint32_t * daccess_size_data,
69
70 // buffer
71 uint32_t * buffer_irsp_size,
72 uint32_t * buffer_drsp_size,
73
74 // Cache
75 uint32_t * icache_dedicated_nb_level ,
76 uint32_t * icache_dedicated_nb_port ,
77 uint32_t ** icache_dedicated_nb_line ,
78 uint32_t ** icache_dedicated_size_line ,
79 uint32_t ** icache_dedicated_size_word ,
80 uint32_t ** icache_dedicated_associativity,
81 uint32_t ** icache_dedicated_hit_latence ,
82 uint32_t ** icache_dedicated_miss_penality,
83 uint32_t * dcache_dedicated_nb_level ,
84 uint32_t * dcache_dedicated_nb_port ,
85 uint32_t ** dcache_dedicated_nb_line ,
86 uint32_t ** dcache_dedicated_size_line ,
87 uint32_t ** dcache_dedicated_size_word ,
88 uint32_t ** dcache_dedicated_associativity,
89 uint32_t ** dcache_dedicated_hit_latence ,
90 uint32_t ** dcache_dedicated_miss_penality,
91 uint32_t cache_shared_nb_level ,
92// uint32_t cache_shared_nb_port ,
93 uint32_t * cache_shared_nb_line ,
94 uint32_t * cache_shared_size_line ,
95 uint32_t * cache_shared_size_word ,
96 uint32_t * cache_shared_associativity ,
97 uint32_t * cache_shared_hit_latence ,
98 uint32_t * cache_shared_miss_penality ,
99
100 // TTY
101 uint32_t nb_component_tty,
102 uint32_t * tty_address,
103 uint32_t * nb_tty,
104 std::string ** name_tty,
105 bool with_xtty,
106
107 // RAMLOCK
108 uint32_t nb_component_ramlock,
109 uint32_t * ramlock_address,
110 uint32_t * nb_lock,
111
112 // SIM2OS
113 uint32_t sim2os_address,
114 uint32_t sim2os_size,
115 SOCLIB_SEGMENT_TABLE * segment_table
116 )
117 {
118 this->nb_thread = nb_thread;
119 this->nb_entity = nb_cache_dedicated;
120
121 this->icache_dedicated_nb_port = icache_dedicated_nb_port;
122 this->dcache_dedicated_nb_port = dcache_dedicated_nb_port;
123
124 this->iaccess_nb_context = iaccess_nb_context ;
125 this->iaccess_nb_instruction = iaccess_nb_instruction ;
126 this->iaccess_nb_packet = iaccess_nb_packet ;
127 this->iaccess_size_address = iaccess_size_address ;
128 this->iaccess_size_instruction = iaccess_size_instruction;
129 this->daccess_nb_context = daccess_nb_context ;
130 this->daccess_nb_packet = daccess_nb_packet ;
131 this->daccess_size_address = daccess_size_address ;
132 this->daccess_size_data = daccess_size_data ;
133
134 param_cache = new cache::Parameters
135 (nb_cache_dedicated ,
136 icache_dedicated_nb_level ,
137 icache_dedicated_nb_port ,
138 icache_dedicated_nb_line ,
139 icache_dedicated_size_line ,
140 icache_dedicated_size_word ,
141 icache_dedicated_associativity,
142 icache_dedicated_hit_latence ,
143 icache_dedicated_miss_penality,
144 dcache_dedicated_nb_level ,
145 dcache_dedicated_nb_port ,
146 dcache_dedicated_nb_line ,
147 dcache_dedicated_size_line ,
148 dcache_dedicated_size_word ,
149 dcache_dedicated_associativity,
150 dcache_dedicated_hit_latence ,
151 dcache_dedicated_miss_penality,
152 cache_shared_nb_level ,
153// cache_shared_nb_port ,
154 cache_shared_nb_line ,
155 cache_shared_size_line ,
156 cache_shared_size_word ,
157 cache_shared_associativity ,
158 cache_shared_hit_latence ,
159 cache_shared_miss_penality
160 );
161
162 nb_iport = 0;
163 nb_dport = 0;
164 for (uint32_t i=0; i<nb_cache_dedicated; i++)
165 {
166 nb_iport += icache_dedicated_nb_port [i];
167 nb_dport += dcache_dedicated_nb_port [i];
168 }
169
170 this->nb_component_tty = nb_component_tty;
171 this->tty_address = tty_address;
172
173 param_tty = new tty::Parameters * [nb_component_tty];
174 for (uint32_t i=0; i<nb_component_tty; i++)
175 {
176 uint32_t tty_size = nb_tty [i] * 16; // 4 32bit-register by tty
177
178// std::ostringstream str("");
179// str << "tty_" << i;
180 segment_table->addSegment("tty",tty_address[i],tty_size,0,0,true);
181
182 param_tty [i] = new tty::Parameters (nb_tty [i],
183 name_tty [i],
184 with_xtty );
185 }
186
187 this->nb_component_ramlock = nb_component_ramlock;
188 this->ramlock_address = ramlock_address;
189
190 param_ramlock = new ramlock::Parameters * [nb_component_ramlock];
191 for (uint32_t i=0; i<nb_component_ramlock; i++)
192 {
193 uint32_t ramlock_size = nb_lock[i]; // registre 8 bits because it's min size access
194// std::ostringstream str ("");
195// str << "ramlock" << i;
196 segment_table->addSegment("ramlock",ramlock_address[i],ramlock_size,0,0,true);
197
198 param_ramlock [i] = new ramlock::Parameters (nb_lock [i]);
199 }
200
201 this->sim2os_address = sim2os_address ;
202 this->sim2os_size = sim2os_size ;
203
204 segment_table->addSegment("sim2os",sim2os_address,sim2os_size,0,0,true);
205 param_sim2os = new sim2os::Parameters (segment_table);
206
207 param_data = new data::Parameters (16,0,0, segment_table);
208
209 param_buffer_irsp = new queue::Parameters * [nb_entity];
210 for (uint32_t i=0; i<nb_entity; i++)
211 param_buffer_irsp [i] = new queue::Parameters (buffer_irsp_size [i]);
212
213 param_buffer_drsp = new queue::Parameters * [nb_entity];
214 for (uint32_t i=0; i<nb_entity; i++)
215 param_buffer_drsp [i] = new queue::Parameters (buffer_drsp_size [i]);
216 }
217
218 public : ~Parameters (void)
219 {
220 for (uint32_t i=0; i<nb_entity; i++)
221 delete param_buffer_irsp [i];
222 delete [] param_buffer_irsp;
223
224 for (uint32_t i=0; i<nb_entity; i++)
225 delete param_buffer_drsp [i];
226 delete [] param_buffer_drsp;
227
228 delete param_data ;
229 delete param_sim2os;
230 for (uint32_t i=0; i<nb_component_ramlock; i++)
231 delete param_ramlock [i];
232 delete [] param_ramlock;
233 for (uint32_t i=0; i<nb_component_tty; i++)
234 delete param_tty [i];
235 delete [] param_tty;
236 delete param_cache;
237 }
238
239 public : std::string print (uint32_t depth)
240 {
241 std::string tab = std::string(depth,'\t');
242 std::string str = "";
243
244 str+=tab+"nb_entity : "+morpheo::toString(nb_entity)+"\n";
245 str+=tab+"nb_iport : "+morpheo::toString(nb_iport )+"\n";
246 str+=tab+"nb_dport : "+morpheo::toString(nb_dport )+"\n";
247 for (uint32_t i=0; i<nb_entity; ++i)
248 {
249 str+=tab+"ENTITY ["+morpheo::toString(i)+"]\n";
250 str+=tab+" * icache_dedicated_nb_port : "+morpheo::toString(icache_dedicated_nb_port[i])+"\n";
251 str+=tab+" * dcache_dedicated_nb_port : "+morpheo::toString(dcache_dedicated_nb_port[i])+"\n";
252 str+=tab+" * iaccess_nb_context : "+morpheo::toString(iaccess_nb_context [i])+"\n";
253 str+=tab+" * iaccess_nb_packet : "+morpheo::toString(iaccess_nb_packet [i])+"\n";
254 str+=tab+" * iaccess_size_address : "+morpheo::toString(iaccess_size_address [i])+"\n";
255 str+=tab+" * iaccess_nb_instruction : "+morpheo::toString(iaccess_nb_instruction [i])+"\n";
256 str+=tab+" * iaccess_size_instruction : "+morpheo::toString(iaccess_size_instruction[i])+"\n";
257 str+=tab+" * daccess_nb_context : "+morpheo::toString(daccess_nb_context [i])+"\n";
258 str+=tab+" * daccess_nb_packet : "+morpheo::toString(daccess_nb_packet [i])+"\n";
259 str+=tab+" * daccess_size_address : "+morpheo::toString(daccess_size_address [i])+"\n";
260 str+=tab+" * daccess_size_data : "+morpheo::toString(daccess_size_data [i])+"\n";
261 }
262
263 str+=tab+"CACHE\n";
264 str+=param_cache->print(depth+1);
265
266// str+=tab+"nb_component_tty : "+morpheo::toString(nb_component_tty )+"\n";
267// for (uint32_t i=0; i<nb_component_tty; ++i)
268// {
269// str+=tab+"TTY ["+morpheo::toString(i)+"]\n";
270// str+=tab+" * tty_address : "+morpheo::toString(tty_address [i])+"\n";
271// str+=param_tty->print(depth+1);
272// }
273
274// str+=tab+"nb_component_ramlock : "+morpheo::toString(nb_component_ramlock )+"\n";
275// for (uint32_t i=0; i<nb_component_ramlock; ++i)
276// {
277// str+=tab+"RAMLOCK ["+morpheo::toString(i)+"]\n";
278// str+=tab+" * ramlock_address : "+morpheo::toString(ramlock_address [i])+"\n";
279// str+=param_ramlock->print(depth+1);
280// }
281
282// str+=tab+"SIM2OS\n";
283// str+=tab+"sim2os_address : "+morpheo::toString(sim2os_address)+"\n";
284// str+=tab+"sim2os_size : "+morpheo::toString(sim2os_size )+"\n";
285// str+=param_sim2os->print(depth+1);
286
287// str+=tab+"DATA\n";
288// str+=param_data->print(depth+1);
289
290// for (uint32_t i=0; i<nb_entity; ++i)
291// {
292// str+=tab+"BUFFER_IRSP ["+morpheo::toString(i)+"]\n";
293// str+=param_buffer_irsp[i]_data->print(depth+1);
294// }
295
296// for (uint32_t i=0; i<nb_entity; ++i)
297// {
298// str+=tab+"BUFFER_DRSP ["+morpheo::toString(i)+"]\n";
299// str+=param_buffer_drsp[i]_data->print(depth+1);
300// }
301
302 return str;
303 }
304
305// public : friend std::ostream& operator<< (std::ostream& output, const Parameters &x)
306// {
307// x.print(0);
308// return output;
309// }
310 };
311
312};
313#endif
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