Context Navigation

← Previous Revision
Next Revision →
Normal
Revision Log

Environment.cpp

Last change on this file was 138, checked in by rosiere, 15 years ago
1) add counters_t type for interface 2) fix in check load in load_store_unit 3) add parameters (but not yet implemented) 4) change environment and add script (distcc_env.sh ...) 5) add warning if an unser change rename flag with l.mtspr instruction 6) ...
Property svn:keywords set to `Id`
File size: 16.5 KB

Rev	Line
[81]	1	#include "../include/Environment.h"
[128]	2	#include "../../processor/Morpheo/Common/include/ToString.h"
[81]	3
[88]	4	using namespace morpheo;
	5
[81]	6	namespace environment {
	7
	8	Environment::Environment (sc_module_name name, Parameters * param) :
	9	name (name)
	10	{
	11	this->param = param;
	12
	13	component_cache = new cache::Cache ("cache", param->param_cache);
	14	component_tty = new tty::TTY * [param->nb_component_tty];
	15	for (uint32_t i=0; i<param->nb_component_tty; i++)
[128]	16	component_tty [i] = new tty::TTY ("tty_"+morpheo::toString(i),param->param_tty [i]);
[81]	17	component_ramlock = new ramlock::RamLock * [param->nb_component_ramlock];
	18	for (uint32_t i=0; i<param->nb_component_ramlock; i++)
[128]	19	component_ramlock [i] = new ramlock::RamLock ("ramlock_"+morpheo::toString(i),param->param_ramlock [i]);
[81]	20	component_sim2os = new sim2os::Sim2OS ("sim2os" ,param->param_sim2os );
	21	component_data = new data::Data ("data" ,param->param_data );
	22	component_buffer_irsp = new queue::Sort_Queue<irsp_t> [param->nb_entity];
	23	component_buffer_drsp = new queue::Sort_Queue<drsp_t> [param->nb_entity];
	24
	25	for (uint32_t i=0; i<param->nb_component_tty; i++)
	26	{
	27	uint32_t tty_size = param->param_tty[i]->nb_tty * 16;
	28
	29	data::Entity entity = component_data->entity(param->tty_address[i], tty_size);
	30	if (entity.present == false)
	31	{
	32	std::cerr << "<Environnement::Environnement> The tty [" << i << "] have not a segment in the segment table" << std::endl;
	33	exit (1);
	34	}
	35	entity.segment->define_target(data::TYPE_TARGET_TTY,i);
	36	}
	37
	38	for (uint32_t i=0; i<param->nb_component_ramlock; i++)
	39	{
	40	uint32_t ramlock_size = param->param_ramlock[i]->_size;
	41	data::Entity entity = component_data->entity(param->ramlock_address[i], ramlock_size);
	42	if (entity.present == false)
	43	{
	44	std::cerr << "<Environnement::Environnement> The ramlock [" << i << "] have not a segment in the segment table" << std::endl;
	45	exit (1);
	46	}
	47	entity.segment->define_target(data::TYPE_TARGET_RAMLOCK,i);
	48	}
	49
	50	{
	51	data::Entity entity = component_data->entity(param->sim2os_address, param->sim2os_size);
	52	if (entity.present == false)
	53	{
	54	std::cerr << "<Environnement::Environnement> The sim2os have not a segment in the segment table" << std::endl;
	55	exit (1);
	56	}
	57	entity.segment->define_target(data::TYPE_TARGET_SIM2OS,0);
	58	}
	59
	60	for (uint32_t i=0; i<param->nb_entity; i++)
	61	{
	62	component_buffer_irsp [i] = new queue::Sort_Queue<irsp_t*> ("buffer_irsp_"+i,param->param_buffer_irsp [i]);
	63	component_buffer_drsp [i] = new queue::Sort_Queue<drsp_t*> ("buffer_drsp_"+i,param->param_buffer_drsp [i]);
	64	}
	65
	66	uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction ,param->nb_entity);
	67	uint32_t max_instruction_size = morpheo::max<uint32_t>(param->iaccess_size_instruction,param->nb_entity);
	68	uint32_t max_data_size = morpheo::max<uint32_t>(param->daccess_size_data ,param->nb_entity);
	69
	70	read_iram = new char * [max_nb_instruction];
	71	for (uint32_t i=0; i<max_nb_instruction; i++)
	72	read_iram [i] = new char [max_instruction_size];
	73
	74	read_dram = new char * [1];
	75	read_dram[0] = new char [max_data_size/8];
	76	write_dram = new char [max_data_size/8];
[88]	77	context_stop = new bool [param->nb_entity];
	78	for (uint32_t i=0; i<param->nb_entity; ++i)
	79	context_stop [i] = false;
	80	nb_context_stop = 0;
[81]	81
	82	// Port
[138]	83	CLOCK = new sc_in_clk ("CLOCK");
[81]	84	NRESET = new sc_in<bool> ("NRESET");
	85
	86	ICACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
	87	ICACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
	88	ICACHE_REQ_CONTEXT_ID = new sc_in <Ticache_context_t > ** [param->nb_entity];
	89	ICACHE_REQ_PACKET_ID = new sc_in <Ticache_packet_t > ** [param->nb_entity];
	90	ICACHE_REQ_ADDRESS = new sc_in <Ticache_address_t > ** [param->nb_entity];
	91	ICACHE_REQ_TYPE = new sc_in <Ticache_type_t > ** [param->nb_entity];
	92
	93	ICACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
	94	ICACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
	95	ICACHE_RSP_CONTEXT_ID = new sc_out<Ticache_context_t > ** [param->nb_entity];
	96	ICACHE_RSP_PACKET_ID = new sc_out<Ticache_packet_t > ** [param->nb_entity];
	97
	98	ICACHE_RSP_INSTRUCTION= new sc_out<Ticache_instruction_t> *** [param->nb_entity];//[nb_instruction]
	99	ICACHE_RSP_ERROR = new sc_out<Ticache_error_t > ** [param->nb_entity];
	100
	101	DCACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
	102	DCACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
	103	DCACHE_REQ_CONTEXT_ID = new sc_in <Tdcache_context_t > ** [param->nb_entity];
	104	DCACHE_REQ_PACKET_ID = new sc_in <Tdcache_packet_t > ** [param->nb_entity];
	105	DCACHE_REQ_ADDRESS = new sc_in <Tdcache_address_t > ** [param->nb_entity];
	106	DCACHE_REQ_TYPE = new sc_in <Tdcache_type_t > ** [param->nb_entity];
	107	DCACHE_REQ_WDATA = new sc_in <Tdcache_data_t > ** [param->nb_entity];
	108
	109	DCACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
	110	DCACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
	111	DCACHE_RSP_CONTEXT_ID = new sc_out<Tdcache_context_t > ** [param->nb_entity];
	112	DCACHE_RSP_PACKET_ID = new sc_out<Tdcache_packet_t > ** [param->nb_entity];
	113	DCACHE_RSP_RDATA = new sc_out<Tdcache_data_t > ** [param->nb_entity];
	114	DCACHE_RSP_ERROR = new sc_out<Tdcache_error_t > ** [param->nb_entity];
	115
	116	for (uint32_t i=0; i<param->nb_entity; i++)
	117	{
	118	ICACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
	119	ICACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
	120	ICACHE_REQ_CONTEXT_ID [i] = new sc_in <Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
	121	ICACHE_REQ_PACKET_ID [i] = new sc_in <Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
	122	ICACHE_REQ_ADDRESS [i] = new sc_in <Ticache_address_t > * [param->icache_dedicated_nb_port[i]];
	123	ICACHE_REQ_TYPE [i] = new sc_in <Ticache_type_t > * [param->icache_dedicated_nb_port[i]];
	124
	125	ICACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
	126	ICACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
	127	ICACHE_RSP_CONTEXT_ID [i] = new sc_out<Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
	128	ICACHE_RSP_PACKET_ID [i] = new sc_out<Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
	129	ICACHE_RSP_INSTRUCTION[i] = new sc_out<Ticache_instruction_t> ** [param->icache_dedicated_nb_port[i]];//[nb_instruction]
	130	ICACHE_RSP_ERROR [i] = new sc_out<Ticache_error_t > * [param->icache_dedicated_nb_port[i]];
	131
	132	for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
	133	{
	134	ICACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
	135	ICACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
	136	ICACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Ticache_context_t > ("");
	137	ICACHE_REQ_PACKET_ID [i][j] = new sc_in <Ticache_packet_t > ("");
	138	ICACHE_REQ_ADDRESS [i][j] = new sc_in <Ticache_address_t > ("");
	139	ICACHE_REQ_TYPE [i][j] = new sc_in <Ticache_type_t > ("");
	140
	141	ICACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
	142	ICACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
	143	ICACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Ticache_context_t > ("");
	144	ICACHE_RSP_PACKET_ID [i][j] = new sc_out<Ticache_packet_t > ("");
	145	ICACHE_RSP_ERROR [i][j] = new sc_out<Ticache_error_t > ("");
	146
	147	ICACHE_RSP_INSTRUCTION [i][j] = new sc_out<Ticache_instruction_t> * [param->iaccess_nb_instruction[i]];
	148
	149	for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
	150	ICACHE_RSP_INSTRUCTION [i][j][k] = new sc_out<Ticache_instruction_t> ("");
	151	}
	152
	153	DCACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
	154	DCACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
	155	DCACHE_REQ_CONTEXT_ID [i] = new sc_in <Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
	156	DCACHE_REQ_PACKET_ID [i] = new sc_in <Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
	157	DCACHE_REQ_ADDRESS [i] = new sc_in <Tdcache_address_t > * [param->dcache_dedicated_nb_port[i]];
	158	DCACHE_REQ_TYPE [i] = new sc_in <Tdcache_type_t > * [param->dcache_dedicated_nb_port[i]];
	159	DCACHE_REQ_WDATA [i] = new sc_in <Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
	160
	161	DCACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
	162	DCACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
	163	DCACHE_RSP_CONTEXT_ID [i] = new sc_out<Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
	164	DCACHE_RSP_PACKET_ID [i] = new sc_out<Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
	165	DCACHE_RSP_RDATA [i] = new sc_out<Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
	166	DCACHE_RSP_ERROR [i] = new sc_out<Tdcache_error_t > * [param->dcache_dedicated_nb_port[i]];
	167
	168	for (uint32_t j=0; j<param->dcache_dedicated_nb_port[i]; j++)
	169	{
	170	DCACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
	171	DCACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
	172	DCACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Tdcache_context_t > ("");
	173	DCACHE_REQ_PACKET_ID [i][j] = new sc_in <Tdcache_packet_t > ("");
	174	DCACHE_REQ_ADDRESS [i][j] = new sc_in <Tdcache_address_t > ("");
	175	DCACHE_REQ_TYPE [i][j] = new sc_in <Tdcache_type_t > ("");
	176	DCACHE_REQ_WDATA [i][j] = new sc_in <Tdcache_data_t > ("");
	177
	178	DCACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
	179	DCACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
	180	DCACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Tdcache_context_t > ("");
	181	DCACHE_RSP_PACKET_ID [i][j] = new sc_out<Tdcache_packet_t > ("");
	182	DCACHE_RSP_RDATA [i][j] = new sc_out<Tdcache_data_t > ("");
	183	DCACHE_RSP_ERROR [i][j] = new sc_out<Tdcache_error_t > ("");
	184	}
	185	}
	186
	187	icache_req_ack = new Tcontrol_t * [param->nb_entity];
	188	icache_rsp_val = new Tcontrol_t * [param->nb_entity];
[128]	189	icache_rsp_num = new uint32_t * [param->nb_entity];
[81]	190	dcache_req_ack = new Tcontrol_t * [param->nb_entity];
	191	dcache_rsp_val = new Tcontrol_t * [param->nb_entity];
[128]	192	dcache_rsp_num = new uint32_t * [param->nb_entity];
[81]	193
	194	for (uint32_t i=0; i<param->nb_entity; i++)
	195	{
	196	icache_req_ack [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
	197	icache_rsp_val [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
[128]	198	icache_rsp_num [i] = new uint32_t [param->icache_dedicated_nb_port[i]];
[81]	199	dcache_req_ack [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
	200	dcache_rsp_val [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
[128]	201	dcache_rsp_num [i] = new uint32_t [param->dcache_dedicated_nb_port[i]];
[81]	202	}
[123]	203
[81]	204	// ***[ Definition of method ]***
	205	SC_METHOD (transition);
	206	dont_initialize ();
	207	sensitive << (*(CLOCK)).pos();
	208
	209	SC_METHOD (genMoore);
	210	dont_initialize ();
	211	sensitive << (*(CLOCK)).neg();
[123]	212
[81]	213	}
	214
	215	Environment::~Environment (void)
	216	{
	217	for (uint32_t i=0; i<param->nb_entity; i++)
	218	{
	219	delete [] icache_req_ack [i];
	220	delete [] icache_rsp_val [i];
[128]	221	delete [] icache_rsp_num [i];
[81]	222	delete [] dcache_req_ack [i];
	223	delete [] dcache_rsp_val [i];
[128]	224	delete [] dcache_rsp_num [i];
[81]	225	}
	226
	227	delete [] icache_req_ack;
	228	delete [] icache_rsp_val;
[128]	229	delete [] icache_rsp_num;
[81]	230	delete [] dcache_req_ack;
	231	delete [] dcache_rsp_val;
[128]	232	delete [] dcache_rsp_num;
[81]	233
	234	delete CLOCK ;
	235	delete NRESET;
	236
	237	for (uint32_t i=0; i<param->nb_entity; i++)
	238	{
	239	for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
	240	{
	241	delete ICACHE_REQ_VAL [i][j];
	242	delete ICACHE_REQ_ACK [i][j];
	243	delete ICACHE_REQ_CONTEXT_ID [i][j];
	244	delete ICACHE_REQ_PACKET_ID [i][j];
	245	delete ICACHE_REQ_ADDRESS [i][j];
	246	delete ICACHE_REQ_TYPE [i][j];
	247	delete ICACHE_RSP_VAL [i][j];
	248	delete ICACHE_RSP_ACK [i][j];
	249	delete ICACHE_RSP_CONTEXT_ID [i][j];
	250	delete ICACHE_RSP_PACKET_ID [i][j];
	251	delete ICACHE_RSP_ERROR [i][j];
	252
	253	for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
[128]	254	delete ICACHE_RSP_INSTRUCTION [i][j][k];
[81]	255	delete [] ICACHE_RSP_INSTRUCTION [i][j];
	256	}
[128]	257
[81]	258	delete [] ICACHE_REQ_VAL [i];
	259	delete [] ICACHE_REQ_ACK [i];
	260	delete [] ICACHE_REQ_CONTEXT_ID [i];
	261	delete [] ICACHE_REQ_PACKET_ID [i];
	262	delete [] ICACHE_REQ_ADDRESS [i];
	263	delete [] ICACHE_REQ_TYPE [i];
	264	delete [] ICACHE_RSP_VAL [i];
	265	delete [] ICACHE_RSP_ACK [i];
	266	delete [] ICACHE_RSP_CONTEXT_ID [i];
	267	delete [] ICACHE_RSP_PACKET_ID [i];
	268	delete [] ICACHE_RSP_ERROR [i];
	269	delete [] ICACHE_RSP_INSTRUCTION [i];
	270	}
	271
	272	delete [] ICACHE_REQ_VAL ;
	273	delete [] ICACHE_REQ_ACK ;
	274	delete [] ICACHE_REQ_CONTEXT_ID ;
	275	delete [] ICACHE_REQ_PACKET_ID ;
	276	delete [] ICACHE_REQ_ADDRESS ;
	277	delete [] ICACHE_REQ_TYPE ;
	278	delete [] ICACHE_RSP_VAL ;
	279	delete [] ICACHE_RSP_ACK ;
	280	delete [] ICACHE_RSP_CONTEXT_ID ;
	281	delete [] ICACHE_RSP_PACKET_ID ;
	282	delete [] ICACHE_RSP_INSTRUCTION;
	283	delete [] ICACHE_RSP_ERROR ;
	284
	285	for (uint32_t i=0; i<param->nb_entity; i++)
	286	{
[128]	287	for (uint32_t j=0; j<param->dcache_dedicated_nb_port[i]; j++)
[81]	288	{
	289	delete DCACHE_REQ_VAL [i][j];
	290	delete DCACHE_REQ_ACK [i][j];
	291	delete DCACHE_REQ_CONTEXT_ID [i][j];
	292	delete DCACHE_REQ_PACKET_ID [i][j];
	293	delete DCACHE_REQ_ADDRESS [i][j];
	294	delete DCACHE_REQ_TYPE [i][j];
	295	delete DCACHE_REQ_WDATA [i][j];
	296	delete DCACHE_RSP_VAL [i][j];
	297	delete DCACHE_RSP_ACK [i][j];
	298	delete DCACHE_RSP_CONTEXT_ID [i][j];
	299	delete DCACHE_RSP_PACKET_ID [i][j];
	300	delete DCACHE_RSP_RDATA [i][j];
	301	delete DCACHE_RSP_ERROR [i][j];
	302	}
	303
	304	delete [] DCACHE_REQ_VAL [i];
	305	delete [] DCACHE_REQ_ACK [i];
	306	delete [] DCACHE_REQ_CONTEXT_ID [i];
	307	delete [] DCACHE_REQ_PACKET_ID [i];
	308	delete [] DCACHE_REQ_ADDRESS [i];
	309	delete [] DCACHE_REQ_TYPE [i];
	310	delete [] DCACHE_REQ_WDATA [i];
	311	delete [] DCACHE_RSP_VAL [i];
	312	delete [] DCACHE_RSP_ACK [i];
	313	delete [] DCACHE_RSP_CONTEXT_ID [i];
	314	delete [] DCACHE_RSP_PACKET_ID [i];
	315	delete [] DCACHE_RSP_RDATA [i];
	316	delete [] DCACHE_RSP_ERROR [i];
	317	}
	318
	319	delete [] DCACHE_REQ_VAL ;
	320	delete [] DCACHE_REQ_ACK ;
	321	delete [] DCACHE_REQ_CONTEXT_ID ;
	322	delete [] DCACHE_REQ_PACKET_ID ;
	323	delete [] DCACHE_REQ_ADDRESS ;
	324	delete [] DCACHE_REQ_TYPE ;
	325	delete [] DCACHE_REQ_WDATA ;
	326	delete [] DCACHE_RSP_VAL ;
	327	delete [] DCACHE_RSP_ACK ;
	328	delete [] DCACHE_RSP_CONTEXT_ID ;
	329	delete [] DCACHE_RSP_PACKET_ID ;
	330	delete [] DCACHE_RSP_RDATA ;
	331	delete [] DCACHE_RSP_ERROR ;
	332
[112]	333	delete [] context_stop;
[81]	334	delete [] write_dram;
	335	delete [] read_dram [0];
	336	delete [] read_dram;
	337
	338	uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction,param->nb_entity);
	339	for (uint32_t i=0; i<max_nb_instruction; i++)
	340	delete [] read_iram [i];
	341	delete [] read_iram;
	342
	343	for (uint32_t i=0; i<param->nb_entity; i++)
	344	{
	345	while (not component_buffer_irsp [i]->empty())
	346	{
	347	delete component_buffer_irsp [i]->read(0)._data;
	348	component_buffer_irsp [i]->pop();
	349	}
	350	while (not component_buffer_drsp [i]->empty())
	351	{
	352	delete component_buffer_drsp [i]->read(0)._data;
	353	component_buffer_drsp [i]->pop();
	354	}
	355
	356	delete component_buffer_irsp [i];
	357	delete component_buffer_drsp [i];
	358	}
	359	delete [] component_buffer_irsp;
	360	delete [] component_buffer_drsp;
	361
	362	delete component_data;
	363	delete component_sim2os;
	364	for (uint32_t i=0; i<param->nb_component_ramlock; i++)
	365	delete component_ramlock [i];
	366	delete [] component_ramlock;
	367	for (uint32_t i=0; i<param->nb_component_tty; i++)
	368	delete component_tty [i];
	369	delete [] component_tty;
	370	delete component_cache;
	371
	372	}
	373
	374	};

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/IPs/systemC/Environment/src/Environment.cpp

Download in other formats: