source: trunk/IPs/systemC/Environment/src/Environment.cpp@ 84

Last change on this file since 84 was 81, checked in by rosiere, 18 years ago
  • Finish Environment (and test)
  • Continue predictor_unit
  • Add external tools
  • svn keyword "Id" set
  • Property svn:keywords set to Id
File size: 15.8 KB
RevLine 
[81]1#include "../include/Environment.h"
2
3namespace environment {
4
5 Environment::Environment (sc_module_name name, Parameters * param) :
6 name (name)
7 {
8 this->param = param;
9
10 component_cache = new cache::Cache ("cache", param->param_cache);
11
12 component_tty = new tty::TTY * [param->nb_component_tty];
13 for (uint32_t i=0; i<param->nb_component_tty; i++)
14 component_tty [i] = new tty::TTY ("tty_"+i ,param->param_tty [i]);
15
16 component_ramlock = new ramlock::RamLock * [param->nb_component_ramlock];
17 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
18 component_ramlock [i] = new ramlock::RamLock ("ramlock_"+i,param->param_ramlock [i]);
19
20 component_sim2os = new sim2os::Sim2OS ("sim2os" ,param->param_sim2os );
21 component_data = new data::Data ("data" ,param->param_data );
22
23 component_buffer_irsp = new queue::Sort_Queue<irsp_t*> * [param->nb_entity];
24 component_buffer_drsp = new queue::Sort_Queue<drsp_t*> * [param->nb_entity];
25
26 for (uint32_t i=0; i<param->nb_component_tty; i++)
27 {
28 uint32_t tty_size = param->param_tty[i]->nb_tty * 16;
29
30 data::Entity entity = component_data->entity(param->tty_address[i], tty_size);
31 if (entity.present == false)
32 {
33 std::cerr << "<Environnement::Environnement> The tty [" << i << "] have not a segment in the segment table" << std::endl;
34 exit (1);
35 }
36 entity.segment->define_target(data::TYPE_TARGET_TTY,i);
37 }
38
39 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
40 {
41 uint32_t ramlock_size = param->param_ramlock[i]->_size;
42 data::Entity entity = component_data->entity(param->ramlock_address[i], ramlock_size);
43 if (entity.present == false)
44 {
45 std::cerr << "<Environnement::Environnement> The ramlock [" << i << "] have not a segment in the segment table" << std::endl;
46 exit (1);
47 }
48 entity.segment->define_target(data::TYPE_TARGET_RAMLOCK,i);
49 }
50
51 {
52 data::Entity entity = component_data->entity(param->sim2os_address, param->sim2os_size);
53 if (entity.present == false)
54 {
55 std::cerr << "<Environnement::Environnement> The sim2os have not a segment in the segment table" << std::endl;
56 exit (1);
57 }
58 entity.segment->define_target(data::TYPE_TARGET_SIM2OS,0);
59 }
60
61
62
63
64 for (uint32_t i=0; i<param->nb_entity; i++)
65 {
66 component_buffer_irsp [i] = new queue::Sort_Queue<irsp_t*> ("buffer_irsp_"+i,param->param_buffer_irsp [i]);
67 component_buffer_drsp [i] = new queue::Sort_Queue<drsp_t*> ("buffer_drsp_"+i,param->param_buffer_drsp [i]);
68 }
69
70 uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction ,param->nb_entity);
71 uint32_t max_instruction_size = morpheo::max<uint32_t>(param->iaccess_size_instruction,param->nb_entity);
72 uint32_t max_data_size = morpheo::max<uint32_t>(param->daccess_size_data ,param->nb_entity);
73
74 read_iram = new char * [max_nb_instruction];
75 for (uint32_t i=0; i<max_nb_instruction; i++)
76 read_iram [i] = new char [max_instruction_size];
77
78 read_dram = new char * [1];
79 read_dram[0] = new char [max_data_size/8];
80 write_dram = new char [max_data_size/8];
81
82 // Port
83 CLOCK = new sc_in_clk ("CLOCK ");
84 NRESET = new sc_in<bool> ("NRESET");
85
86 ICACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
87 ICACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
88 ICACHE_REQ_CONTEXT_ID = new sc_in <Ticache_context_t > ** [param->nb_entity];
89 ICACHE_REQ_PACKET_ID = new sc_in <Ticache_packet_t > ** [param->nb_entity];
90 ICACHE_REQ_ADDRESS = new sc_in <Ticache_address_t > ** [param->nb_entity];
91 ICACHE_REQ_TYPE = new sc_in <Ticache_type_t > ** [param->nb_entity];
92
93 ICACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
94 ICACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
95 ICACHE_RSP_CONTEXT_ID = new sc_out<Ticache_context_t > ** [param->nb_entity];
96 ICACHE_RSP_PACKET_ID = new sc_out<Ticache_packet_t > ** [param->nb_entity];
97
98 ICACHE_RSP_INSTRUCTION= new sc_out<Ticache_instruction_t> *** [param->nb_entity];//[nb_instruction]
99 ICACHE_RSP_ERROR = new sc_out<Ticache_error_t > ** [param->nb_entity];
100
101 DCACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
102 DCACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
103 DCACHE_REQ_CONTEXT_ID = new sc_in <Tdcache_context_t > ** [param->nb_entity];
104 DCACHE_REQ_PACKET_ID = new sc_in <Tdcache_packet_t > ** [param->nb_entity];
105 DCACHE_REQ_ADDRESS = new sc_in <Tdcache_address_t > ** [param->nb_entity];
106 DCACHE_REQ_TYPE = new sc_in <Tdcache_type_t > ** [param->nb_entity];
107 DCACHE_REQ_WDATA = new sc_in <Tdcache_data_t > ** [param->nb_entity];
108
109 DCACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
110 DCACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
111 DCACHE_RSP_CONTEXT_ID = new sc_out<Tdcache_context_t > ** [param->nb_entity];
112 DCACHE_RSP_PACKET_ID = new sc_out<Tdcache_packet_t > ** [param->nb_entity];
113 DCACHE_RSP_RDATA = new sc_out<Tdcache_data_t > ** [param->nb_entity];
114 DCACHE_RSP_ERROR = new sc_out<Tdcache_error_t > ** [param->nb_entity];
115
116 for (uint32_t i=0; i<param->nb_entity; i++)
117 {
118 ICACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
119 ICACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
120 ICACHE_REQ_CONTEXT_ID [i] = new sc_in <Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
121 ICACHE_REQ_PACKET_ID [i] = new sc_in <Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
122 ICACHE_REQ_ADDRESS [i] = new sc_in <Ticache_address_t > * [param->icache_dedicated_nb_port[i]];
123 ICACHE_REQ_TYPE [i] = new sc_in <Ticache_type_t > * [param->icache_dedicated_nb_port[i]];
124
125 ICACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
126 ICACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
127 ICACHE_RSP_CONTEXT_ID [i] = new sc_out<Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
128 ICACHE_RSP_PACKET_ID [i] = new sc_out<Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
129 ICACHE_RSP_INSTRUCTION[i] = new sc_out<Ticache_instruction_t> ** [param->icache_dedicated_nb_port[i]];//[nb_instruction]
130 ICACHE_RSP_ERROR [i] = new sc_out<Ticache_error_t > * [param->icache_dedicated_nb_port[i]];
131
132 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
133 {
134 ICACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
135 ICACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
136 ICACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Ticache_context_t > ("");
137 ICACHE_REQ_PACKET_ID [i][j] = new sc_in <Ticache_packet_t > ("");
138 ICACHE_REQ_ADDRESS [i][j] = new sc_in <Ticache_address_t > ("");
139 ICACHE_REQ_TYPE [i][j] = new sc_in <Ticache_type_t > ("");
140
141 ICACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
142 ICACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
143 ICACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Ticache_context_t > ("");
144 ICACHE_RSP_PACKET_ID [i][j] = new sc_out<Ticache_packet_t > ("");
145 ICACHE_RSP_ERROR [i][j] = new sc_out<Ticache_error_t > ("");
146
147 ICACHE_RSP_INSTRUCTION [i][j] = new sc_out<Ticache_instruction_t> * [param->iaccess_nb_instruction[i]];
148
149 for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
150 ICACHE_RSP_INSTRUCTION [i][j][k] = new sc_out<Ticache_instruction_t> ("");
151 }
152
153 DCACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
154 DCACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
155 DCACHE_REQ_CONTEXT_ID [i] = new sc_in <Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
156 DCACHE_REQ_PACKET_ID [i] = new sc_in <Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
157 DCACHE_REQ_ADDRESS [i] = new sc_in <Tdcache_address_t > * [param->dcache_dedicated_nb_port[i]];
158 DCACHE_REQ_TYPE [i] = new sc_in <Tdcache_type_t > * [param->dcache_dedicated_nb_port[i]];
159 DCACHE_REQ_WDATA [i] = new sc_in <Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
160
161 DCACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
162 DCACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
163 DCACHE_RSP_CONTEXT_ID [i] = new sc_out<Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
164 DCACHE_RSP_PACKET_ID [i] = new sc_out<Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
165 DCACHE_RSP_RDATA [i] = new sc_out<Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
166 DCACHE_RSP_ERROR [i] = new sc_out<Tdcache_error_t > * [param->dcache_dedicated_nb_port[i]];
167
168 for (uint32_t j=0; j<param->dcache_dedicated_nb_port[i]; j++)
169 {
170 DCACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
171 DCACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
172 DCACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Tdcache_context_t > ("");
173 DCACHE_REQ_PACKET_ID [i][j] = new sc_in <Tdcache_packet_t > ("");
174 DCACHE_REQ_ADDRESS [i][j] = new sc_in <Tdcache_address_t > ("");
175 DCACHE_REQ_TYPE [i][j] = new sc_in <Tdcache_type_t > ("");
176 DCACHE_REQ_WDATA [i][j] = new sc_in <Tdcache_data_t > ("");
177
178 DCACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
179 DCACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
180 DCACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Tdcache_context_t > ("");
181 DCACHE_RSP_PACKET_ID [i][j] = new sc_out<Tdcache_packet_t > ("");
182 DCACHE_RSP_RDATA [i][j] = new sc_out<Tdcache_data_t > ("");
183 DCACHE_RSP_ERROR [i][j] = new sc_out<Tdcache_error_t > ("");
184 }
185 }
186
187 icache_req_ack = new Tcontrol_t * [param->nb_entity];
188 icache_rsp_val = new Tcontrol_t * [param->nb_entity];
189 dcache_req_ack = new Tcontrol_t * [param->nb_entity];
190 dcache_rsp_val = new Tcontrol_t * [param->nb_entity];
191
192 for (uint32_t i=0; i<param->nb_entity; i++)
193 {
194 icache_req_ack [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
195 icache_rsp_val [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
196 dcache_req_ack [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
197 dcache_rsp_val [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
198 }
199 // *****[ Definition of method ]*****
200 SC_METHOD (transition);
201 dont_initialize ();
202 sensitive << (*(CLOCK)).pos();
203
204 SC_METHOD (genMoore);
205 dont_initialize ();
206 sensitive << (*(CLOCK)).neg();
207 }
208
209 Environment::~Environment (void)
210 {
211 for (uint32_t i=0; i<param->nb_entity; i++)
212 {
213 delete [] icache_req_ack [i];
214 delete [] icache_rsp_val [i];
215 delete [] dcache_req_ack [i];
216 delete [] dcache_rsp_val [i];
217 }
218
219 delete [] icache_req_ack;
220 delete [] icache_rsp_val;
221 delete [] dcache_req_ack;
222 delete [] dcache_rsp_val;
223
224 delete CLOCK ;
225 delete NRESET;
226
227 for (uint32_t i=0; i<param->nb_entity; i++)
228 {
229 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
230 {
231 delete ICACHE_REQ_VAL [i][j];
232 delete ICACHE_REQ_ACK [i][j];
233 delete ICACHE_REQ_CONTEXT_ID [i][j];
234 delete ICACHE_REQ_PACKET_ID [i][j];
235 delete ICACHE_REQ_ADDRESS [i][j];
236 delete ICACHE_REQ_TYPE [i][j];
237 delete ICACHE_RSP_VAL [i][j];
238 delete ICACHE_RSP_ACK [i][j];
239 delete ICACHE_RSP_CONTEXT_ID [i][j];
240 delete ICACHE_RSP_PACKET_ID [i][j];
241 delete ICACHE_RSP_ERROR [i][j];
242
243 for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
244 delete ICACHE_RSP_INSTRUCTION [i][j][k];
245
246 delete [] ICACHE_RSP_INSTRUCTION [i][j];
247 }
248 delete [] ICACHE_REQ_VAL [i];
249 delete [] ICACHE_REQ_ACK [i];
250 delete [] ICACHE_REQ_CONTEXT_ID [i];
251 delete [] ICACHE_REQ_PACKET_ID [i];
252 delete [] ICACHE_REQ_ADDRESS [i];
253 delete [] ICACHE_REQ_TYPE [i];
254 delete [] ICACHE_RSP_VAL [i];
255 delete [] ICACHE_RSP_ACK [i];
256 delete [] ICACHE_RSP_CONTEXT_ID [i];
257 delete [] ICACHE_RSP_PACKET_ID [i];
258 delete [] ICACHE_RSP_ERROR [i];
259 delete [] ICACHE_RSP_INSTRUCTION [i];
260 }
261
262 delete [] ICACHE_REQ_VAL ;
263 delete [] ICACHE_REQ_ACK ;
264 delete [] ICACHE_REQ_CONTEXT_ID ;
265 delete [] ICACHE_REQ_PACKET_ID ;
266 delete [] ICACHE_REQ_ADDRESS ;
267 delete [] ICACHE_REQ_TYPE ;
268 delete [] ICACHE_RSP_VAL ;
269 delete [] ICACHE_RSP_ACK ;
270 delete [] ICACHE_RSP_CONTEXT_ID ;
271 delete [] ICACHE_RSP_PACKET_ID ;
272 delete [] ICACHE_RSP_INSTRUCTION;
273 delete [] ICACHE_RSP_ERROR ;
274
275 for (uint32_t i=0; i<param->nb_entity; i++)
276 {
277 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
278 {
279 delete DCACHE_REQ_VAL [i][j];
280 delete DCACHE_REQ_ACK [i][j];
281 delete DCACHE_REQ_CONTEXT_ID [i][j];
282 delete DCACHE_REQ_PACKET_ID [i][j];
283 delete DCACHE_REQ_ADDRESS [i][j];
284 delete DCACHE_REQ_TYPE [i][j];
285 delete DCACHE_REQ_WDATA [i][j];
286 delete DCACHE_RSP_VAL [i][j];
287 delete DCACHE_RSP_ACK [i][j];
288 delete DCACHE_RSP_CONTEXT_ID [i][j];
289 delete DCACHE_RSP_PACKET_ID [i][j];
290 delete DCACHE_RSP_RDATA [i][j];
291 delete DCACHE_RSP_ERROR [i][j];
292 }
293
294 delete [] DCACHE_REQ_VAL [i];
295 delete [] DCACHE_REQ_ACK [i];
296 delete [] DCACHE_REQ_CONTEXT_ID [i];
297 delete [] DCACHE_REQ_PACKET_ID [i];
298 delete [] DCACHE_REQ_ADDRESS [i];
299 delete [] DCACHE_REQ_TYPE [i];
300 delete [] DCACHE_REQ_WDATA [i];
301 delete [] DCACHE_RSP_VAL [i];
302 delete [] DCACHE_RSP_ACK [i];
303 delete [] DCACHE_RSP_CONTEXT_ID [i];
304 delete [] DCACHE_RSP_PACKET_ID [i];
305 delete [] DCACHE_RSP_RDATA [i];
306 delete [] DCACHE_RSP_ERROR [i];
307 }
308
309 delete [] DCACHE_REQ_VAL ;
310 delete [] DCACHE_REQ_ACK ;
311 delete [] DCACHE_REQ_CONTEXT_ID ;
312 delete [] DCACHE_REQ_PACKET_ID ;
313 delete [] DCACHE_REQ_ADDRESS ;
314 delete [] DCACHE_REQ_TYPE ;
315 delete [] DCACHE_REQ_WDATA ;
316 delete [] DCACHE_RSP_VAL ;
317 delete [] DCACHE_RSP_ACK ;
318 delete [] DCACHE_RSP_CONTEXT_ID ;
319 delete [] DCACHE_RSP_PACKET_ID ;
320 delete [] DCACHE_RSP_RDATA ;
321 delete [] DCACHE_RSP_ERROR ;
322
323 delete [] write_dram;
324 delete [] read_dram [0];
325 delete [] read_dram;
326
327 uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction,param->nb_entity);
328 for (uint32_t i=0; i<max_nb_instruction; i++)
329 delete [] read_iram [i];
330 delete [] read_iram;
331
332 for (uint32_t i=0; i<param->nb_entity; i++)
333 {
334 while (not component_buffer_irsp [i]->empty())
335 {
336 delete component_buffer_irsp [i]->read(0)._data;
337 component_buffer_irsp [i]->pop();
338 }
339 while (not component_buffer_drsp [i]->empty())
340 {
341 delete component_buffer_drsp [i]->read(0)._data;
342 component_buffer_drsp [i]->pop();
343 }
344
345 delete component_buffer_irsp [i];
346 delete component_buffer_drsp [i];
347 }
348 delete [] component_buffer_irsp;
349 delete [] component_buffer_drsp;
350
351 delete component_data;
352 delete component_sim2os;
353 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
354 delete component_ramlock [i];
355 delete [] component_ramlock;
356 for (uint32_t i=0; i<param->nb_component_tty; i++)
357 delete component_tty [i];
358 delete [] component_tty;
359 delete component_cache;
360
361 }
362
363};
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