source: trunk/IPs/systemC/Environment/src/Environment.cpp@ 123

Last change on this file since 123 was 123, checked in by rosiere, 17 years ago

1) Fix performance
2) add auto generation to SPECINT2000
3) add reset in genMoore and genMealy
  • Property svn:keywords set to Id
File size: 16.0 KB
Line 
1#include "../include/Environment.h"
2
3using namespace morpheo;
4
5namespace environment {
6
7 Environment::Environment (sc_module_name name, Parameters * param) :
8 name (name)
9 {
10 this->param = param;
11
12 component_cache = new cache::Cache ("cache", param->param_cache);
13 component_tty = new tty::TTY * [param->nb_component_tty];
14 for (uint32_t i=0; i<param->nb_component_tty; i++)
15 component_tty [i] = new tty::TTY ("tty_"+i ,param->param_tty [i]);
16 component_ramlock = new ramlock::RamLock * [param->nb_component_ramlock];
17 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
18 component_ramlock [i] = new ramlock::RamLock ("ramlock_"+i,param->param_ramlock [i]);
19 component_sim2os = new sim2os::Sim2OS ("sim2os" ,param->param_sim2os );
20 component_data = new data::Data ("data" ,param->param_data );
21 component_buffer_irsp = new queue::Sort_Queue<irsp_t*> * [param->nb_entity];
22 component_buffer_drsp = new queue::Sort_Queue<drsp_t*> * [param->nb_entity];
23
24 for (uint32_t i=0; i<param->nb_component_tty; i++)
25 {
26 uint32_t tty_size = param->param_tty[i]->nb_tty * 16;
27
28 data::Entity entity = component_data->entity(param->tty_address[i], tty_size);
29 if (entity.present == false)
30 {
31 std::cerr << "<Environnement::Environnement> The tty [" << i << "] have not a segment in the segment table" << std::endl;
32 exit (1);
33 }
34 entity.segment->define_target(data::TYPE_TARGET_TTY,i);
35 }
36
37 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
38 {
39 uint32_t ramlock_size = param->param_ramlock[i]->_size;
40 data::Entity entity = component_data->entity(param->ramlock_address[i], ramlock_size);
41 if (entity.present == false)
42 {
43 std::cerr << "<Environnement::Environnement> The ramlock [" << i << "] have not a segment in the segment table" << std::endl;
44 exit (1);
45 }
46 entity.segment->define_target(data::TYPE_TARGET_RAMLOCK,i);
47 }
48
49 {
50 data::Entity entity = component_data->entity(param->sim2os_address, param->sim2os_size);
51 if (entity.present == false)
52 {
53 std::cerr << "<Environnement::Environnement> The sim2os have not a segment in the segment table" << std::endl;
54 exit (1);
55 }
56 entity.segment->define_target(data::TYPE_TARGET_SIM2OS,0);
57 }
58
59 for (uint32_t i=0; i<param->nb_entity; i++)
60 {
61 component_buffer_irsp [i] = new queue::Sort_Queue<irsp_t*> ("buffer_irsp_"+i,param->param_buffer_irsp [i]);
62 component_buffer_drsp [i] = new queue::Sort_Queue<drsp_t*> ("buffer_drsp_"+i,param->param_buffer_drsp [i]);
63 }
64
65 uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction ,param->nb_entity);
66 uint32_t max_instruction_size = morpheo::max<uint32_t>(param->iaccess_size_instruction,param->nb_entity);
67 uint32_t max_data_size = morpheo::max<uint32_t>(param->daccess_size_data ,param->nb_entity);
68
69 read_iram = new char * [max_nb_instruction];
70 for (uint32_t i=0; i<max_nb_instruction; i++)
71 read_iram [i] = new char [max_instruction_size];
72
73 read_dram = new char * [1];
74 read_dram[0] = new char [max_data_size/8];
75 write_dram = new char [max_data_size/8];
76 context_stop = new bool [param->nb_entity];
77 for (uint32_t i=0; i<param->nb_entity; ++i)
78 context_stop [i] = false;
79 nb_context_stop = 0;
80
81 // Port
82 CLOCK = new sc_in_clk ("CLOCK ");
83 NRESET = new sc_in<bool> ("NRESET");
84
85 ICACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
86 ICACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
87 ICACHE_REQ_CONTEXT_ID = new sc_in <Ticache_context_t > ** [param->nb_entity];
88 ICACHE_REQ_PACKET_ID = new sc_in <Ticache_packet_t > ** [param->nb_entity];
89 ICACHE_REQ_ADDRESS = new sc_in <Ticache_address_t > ** [param->nb_entity];
90 ICACHE_REQ_TYPE = new sc_in <Ticache_type_t > ** [param->nb_entity];
91
92 ICACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
93 ICACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
94 ICACHE_RSP_CONTEXT_ID = new sc_out<Ticache_context_t > ** [param->nb_entity];
95 ICACHE_RSP_PACKET_ID = new sc_out<Ticache_packet_t > ** [param->nb_entity];
96
97 ICACHE_RSP_INSTRUCTION= new sc_out<Ticache_instruction_t> *** [param->nb_entity];//[nb_instruction]
98 ICACHE_RSP_ERROR = new sc_out<Ticache_error_t > ** [param->nb_entity];
99
100 DCACHE_REQ_VAL = new sc_in <Tcontrol_t > ** [param->nb_entity];
101 DCACHE_REQ_ACK = new sc_out<Tcontrol_t > ** [param->nb_entity];
102 DCACHE_REQ_CONTEXT_ID = new sc_in <Tdcache_context_t > ** [param->nb_entity];
103 DCACHE_REQ_PACKET_ID = new sc_in <Tdcache_packet_t > ** [param->nb_entity];
104 DCACHE_REQ_ADDRESS = new sc_in <Tdcache_address_t > ** [param->nb_entity];
105 DCACHE_REQ_TYPE = new sc_in <Tdcache_type_t > ** [param->nb_entity];
106 DCACHE_REQ_WDATA = new sc_in <Tdcache_data_t > ** [param->nb_entity];
107
108 DCACHE_RSP_VAL = new sc_out<Tcontrol_t > ** [param->nb_entity];
109 DCACHE_RSP_ACK = new sc_in <Tcontrol_t > ** [param->nb_entity];
110 DCACHE_RSP_CONTEXT_ID = new sc_out<Tdcache_context_t > ** [param->nb_entity];
111 DCACHE_RSP_PACKET_ID = new sc_out<Tdcache_packet_t > ** [param->nb_entity];
112 DCACHE_RSP_RDATA = new sc_out<Tdcache_data_t > ** [param->nb_entity];
113 DCACHE_RSP_ERROR = new sc_out<Tdcache_error_t > ** [param->nb_entity];
114
115 for (uint32_t i=0; i<param->nb_entity; i++)
116 {
117 ICACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
118 ICACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
119 ICACHE_REQ_CONTEXT_ID [i] = new sc_in <Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
120 ICACHE_REQ_PACKET_ID [i] = new sc_in <Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
121 ICACHE_REQ_ADDRESS [i] = new sc_in <Ticache_address_t > * [param->icache_dedicated_nb_port[i]];
122 ICACHE_REQ_TYPE [i] = new sc_in <Ticache_type_t > * [param->icache_dedicated_nb_port[i]];
123
124 ICACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
125 ICACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->icache_dedicated_nb_port[i]];
126 ICACHE_RSP_CONTEXT_ID [i] = new sc_out<Ticache_context_t > * [param->icache_dedicated_nb_port[i]];
127 ICACHE_RSP_PACKET_ID [i] = new sc_out<Ticache_packet_t > * [param->icache_dedicated_nb_port[i]];
128 ICACHE_RSP_INSTRUCTION[i] = new sc_out<Ticache_instruction_t> ** [param->icache_dedicated_nb_port[i]];//[nb_instruction]
129 ICACHE_RSP_ERROR [i] = new sc_out<Ticache_error_t > * [param->icache_dedicated_nb_port[i]];
130
131 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
132 {
133 ICACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
134 ICACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
135 ICACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Ticache_context_t > ("");
136 ICACHE_REQ_PACKET_ID [i][j] = new sc_in <Ticache_packet_t > ("");
137 ICACHE_REQ_ADDRESS [i][j] = new sc_in <Ticache_address_t > ("");
138 ICACHE_REQ_TYPE [i][j] = new sc_in <Ticache_type_t > ("");
139
140 ICACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
141 ICACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
142 ICACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Ticache_context_t > ("");
143 ICACHE_RSP_PACKET_ID [i][j] = new sc_out<Ticache_packet_t > ("");
144 ICACHE_RSP_ERROR [i][j] = new sc_out<Ticache_error_t > ("");
145
146 ICACHE_RSP_INSTRUCTION [i][j] = new sc_out<Ticache_instruction_t> * [param->iaccess_nb_instruction[i]];
147
148 for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
149 ICACHE_RSP_INSTRUCTION [i][j][k] = new sc_out<Ticache_instruction_t> ("");
150 }
151
152 DCACHE_REQ_VAL [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
153 DCACHE_REQ_ACK [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
154 DCACHE_REQ_CONTEXT_ID [i] = new sc_in <Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
155 DCACHE_REQ_PACKET_ID [i] = new sc_in <Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
156 DCACHE_REQ_ADDRESS [i] = new sc_in <Tdcache_address_t > * [param->dcache_dedicated_nb_port[i]];
157 DCACHE_REQ_TYPE [i] = new sc_in <Tdcache_type_t > * [param->dcache_dedicated_nb_port[i]];
158 DCACHE_REQ_WDATA [i] = new sc_in <Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
159
160 DCACHE_RSP_VAL [i] = new sc_out<Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
161 DCACHE_RSP_ACK [i] = new sc_in <Tcontrol_t > * [param->dcache_dedicated_nb_port[i]];
162 DCACHE_RSP_CONTEXT_ID [i] = new sc_out<Tdcache_context_t > * [param->dcache_dedicated_nb_port[i]];
163 DCACHE_RSP_PACKET_ID [i] = new sc_out<Tdcache_packet_t > * [param->dcache_dedicated_nb_port[i]];
164 DCACHE_RSP_RDATA [i] = new sc_out<Tdcache_data_t > * [param->dcache_dedicated_nb_port[i]];
165 DCACHE_RSP_ERROR [i] = new sc_out<Tdcache_error_t > * [param->dcache_dedicated_nb_port[i]];
166
167 for (uint32_t j=0; j<param->dcache_dedicated_nb_port[i]; j++)
168 {
169 DCACHE_REQ_VAL [i][j] = new sc_in <Tcontrol_t > ("");
170 DCACHE_REQ_ACK [i][j] = new sc_out<Tcontrol_t > ("");
171 DCACHE_REQ_CONTEXT_ID [i][j] = new sc_in <Tdcache_context_t > ("");
172 DCACHE_REQ_PACKET_ID [i][j] = new sc_in <Tdcache_packet_t > ("");
173 DCACHE_REQ_ADDRESS [i][j] = new sc_in <Tdcache_address_t > ("");
174 DCACHE_REQ_TYPE [i][j] = new sc_in <Tdcache_type_t > ("");
175 DCACHE_REQ_WDATA [i][j] = new sc_in <Tdcache_data_t > ("");
176
177 DCACHE_RSP_VAL [i][j] = new sc_out<Tcontrol_t > ("");
178 DCACHE_RSP_ACK [i][j] = new sc_in <Tcontrol_t > ("");
179 DCACHE_RSP_CONTEXT_ID [i][j] = new sc_out<Tdcache_context_t > ("");
180 DCACHE_RSP_PACKET_ID [i][j] = new sc_out<Tdcache_packet_t > ("");
181 DCACHE_RSP_RDATA [i][j] = new sc_out<Tdcache_data_t > ("");
182 DCACHE_RSP_ERROR [i][j] = new sc_out<Tdcache_error_t > ("");
183 }
184 }
185
186 icache_req_ack = new Tcontrol_t * [param->nb_entity];
187 icache_rsp_val = new Tcontrol_t * [param->nb_entity];
188 dcache_req_ack = new Tcontrol_t * [param->nb_entity];
189 dcache_rsp_val = new Tcontrol_t * [param->nb_entity];
190
191 for (uint32_t i=0; i<param->nb_entity; i++)
192 {
193 icache_req_ack [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
194 icache_rsp_val [i] = new Tcontrol_t [param->icache_dedicated_nb_port[i]];
195 dcache_req_ack [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
196 dcache_rsp_val [i] = new Tcontrol_t [param->dcache_dedicated_nb_port[i]];
197 }
198
199 // *****[ Definition of method ]*****
200 SC_METHOD (transition);
201 dont_initialize ();
202 sensitive << (*(CLOCK)).pos();
203
204 SC_METHOD (genMoore);
205 dont_initialize ();
206 sensitive << (*(CLOCK)).neg();
207
208 }
209
210 Environment::~Environment (void)
211 {
212 for (uint32_t i=0; i<param->nb_entity; i++)
213 {
214 delete [] icache_req_ack [i];
215 delete [] icache_rsp_val [i];
216 delete [] dcache_req_ack [i];
217 delete [] dcache_rsp_val [i];
218 }
219
220 delete [] icache_req_ack;
221 delete [] icache_rsp_val;
222 delete [] dcache_req_ack;
223 delete [] dcache_rsp_val;
224
225 delete CLOCK ;
226 delete NRESET;
227
228 for (uint32_t i=0; i<param->nb_entity; i++)
229 {
230 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
231 {
232 delete ICACHE_REQ_VAL [i][j];
233 delete ICACHE_REQ_ACK [i][j];
234 delete ICACHE_REQ_CONTEXT_ID [i][j];
235 delete ICACHE_REQ_PACKET_ID [i][j];
236 delete ICACHE_REQ_ADDRESS [i][j];
237 delete ICACHE_REQ_TYPE [i][j];
238 delete ICACHE_RSP_VAL [i][j];
239 delete ICACHE_RSP_ACK [i][j];
240 delete ICACHE_RSP_CONTEXT_ID [i][j];
241 delete ICACHE_RSP_PACKET_ID [i][j];
242 delete ICACHE_RSP_ERROR [i][j];
243
244 for (uint32_t k=0; k<param->iaccess_nb_instruction[i]; k++)
245 delete ICACHE_RSP_INSTRUCTION [i][j][k];
246
247 delete [] ICACHE_RSP_INSTRUCTION [i][j];
248 }
249 delete [] ICACHE_REQ_VAL [i];
250 delete [] ICACHE_REQ_ACK [i];
251 delete [] ICACHE_REQ_CONTEXT_ID [i];
252 delete [] ICACHE_REQ_PACKET_ID [i];
253 delete [] ICACHE_REQ_ADDRESS [i];
254 delete [] ICACHE_REQ_TYPE [i];
255 delete [] ICACHE_RSP_VAL [i];
256 delete [] ICACHE_RSP_ACK [i];
257 delete [] ICACHE_RSP_CONTEXT_ID [i];
258 delete [] ICACHE_RSP_PACKET_ID [i];
259 delete [] ICACHE_RSP_ERROR [i];
260 delete [] ICACHE_RSP_INSTRUCTION [i];
261 }
262
263 delete [] ICACHE_REQ_VAL ;
264 delete [] ICACHE_REQ_ACK ;
265 delete [] ICACHE_REQ_CONTEXT_ID ;
266 delete [] ICACHE_REQ_PACKET_ID ;
267 delete [] ICACHE_REQ_ADDRESS ;
268 delete [] ICACHE_REQ_TYPE ;
269 delete [] ICACHE_RSP_VAL ;
270 delete [] ICACHE_RSP_ACK ;
271 delete [] ICACHE_RSP_CONTEXT_ID ;
272 delete [] ICACHE_RSP_PACKET_ID ;
273 delete [] ICACHE_RSP_INSTRUCTION;
274 delete [] ICACHE_RSP_ERROR ;
275
276 for (uint32_t i=0; i<param->nb_entity; i++)
277 {
278 for (uint32_t j=0; j<param->icache_dedicated_nb_port[i]; j++)
279 {
280 delete DCACHE_REQ_VAL [i][j];
281 delete DCACHE_REQ_ACK [i][j];
282 delete DCACHE_REQ_CONTEXT_ID [i][j];
283 delete DCACHE_REQ_PACKET_ID [i][j];
284 delete DCACHE_REQ_ADDRESS [i][j];
285 delete DCACHE_REQ_TYPE [i][j];
286 delete DCACHE_REQ_WDATA [i][j];
287 delete DCACHE_RSP_VAL [i][j];
288 delete DCACHE_RSP_ACK [i][j];
289 delete DCACHE_RSP_CONTEXT_ID [i][j];
290 delete DCACHE_RSP_PACKET_ID [i][j];
291 delete DCACHE_RSP_RDATA [i][j];
292 delete DCACHE_RSP_ERROR [i][j];
293 }
294
295 delete [] DCACHE_REQ_VAL [i];
296 delete [] DCACHE_REQ_ACK [i];
297 delete [] DCACHE_REQ_CONTEXT_ID [i];
298 delete [] DCACHE_REQ_PACKET_ID [i];
299 delete [] DCACHE_REQ_ADDRESS [i];
300 delete [] DCACHE_REQ_TYPE [i];
301 delete [] DCACHE_REQ_WDATA [i];
302 delete [] DCACHE_RSP_VAL [i];
303 delete [] DCACHE_RSP_ACK [i];
304 delete [] DCACHE_RSP_CONTEXT_ID [i];
305 delete [] DCACHE_RSP_PACKET_ID [i];
306 delete [] DCACHE_RSP_RDATA [i];
307 delete [] DCACHE_RSP_ERROR [i];
308 }
309
310 delete [] DCACHE_REQ_VAL ;
311 delete [] DCACHE_REQ_ACK ;
312 delete [] DCACHE_REQ_CONTEXT_ID ;
313 delete [] DCACHE_REQ_PACKET_ID ;
314 delete [] DCACHE_REQ_ADDRESS ;
315 delete [] DCACHE_REQ_TYPE ;
316 delete [] DCACHE_REQ_WDATA ;
317 delete [] DCACHE_RSP_VAL ;
318 delete [] DCACHE_RSP_ACK ;
319 delete [] DCACHE_RSP_CONTEXT_ID ;
320 delete [] DCACHE_RSP_PACKET_ID ;
321 delete [] DCACHE_RSP_RDATA ;
322 delete [] DCACHE_RSP_ERROR ;
323
324 delete [] context_stop;
325 delete [] write_dram;
326 delete [] read_dram [0];
327 delete [] read_dram;
328
329 uint32_t max_nb_instruction = morpheo::max<uint32_t>(param->iaccess_nb_instruction,param->nb_entity);
330 for (uint32_t i=0; i<max_nb_instruction; i++)
331 delete [] read_iram [i];
332 delete [] read_iram;
333
334 for (uint32_t i=0; i<param->nb_entity; i++)
335 {
336 while (not component_buffer_irsp [i]->empty())
337 {
338 delete component_buffer_irsp [i]->read(0)._data;
339 component_buffer_irsp [i]->pop();
340 }
341 while (not component_buffer_drsp [i]->empty())
342 {
343 delete component_buffer_drsp [i]->read(0)._data;
344 component_buffer_drsp [i]->pop();
345 }
346
347 delete component_buffer_irsp [i];
348 delete component_buffer_drsp [i];
349 }
350 delete [] component_buffer_irsp;
351 delete [] component_buffer_drsp;
352
353 delete component_data;
354 delete component_sim2os;
355 for (uint32_t i=0; i<param->nb_component_ramlock; i++)
356 delete component_ramlock [i];
357 delete [] component_ramlock;
358 for (uint32_t i=0; i<param->nb_component_tty; i++)
359 delete component_tty [i];
360 delete [] component_tty;
361 delete component_cache;
362
363 }
364
365};
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