source: trunk/IPs/systemC/Environment/src/Environment_genMoore.cpp

#include "../include/Environment.h"
#include "../../processor/Morpheo/Common/include/Systemc.h"

using namespace morpheo;

namespace environment {

  void Environment::genMoore (void)
  {
    _cout(ENVIRONMENT, " [%d] <Environment::genMoore>\n",static_cast<uint32_t>(simulation_cycle()));

    //Scan all entity and for each entity scan all port
    for (uint32_t i = 0; i < param->nb_entity; i++)
      {
        //=============================================================================
        //===== [ ICACHE ]=============================================================
        //=============================================================================
        
        //-----------------------------------------------------------------------------
        //----- [ Request ]------------------------------------------------------------
        //-----------------------------------------------------------------------------
        {
          uint32_t nb_slot_free = component_buffer_irsp [i]->nb_slot_free ();
          for (uint32_t j=0; j<param->icache_dedicated_nb_port [i]; j ++)
            {
              icache_req_ack [i][j] = (j < nb_slot_free);
              ICACHE_REQ_ACK [i][j]->write (icache_req_ack [i][j]);
            }
        }

        //-----------------------------------------------------------------------------
        //----- [ Respons ]------------------------------------------------------------
        //-----------------------------------------------------------------------------
        {
          // init
          for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++)
            {
              icache_rsp_val [i][j] = 0;
              icache_rsp_num [i][j] = 0;
            }

          _cout(ENVIRONMENT, "  * buffer_irsp [%d] : nb_slot_use %d\n",i,component_buffer_irsp [i]->nb_slot_use());
          for (uint32_t j = 0; j+1 <= component_buffer_irsp [i]->nb_slot_use(); j ++)
            {
              // Test the number of element in the respons's buffer
              
              queue::slot_t<irsp_t*> slot = component_buffer_irsp [i]->read(j);
              
              uint32_t port = slot._data->port;
              
              bool val = ((slot._delay == 0) and (icache_rsp_val [i][port] == 0));

              _cout(ENVIRONMENT, "  * buffer_irsp [%d][%d] - delay %d - port %d\n",i,j,slot._delay,port);

              
              if (val)
                {
                  _cout(ENVIRONMENT, "  * ICACHE_RSP [%d][%d] - respons valid\n",i,port);
                  
                  icache_rsp_val        [i][port] = 1;
                  icache_rsp_num        [i][port] = j;
                                
                  ICACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist
                  ICACHE_RSP_PACKET_ID  [i][port]->write(slot._data->pktid); // TODO : test if exist
                  ICACHE_RSP_ERROR      [i][port]->write(slot._data->error);
                  
                  for (uint32_t k = 0; k < param->iaccess_nb_instruction[i]; k ++)
                    {
                      Ticache_instruction_t data = 0;
                      
                      atoi (slot._data->data[k], data, param->iaccess_size_instruction[i]/8);
                      
                      ICACHE_RSP_INSTRUCTION [i][port][k]->write(data);
                    }
                }
            }
          
          for (uint32_t j = 0; j < param->icache_dedicated_nb_port [i]; j ++)
            ICACHE_RSP_VAL [i][j]->write (icache_rsp_val [i][j]);
        }
        
        //=============================================================================
        //===== [ DCACHE ]=============================================================
        //=============================================================================
        
        //-----------------------------------------------------------------------------
        //----- [ Request ]------------------------------------------------------------
        //-----------------------------------------------------------------------------
        {
          uint32_t nb_slot_free = component_buffer_drsp [i]->nb_slot_free ();
          for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++)
            {
              dcache_req_ack [i][j] = (j < nb_slot_free);
              DCACHE_REQ_ACK [i][j]->write (dcache_req_ack [i][j]);
            }
        }
        
        //-----------------------------------------------------------------------------
        //----- [ Respons ]------------------------------------------------------------
        //-----------------------------------------------------------------------------
        {
          // init
          for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++)
            {
              dcache_rsp_val [i][j] = 0;
              dcache_rsp_num [i][j] = 0;
            }

          for (uint32_t j = 0; j+1 <= component_buffer_drsp [i]->nb_slot_use(); j ++)
            {
              queue::slot_t<drsp_t*> slot = component_buffer_drsp [i]->read(j);
              
              uint32_t port = slot._data->port;
              bool val = ((slot._delay == 0) and (dcache_rsp_val [i][port] == 0));
              
              if (val)
                {
                  _cout(ENVIRONMENT, "  * DCACHE_RSP [%d][%d] - respons valid\n",i,port);
                  
                  dcache_rsp_val        [i][port] = 1;
                  dcache_rsp_num        [i][port] = j;
                  
                  DCACHE_RSP_CONTEXT_ID [i][port]->write(slot._data->trdid); // TODO : test if exist
                  DCACHE_RSP_PACKET_ID  [i][port]->write(slot._data->pktid); // TODO : test if exist
                  DCACHE_RSP_ERROR      [i][port]->write(slot._data->error);
                  
                  Tdcache_data_t data = 0;
                  atoi (slot._data->data[0], data, param->daccess_size_data[i]/8);
                  
                  DCACHE_RSP_RDATA      [i][port]->write(data);
                }
            }

          for (uint32_t j = 0; j < param->dcache_dedicated_nb_port [i]; j ++)
            DCACHE_RSP_VAL [i][j]->write (dcache_rsp_val [i][j]);
        }
      }
  }

};