[81] | 1 | #include "../include/Environment.h" |
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| 2 | |
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| 3 | namespace environment { |
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| 4 | |
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| 5 | void Environment::transition (void) |
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| 6 | { |
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| 7 | if (NRESET->read() == 0) |
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| 8 | { |
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| 9 | reset (); |
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| 10 | } |
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| 11 | else |
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| 12 | { |
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| 13 | //============================================================================= |
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| 14 | //===== [ ICACHE - RESPONS ]=================================================== |
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| 15 | //============================================================================= |
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| 16 | for (uint32_t i = 0; i < param->nb_entity; i++) |
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| 17 | for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--) |
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| 18 | if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read()) |
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| 19 | { |
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| 20 | delete component_buffer_irsp [i]->read(j)._data; |
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| 21 | component_buffer_irsp [i]->pop(j); |
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| 22 | } |
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| 23 | //============================================================================= |
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| 24 | //===== [ DCACHE - RESPONS ]=================================================== |
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| 25 | //============================================================================= |
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| 26 | for (uint32_t i = 0; i < param->nb_entity; i++) |
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| 27 | for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--) |
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| 28 | if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read()) |
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| 29 | { |
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| 30 | delete component_buffer_drsp [i]->read(j)._data; |
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| 31 | component_buffer_drsp [i]->pop(j); |
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| 32 | } |
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| 33 | |
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| 34 | //============================================================================= |
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| 35 | //===== [ ICACHE - RESPONS ]=================================================== |
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| 36 | //============================================================================= |
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| 37 | for (uint32_t i=0; i<param->nb_entity; i++) |
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| 38 | for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++) |
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| 39 | if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j]) |
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| 40 | { |
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| 41 | _cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i); |
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| 42 | |
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| 43 | Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence |
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| 44 | Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence |
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| 45 | Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read(); |
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| 46 | Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read(); |
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| 47 | uint32_t size = param->iaccess_size_address [i]/8; |
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| 48 | |
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| 49 | _cout(ENVIRONMENT," * information\n"); |
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| 50 | _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context)); |
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| 51 | _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet )); |
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| 52 | _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address)); |
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| 53 | _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type )); |
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| 54 | _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size )); |
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| 55 | |
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| 56 | // search the entity |
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| 57 | data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size); |
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| 58 | |
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| 59 | bool uncached ; |
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| 60 | bool bus_error; |
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| 61 | bool must_read = (type == ICACHE_TYPE_LOAD); |
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| 62 | bool must_ack = (type == ICACHE_TYPE_LOAD); |
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| 63 | bool must_ack_on_error = (type == ICACHE_TYPE_LOAD); |
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| 64 | |
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| 65 | // Test the type of the address : if != MEMORY -> error |
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| 66 | if ((entity.present == true) and |
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| 67 | (entity.segment->getType() == data::TYPE_TARGET_MEMORY)) |
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| 68 | { |
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| 69 | _cout(ENVIRONMENT, " * OK !\n"); |
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| 70 | bus_error = false; |
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| 71 | uncached = entity.segment->getUncached(); |
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| 72 | |
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| 73 | if (must_read == true) // Test if must read the ram |
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| 74 | { |
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| 75 | _cout(ENVIRONMENT, " * must read\n"); |
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| 76 | // Read all instruction |
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| 77 | for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++) |
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| 78 | { |
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| 79 | uint32_t addr = address+k*(size); |
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| 80 | _cout(ENVIRONMENT, " * addr : %.8x\n",addr); |
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| 81 | |
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| 82 | bus_error |= !component_data->read(addr,size,read_iram[k]); |
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| 83 | |
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| 84 | // Swap if endienness is different |
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| 85 | if (endianness::isSameEndianness(context) == false) |
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| 86 | read_iram[k] = endianness::swapBytes(read_iram[k],size,size); |
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| 87 | } |
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| 88 | } |
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| 89 | } |
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| 90 | else |
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| 91 | { |
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| 92 | _cout(ENVIRONMENT, " * KO !\n"); |
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| 93 | _cout(ENVIRONMENT, " * present : %d\n",entity.present); |
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| 94 | if (entity.present) |
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| 95 | _cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY); |
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| 96 | |
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| 97 | // entity is not present, or is present but is not a memory : have a bus error |
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| 98 | bus_error = true; |
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| 99 | uncached = true; |
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| 100 | } |
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| 101 | |
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| 102 | Cache_Access cache_type = ireq_type2cache_type (type,uncached); |
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| 103 | uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE, |
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| 104 | i, |
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| 105 | j, |
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| 106 | address, |
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| 107 | context, |
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| 108 | cache_type.type, |
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| 109 | cache_type.direction); |
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| 110 | |
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| 111 | _cout(ENVIRONMENT, " * latence : %d\n",latence); |
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| 112 | |
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| 113 | // If is a respons -> compute the latence and push in the write_buffer |
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| 114 | if (must_ack or (must_ack_on_error and bus_error)) |
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| 115 | { |
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| 116 | _cout(ENVIRONMENT, " * must ack\n"); |
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| 117 | |
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| 118 | if (bus_error == true) |
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| 119 | { |
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| 120 | std::cout << "Icache : have a bus error" << std::endl |
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| 121 | << " * entity : " << i << std::endl |
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| 122 | << " * port : " << j << std::endl |
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| 123 | << std::hex |
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| 124 | << " * req_addr : " << address << std::endl |
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| 125 | << std::dec |
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| 126 | << " * req_trdid : " << context << std::endl |
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| 127 | << " * req_pktid : " << packet << std::endl; |
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| 128 | |
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| 129 | // Write in instruction [0] the bad address (only 32bit ....) |
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| 130 | itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8); |
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| 131 | } |
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| 132 | |
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| 133 | // Simplification : the size of a line is a multiple of size_iword (no test) |
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| 134 | _cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i); |
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| 135 | |
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| 136 | irsp_t * rsp = new irsp_t(context, |
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| 137 | packet, |
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| 138 | param->iaccess_nb_instruction[i], |
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| 139 | size, |
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| 140 | read_iram, |
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| 141 | (bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE); |
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| 142 | component_buffer_irsp [i]->push(latence,rsp); |
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| 143 | } |
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| 144 | |
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| 145 | _cout(ENVIRONMENT, " * End request\n"); |
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| 146 | } |
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| 147 | |
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| 148 | //============================================================================= |
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| 149 | //===== [ DCACHE - REQUEST ]=================================================== |
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| 150 | //============================================================================= |
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| 151 | for (uint32_t i=0; i<param->nb_entity; i++) |
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| 152 | for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++) |
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| 153 | if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j]) |
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| 154 | { |
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| 155 | _cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i); |
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| 156 | |
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| 157 | Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence |
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| 158 | Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence |
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| 159 | Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read(); |
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| 160 | Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read(); |
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| 161 | Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read(); |
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| 162 | uint32_t size = param->daccess_size_data [i]/8; |
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| 163 | |
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| 164 | // _cout(ENVIRONMENT," * information\n"); |
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| 165 | // _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context)); |
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| 166 | // _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet )); |
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| 167 | // _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address)); |
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| 168 | // _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type )); |
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| 169 | // _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size )); |
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| 170 | |
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| 171 | // search the entity |
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| 172 | data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size); |
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| 173 | |
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| 174 | std::cout << entity << std::endl; |
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| 175 | |
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| 176 | bool uncached = false; |
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| 177 | bool bus_error = false; |
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| 178 | |
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| 179 | uint32_t nb_bytes = size; |
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| 180 | bool must_read ; |
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| 181 | bool must_write; |
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| 182 | bool must_ack ; |
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| 183 | bool must_ack_on_error; |
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| 184 | |
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| 185 | switch (type) |
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| 186 | { |
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| 187 | case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;} |
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| 188 | case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;} |
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| 189 | case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;} |
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| 190 | case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;} |
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| 191 | case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;} |
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| 192 | case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;} |
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| 193 | case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;} |
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| 194 | case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;} |
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| 195 | case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;} |
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| 196 | case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;} |
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| 197 | case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;} |
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| 198 | case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;} |
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| 199 | case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;} |
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| 200 | default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;} |
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| 201 | } |
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| 202 | |
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| 203 | // Test the type of the address |
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| 204 | if (entity.present == true) |
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| 205 | { |
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| 206 | switch (entity.segment->getType()) |
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| 207 | { |
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| 208 | //************************************************************** |
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| 209 | //*****[ TTY ]************************************************** |
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| 210 | //************************************************************** |
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| 211 | case data::TYPE_TARGET_TTY : |
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| 212 | { |
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| 213 | // Can't read a tty, must write |
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| 214 | if (must_write == false) |
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| 215 | { |
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| 216 | bus_error = true; |
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| 217 | break; |
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| 218 | } |
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| 219 | |
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| 220 | uint32_t num_tty = (address - entity.segment->getBase())>>4; |
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| 221 | uint32_t num_print = ((address>>2) & 0x3); |
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| 222 | _cout(ENVIRONMENT," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print); |
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| 223 | |
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| 224 | switch (num_print) |
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| 225 | { |
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| 226 | case 0 : // Write TTY |
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| 227 | { |
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| 228 | uint32_t num_component_tty = entity.segment->getIndex(); |
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| 229 | char char_write = static_cast<char>(wdata&0xff); |
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| 230 | bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write); |
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| 231 | break; |
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| 232 | } |
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| 233 | case 1 : // STOP |
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| 234 | { |
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| 235 | printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" |
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| 236 | ,static_cast<uint32_t>(sc_simulation_time()) |
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| 237 | ,static_cast<uint32_t>(address ) |
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| 238 | ,static_cast<uint32_t>((wdata>>24)&0xff) |
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| 239 | ,static_cast<uint32_t>((wdata>>16)&0xff) |
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| 240 | ,static_cast<uint32_t>((wdata>> 8)&0xff) |
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| 241 | ,static_cast<uint32_t>((wdata>> 0)&0xff) |
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| 242 | ); |
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| 243 | |
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| 244 | // if (context_stop [context] == false) |
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| 245 | // { |
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| 246 | // context_stop [context] = true; |
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| 247 | // nb_context_stop ++; |
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| 248 | |
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| 249 | // if (nb_context_stop >= nb_context) |
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| 250 | // sc_stop(); |
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| 251 | // } |
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| 252 | |
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| 253 | break; |
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| 254 | } |
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| 255 | case 2 : // PRINT |
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| 256 | { |
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| 257 | printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" |
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| 258 | ,static_cast<uint32_t>(sc_simulation_time()) |
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| 259 | ,static_cast<uint32_t>(address ) |
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| 260 | ,static_cast<uint32_t>((wdata>>24)&0xff) |
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| 261 | ,static_cast<uint32_t>((wdata>>16)&0xff) |
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| 262 | ,static_cast<uint32_t>((wdata>> 8)&0xff) |
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| 263 | ,static_cast<uint32_t>((wdata>> 0)&0xff) |
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| 264 | ); |
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| 265 | |
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| 266 | break; |
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| 267 | } |
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| 268 | default : |
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| 269 | { |
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| 270 | printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print); |
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| 271 | bus_error = true; |
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| 272 | } |
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| 273 | } |
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| 274 | break; |
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| 275 | } |
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| 276 | |
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| 277 | //************************************************************** |
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| 278 | //*****[ MEMORY ]*********************************************** |
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| 279 | //************************************************************** |
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| 280 | case data::TYPE_TARGET_MEMORY : |
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| 281 | { |
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| 282 | _cout(ENVIRONMENT,"MEMORY\n"); |
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| 283 | _cout(ENVIRONMENT,"access : %x\n",address); |
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| 284 | |
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| 285 | if (must_read == true) |
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| 286 | { |
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| 287 | // Read |
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| 288 | _cout(ENVIRONMENT," * Read (%d bytes)\n",size); |
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| 289 | bus_error |= !component_data->read(address,size,read_dram[0]); // always read a complete word |
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| 290 | |
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| 291 | _cout(ENVIRONMENT," * Rdata : "); |
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| 292 | for (uint32_t i=0; i<size; i++) |
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| 293 | _cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i])); |
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| 294 | _cout(ENVIRONMENT,".\n"); |
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| 295 | |
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| 296 | // Multiple copy |
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| 297 | for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes) |
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| 298 | memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes); |
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| 299 | |
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| 300 | // Permutation if problem of endianness |
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| 301 | if (endianness::isSameEndianness(context) == false) |
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| 302 | read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes); |
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| 303 | } |
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| 304 | |
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| 305 | if (must_write == true) |
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| 306 | { |
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| 307 | // Write |
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| 308 | _cout(ENVIRONMENT," * Write (%d bytes)\n",size); |
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| 309 | _cout(ENVIRONMENT," * Wdata : %x\n",wdata); |
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| 310 | itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes); |
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| 311 | |
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| 312 | // for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++) |
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| 313 | // write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes); |
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| 314 | } |
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| 315 | |
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| 316 | break; |
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| 317 | } |
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| 318 | //************************************************************** |
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| 319 | //*****[ RAMLOCK ]********************************************** |
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| 320 | //************************************************************** |
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| 321 | case data::TYPE_TARGET_RAMLOCK : |
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| 322 | { |
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| 323 | // Access is on a byte, else error |
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| 324 | if (nb_bytes != 1) |
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| 325 | { |
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| 326 | bus_error = true; |
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| 327 | break; |
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| 328 | } |
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| 329 | |
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| 330 | uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access |
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| 331 | uint32_t num_component_ramlock = entity.segment->getIndex(); |
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| 332 | |
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| 333 | // No test : because out of range |
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| 334 | |
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| 335 | // bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock); |
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| 336 | |
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| 337 | // if (bus_error == true) |
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| 338 | // break; |
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| 339 | |
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| 340 | memset (read_dram[0],0,size); |
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| 341 | |
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| 342 | if (must_read == true) |
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| 343 | read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock)); |
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| 344 | if (must_write == true) |
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| 345 | read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock)); |
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| 346 | |
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| 347 | break; |
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| 348 | } |
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| 349 | |
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| 350 | //************************************************************** |
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| 351 | //*****[ SIM2OS ]*********************************************** |
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| 352 | //************************************************************** |
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| 353 | case data::TYPE_TARGET_SIM2OS : |
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| 354 | { |
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| 355 | // Mapping : |
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| 356 | // [0] number of service - Wonly - A write in this register lunch the execution of service |
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| 357 | // [1] result - Ronly - Content the result of the service |
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| 358 | // [2] error - Ronly - Content the code of errno |
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| 359 | // [3+] argument - Wonly - it's all argument to execute the service |
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| 360 | |
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| 361 | uint32_t num_reg = (address - entity.segment->getBase())>>2; |
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| 362 | |
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| 363 | switch (num_reg) |
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| 364 | { |
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| 365 | case 0 : // ---> number of service |
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| 366 | { |
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| 367 | if (must_write == false) |
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| 368 | { |
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| 369 | std::cerr << "<Environment::transition> SIM2OS[0] is not accessible in Read" << std::endl; |
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| 370 | bus_error = true; |
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| 371 | } |
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| 372 | else |
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| 373 | { |
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| 374 | _cout(ENVIRONMENT,"<sim2os> service : %x\n",wdata); |
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| 375 | component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata))); |
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| 376 | } |
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| 377 | break; |
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| 378 | } |
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| 379 | case 1 : // ---> result |
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| 380 | { |
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| 381 | if (must_read == false) |
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| 382 | { |
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| 383 | std::cerr << "<Environment::transition> SIM2OS[1] is not accessible in Write" << std::endl; |
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| 384 | bus_error = true; |
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| 385 | } |
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| 386 | else |
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| 387 | { |
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| 388 | // Decomposition en groupe octect |
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| 389 | Tdcache_data_t result = (Tdcache_data_t)(component_sim2os->result); |
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| 390 | _cout(ENVIRONMENT,"<sim2os> result : %x\n",result); |
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| 391 | |
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| 392 | itoa<Tdcache_data_t>(result,read_dram[0],size); |
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| 393 | } |
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| 394 | break; |
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| 395 | } |
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| 396 | case 2 : // ---> error |
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| 397 | { |
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| 398 | if (must_read == false) |
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| 399 | { |
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| 400 | std::cerr << "<Environment::transition> SIM2OS[2] is not accessible in Write" << std::endl; |
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| 401 | bus_error = true; |
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| 402 | } |
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| 403 | else |
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| 404 | { |
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| 405 | // Decomposition en groupe octect |
---|
| 406 | Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error; |
---|
| 407 | _cout(ENVIRONMENT,"<sim2os> error : %x\n",error); |
---|
| 408 | |
---|
| 409 | itoa<Tdcache_data_t>(error,read_dram[0],size); |
---|
| 410 | } |
---|
| 411 | |
---|
| 412 | break; |
---|
| 413 | } |
---|
| 414 | default : //---> argument |
---|
| 415 | { |
---|
| 416 | if (must_write == false) |
---|
| 417 | { |
---|
| 418 | std::cerr << "<Environment::transition> SIM2OS[" << num_reg << "] is not accessible in Read" << std::endl; |
---|
| 419 | bus_error = true; |
---|
| 420 | } |
---|
| 421 | else |
---|
| 422 | { |
---|
| 423 | _cout(ENVIRONMENT,"<sim2os> argument[%d] : %x\n",num_reg-1,wdata); |
---|
| 424 | component_sim2os->parameter(num_reg-2,(void *)wdata); |
---|
| 425 | } |
---|
| 426 | break; |
---|
| 427 | } |
---|
| 428 | } |
---|
| 429 | |
---|
| 430 | break; |
---|
| 431 | } |
---|
| 432 | |
---|
| 433 | default : |
---|
| 434 | { |
---|
| 435 | std::cerr << "<Environment::transition> Dcache_req : Unknow type" << std::endl; |
---|
| 436 | exit(1); |
---|
| 437 | break; |
---|
| 438 | } |
---|
| 439 | } |
---|
| 440 | uncached |= entity.segment->getUncached(); |
---|
| 441 | } |
---|
| 442 | else |
---|
| 443 | { |
---|
| 444 | // entity is not present, or is present but is not a memory : have a bus error |
---|
| 445 | bus_error = true; |
---|
| 446 | uncached = true; |
---|
| 447 | } |
---|
| 448 | |
---|
| 449 | if ((must_write == true) and (bus_error == false)) |
---|
| 450 | { |
---|
| 451 | // Permutation if problem of endianness |
---|
| 452 | if (endianness::isSameEndianness(context) == false) |
---|
| 453 | write_dram = endianness::swapBytes(write_dram, size, nb_bytes); |
---|
| 454 | |
---|
| 455 | bus_error |= !component_data->write(address, nb_bytes, write_dram); // take the good access |
---|
| 456 | } |
---|
| 457 | |
---|
| 458 | // Acces at the cache !!! |
---|
| 459 | // Cache WRITE ALLOCATE (becauce compute latence always; ) |
---|
| 460 | Cache_Access cache_type = dreq_type2cache_type (type,uncached); |
---|
| 461 | uint32_t latence = component_cache->latence(cache::DATA_CACHE, |
---|
| 462 | i, |
---|
| 463 | j, |
---|
| 464 | address, |
---|
| 465 | context, |
---|
| 466 | cache_type.type, |
---|
| 467 | cache_type.direction); |
---|
| 468 | |
---|
| 469 | // If is a respons -> compute the latence and push in the write_buffer |
---|
| 470 | if (must_ack or (must_ack_on_error and bus_error)) |
---|
| 471 | { |
---|
| 472 | if (bus_error == true) |
---|
| 473 | { |
---|
| 474 | std::cout << "Dcache : have a bus error" << std::endl |
---|
| 475 | << " * entity : " << i << std::endl |
---|
| 476 | << " * port : " << j << std::endl |
---|
| 477 | << std::hex |
---|
| 478 | << " * req_addr : 0x" << address << std::endl |
---|
| 479 | << std::dec |
---|
| 480 | << " * req_trdid : " << context << std::endl |
---|
| 481 | << " * req_pktid : " << packet << std::endl; |
---|
| 482 | |
---|
| 483 | // Write in data [0] the bad address (32bit or 64bits ) |
---|
| 484 | itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8); |
---|
| 485 | } |
---|
| 486 | |
---|
| 487 | // Simplification : the size of a line is a multiple of size_iword (no test) |
---|
| 488 | drsp_t * rsp = new drsp_t(context, |
---|
| 489 | packet, |
---|
| 490 | 1, |
---|
| 491 | size, |
---|
| 492 | read_dram, |
---|
| 493 | (bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE); |
---|
| 494 | component_buffer_drsp [i]->push(latence,rsp); |
---|
| 495 | } |
---|
| 496 | |
---|
| 497 | } |
---|
| 498 | //============================================================================= |
---|
| 499 | //===== [ OTHERS ]============================================================= |
---|
| 500 | //============================================================================= |
---|
| 501 | |
---|
| 502 | // Transition for each component |
---|
| 503 | component_cache -> transition(); |
---|
| 504 | for (uint32_t i=0; i<param->nb_entity; i++) |
---|
| 505 | { |
---|
| 506 | component_buffer_irsp [i]->transition(); |
---|
| 507 | component_buffer_drsp [i]->transition(); |
---|
| 508 | } |
---|
| 509 | component_sim2os->transition(); |
---|
| 510 | } |
---|
| 511 | } |
---|
| 512 | |
---|
| 513 | // // ****************** |
---|
| 514 | // // ***** DCACHE ***** |
---|
| 515 | // // ****************** |
---|
| 516 | |
---|
| 517 | // for (uint32_t j = 0; j < nb_dport [i]; j ++) |
---|
| 518 | // { |
---|
| 519 | // // Test if transaction |
---|
| 520 | // // cout << "[" << i << "]" |
---|
| 521 | // // << "[" << j << "] " |
---|
| 522 | // // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " " |
---|
| 523 | // // << "dreq_ack : " << dreq_ack [i][j] << endl; |
---|
| 524 | |
---|
| 525 | // if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false) |
---|
| 526 | // continue; |
---|
| 527 | |
---|
| 528 | // entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8); |
---|
| 529 | |
---|
| 530 | // bool uncached = DCACHE [i][j].REQ_UNC.read(); |
---|
| 531 | // bool bus_error = false; |
---|
| 532 | |
---|
| 533 | // uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read(); |
---|
| 534 | // sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read(); |
---|
| 535 | // sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read(); |
---|
| 536 | // uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read()); |
---|
| 537 | // // A lot of flag |
---|
| 538 | // bool must_read = ((type == DTYPE_READ )); |
---|
| 539 | // bool must_write = ((type == DTYPE_WRITE ) || |
---|
| 540 | // (type == DTYPE_WRITE_ACK ) ); |
---|
| 541 | // bool must_ack = ((type == DTYPE_READ ) || |
---|
| 542 | // (type == DTYPE_WRITE_ACK ) ); |
---|
| 543 | |
---|
| 544 | // // Test the type of the address |
---|
| 545 | // if (entity.present == true) |
---|
| 546 | // { |
---|
| 547 | // switch (entity.segment->getType()) |
---|
| 548 | // { |
---|
| 549 | // // ACCESS AT A RAM |
---|
| 550 | // case data::TYPE_TARGET_MEMORY : |
---|
| 551 | // { |
---|
| 552 | // if (must_read == true) |
---|
| 553 | // { |
---|
| 554 | // // Read |
---|
| 555 | // bus_error |= !component_data->read(addr , |
---|
| 556 | // SIZE_DDATA/8 , // always read a complete word |
---|
| 557 | // read_dram ); |
---|
| 558 | |
---|
| 559 | // for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes) |
---|
| 560 | // memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes); |
---|
| 561 | |
---|
| 562 | // // Permutation if problem of endianness |
---|
| 563 | // if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false) |
---|
| 564 | // read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes); |
---|
| 565 | // } |
---|
| 566 | |
---|
| 567 | // if (must_write == true) |
---|
| 568 | // { |
---|
| 569 | // // Write |
---|
| 570 | // for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++) |
---|
| 571 | // write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes); |
---|
| 572 | // } |
---|
| 573 | // break; |
---|
| 574 | // } |
---|
| 575 | // //ACCESS AT THE TTY |
---|
| 576 | // case TYPE_TTY : |
---|
| 577 | // { |
---|
| 578 | // if (must_write == false) |
---|
| 579 | // { |
---|
| 580 | // bus_error = true; |
---|
| 581 | // break; |
---|
| 582 | // } |
---|
| 583 | // uint32_t num_tty = (addr - entity.segment->getBase())>>4; |
---|
| 584 | // uint32_t num_print = ((addr>>2) & 0x3); |
---|
| 585 | |
---|
| 586 | // switch (num_print) |
---|
| 587 | // { |
---|
| 588 | // case 0 : // Write TTY |
---|
| 589 | // { |
---|
| 590 | // uint32_t num_component_tty = entity.segment->getIndex(); |
---|
| 591 | // char char_write = (char)wdata.range( 7, 0); |
---|
| 592 | // bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write); |
---|
| 593 | // break; |
---|
| 594 | // } |
---|
| 595 | // case 1 : // STOP |
---|
| 596 | // { |
---|
| 597 | // printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" |
---|
| 598 | // ,(unsigned int)sc_simulation_time() |
---|
| 599 | // ,(unsigned int)addr |
---|
| 600 | // ,(unsigned int)wdata.range(31,24) |
---|
| 601 | // ,(unsigned int)wdata.range(23,16) |
---|
| 602 | // ,(unsigned int)wdata.range(15, 8) |
---|
| 603 | // ,(unsigned int)wdata.range( 7, 0) |
---|
| 604 | // ); |
---|
| 605 | |
---|
| 606 | // uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read(); |
---|
| 607 | |
---|
| 608 | // if (context_stop [trdid] == false) |
---|
| 609 | // { |
---|
| 610 | // context_stop [trdid] = true; |
---|
| 611 | // nb_context_stop ++; |
---|
| 612 | |
---|
| 613 | // if (nb_context_stop >= nb_context) |
---|
| 614 | // sc_stop(); |
---|
| 615 | // } |
---|
| 616 | |
---|
| 617 | // break; |
---|
| 618 | // } |
---|
| 619 | // case 2 : // PRINT |
---|
| 620 | // { |
---|
| 621 | // printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" |
---|
| 622 | // ,(unsigned int)sc_simulation_time() |
---|
| 623 | // ,(unsigned int)addr |
---|
| 624 | // ,(unsigned int)wdata.range(31,24) |
---|
| 625 | // ,(unsigned int)wdata.range(23,16) |
---|
| 626 | // ,(unsigned int)wdata.range(15, 8) |
---|
| 627 | // ,(unsigned int)wdata.range( 7, 0) |
---|
| 628 | // ); |
---|
| 629 | |
---|
| 630 | // break; |
---|
| 631 | // } |
---|
| 632 | // default : |
---|
| 633 | // { |
---|
| 634 | // printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print); |
---|
| 635 | // exit(1); |
---|
| 636 | // } |
---|
| 637 | // } |
---|
| 638 | |
---|
| 639 | // break; |
---|
| 640 | // } |
---|
| 641 | // case TYPE_RAMLOCK : |
---|
| 642 | // { |
---|
| 643 | // // Access is on a byte, else error |
---|
| 644 | // if (nb_bytes != 1) |
---|
| 645 | // { |
---|
| 646 | // bus_error = true; |
---|
| 647 | // break; |
---|
| 648 | // } |
---|
| 649 | // uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access |
---|
| 650 | // uint32_t num_component_ramlock = entity.segment->getIndex(); |
---|
| 651 | // bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock); |
---|
| 652 | |
---|
| 653 | // if (bus_error == true) |
---|
| 654 | // break; |
---|
| 655 | |
---|
| 656 | // memset (read_dram,0,SIZE_DDATA/8); |
---|
| 657 | |
---|
| 658 | // if (must_read == true) |
---|
| 659 | // read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock); |
---|
| 660 | // if (must_write == true) |
---|
| 661 | // read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock); |
---|
| 662 | |
---|
| 663 | // /* |
---|
| 664 | // printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time()); |
---|
| 665 | // printf(" * addr : %.8x\n" ,(uint32_t)addr); |
---|
| 666 | // printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read()); |
---|
| 667 | // printf(" * r/w : %d/%d\n",must_read,must_write); |
---|
| 668 | // printf(" * val : %d\n" ,(uint32_t)read_dram[0]); |
---|
| 669 | // */ |
---|
| 670 | // break; |
---|
| 671 | // } |
---|
| 672 | // case TYPE_SIM2OS : |
---|
| 673 | // { |
---|
| 674 | // // Mapping : |
---|
| 675 | // // [0] number of service - Wonly - A write in this register lunch the execution of service |
---|
| 676 | // // [1] result - Ronly - Content the result of the service |
---|
| 677 | // // [2] error - Ronly - Content the code of errno |
---|
| 678 | // // [3+] argument - Wonly - it's all argument to execute the service |
---|
| 679 | |
---|
| 680 | // uint32_t num_reg = (addr - entity.segment->getBase())>>2; |
---|
| 681 | |
---|
| 682 | // switch (num_reg) |
---|
| 683 | // { |
---|
| 684 | // case 0 : // ---> number of service |
---|
| 685 | // { |
---|
| 686 | // if (must_write == false) |
---|
| 687 | // { |
---|
| 688 | // cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl; |
---|
| 689 | // bus_error = true; |
---|
| 690 | // } |
---|
| 691 | // else |
---|
| 692 | // { |
---|
| 693 | // printf("<sim2os> service : %.8x\n",(uint32_t)wdata); |
---|
| 694 | // component_sim2os->execute(int2service((uint32_t)wdata)); |
---|
| 695 | // } |
---|
| 696 | // break; |
---|
| 697 | // } |
---|
| 698 | // case 1 : // ---> result |
---|
| 699 | // { |
---|
| 700 | // if (must_read == false) |
---|
| 701 | // { |
---|
| 702 | // cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl; |
---|
| 703 | // bus_error = true; |
---|
| 704 | // } |
---|
| 705 | // else |
---|
| 706 | // { |
---|
| 707 | // // Decomposition en groupe octect |
---|
| 708 | // uint32_t result = (uint32_t) component_sim2os->result; |
---|
| 709 | // printf("<sim2os> result : %.8x (%d)\n",result,result); |
---|
| 710 | |
---|
| 711 | // read_dram = itoa(result,read_dram,SIZE_DDATA/8); |
---|
| 712 | // } |
---|
| 713 | // break; |
---|
| 714 | // } |
---|
| 715 | // case 2 : // ---> error |
---|
| 716 | // { |
---|
| 717 | // if (must_read == false) |
---|
| 718 | // { |
---|
| 719 | // cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl; |
---|
| 720 | // bus_error = true; |
---|
| 721 | // } |
---|
| 722 | // else |
---|
| 723 | // { |
---|
| 724 | // // Decomposition en groupe octect |
---|
| 725 | // uint32_t error = (uint32_t) component_sim2os->error; |
---|
| 726 | // printf("<sim2os> error : %.8x\n",error); |
---|
| 727 | // read_dram = itoa(error ,read_dram,SIZE_DDATA/8); |
---|
| 728 | // } |
---|
| 729 | // break; |
---|
| 730 | // } |
---|
| 731 | // default : // ---> argument |
---|
| 732 | // { |
---|
| 733 | // if (must_write == false) |
---|
| 734 | // { |
---|
| 735 | // cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl; |
---|
| 736 | // bus_error = true; |
---|
| 737 | // } |
---|
| 738 | // else |
---|
| 739 | // { |
---|
| 740 | // uint32_t data = (uint32_t)wdata; |
---|
| 741 | // printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data); |
---|
| 742 | // component_sim2os->parameter(num_reg-2,(void *)data); |
---|
| 743 | // } |
---|
| 744 | // break; |
---|
| 745 | // } |
---|
| 746 | // }//end switch num_reg |
---|
| 747 | |
---|
| 748 | // break; |
---|
| 749 | // } |
---|
| 750 | // default : |
---|
| 751 | // { |
---|
| 752 | // // Have a bus error |
---|
| 753 | // bus_error = true; |
---|
| 754 | // break; |
---|
| 755 | // } |
---|
| 756 | // }// switch |
---|
| 757 | // uncached |= entity.segment->getUncached(); |
---|
| 758 | // } |
---|
| 759 | // else |
---|
| 760 | // uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist |
---|
| 761 | |
---|
| 762 | |
---|
| 763 | // if ((must_write == true) && (bus_error == false)) |
---|
| 764 | // { |
---|
| 765 | // // Permutation if problem of endianness |
---|
| 766 | // if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false) |
---|
| 767 | // write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes); |
---|
| 768 | |
---|
| 769 | // bus_error |= !component_data->write(addr , |
---|
| 770 | // nb_bytes, // take the good access |
---|
| 771 | // write_dram ); |
---|
| 772 | // } |
---|
| 773 | |
---|
| 774 | |
---|
| 775 | // // Acces at the cache !!! |
---|
| 776 | // Cache_Access cache_type = dreq_type2cache_type (type, uncached); |
---|
| 777 | |
---|
| 778 | // uint32_t latence = component_cache->latence(DATA_CACHE , |
---|
| 779 | // i , |
---|
| 780 | // j , |
---|
| 781 | // (uint32_t)DCACHE [i][j].REQ_ADDR .read() , |
---|
| 782 | // (uint32_t)DCACHE [i][j].REQ_TRDID.read() , |
---|
| 783 | // cache_type.type , |
---|
| 784 | // cache_type.direction ); |
---|
| 785 | |
---|
| 786 | // // If is a respons -> compute the latence and push in the write_buffer |
---|
| 787 | // if ( must_ack == true) |
---|
| 788 | // { |
---|
| 789 | // if (bus_error == true) |
---|
| 790 | // cout << "Dcache : have a bus error" << endl; |
---|
| 791 | // component_buffer_drsp [i]->push(latence, |
---|
| 792 | // Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() , |
---|
| 793 | // (uint32_t)DCACHE [i][j].REQ_PKTID.read() , |
---|
| 794 | // 1 , |
---|
| 795 | // SIZE_DDATA/8 , |
---|
| 796 | // &read_dram , |
---|
| 797 | // (bus_error==true)?ERR_BUS:ERR_NO ) |
---|
| 798 | // ); |
---|
| 799 | // } |
---|
| 800 | // }// dnb_port |
---|
| 801 | // }//i |
---|
| 802 | |
---|
| 803 | |
---|
| 804 | }; |
---|