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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 83

Last change on this file since 83 was 81, checked in by rosiere, 17 years ago
Finish Environment (and test) Continue predictor_unit Add external tools svn keyword "Id" set
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File size: 29.4 KB

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1	#include "../include/Environment.h"
2
3	namespace environment {
4
5	void Environment::transition (void)
6	{
7	if (NRESET->read() == 0)
8	{
9	reset ();
10	}
11	else
12	{
13	//=============================================================================
14	//===== [ ICACHE - RESPONS ]===================================================
15	//=============================================================================
16	for (uint32_t i = 0; i < param->nb_entity; i++)
17	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
18	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
19	{
20	delete component_buffer_irsp [i]->read(j)._data;
21	component_buffer_irsp [i]->pop(j);
22	}
23	//=============================================================================
24	//===== [ DCACHE - RESPONS ]===================================================
25	//=============================================================================
26	for (uint32_t i = 0; i < param->nb_entity; i++)
27	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
28	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
29	{
30	delete component_buffer_drsp [i]->read(j)._data;
31	component_buffer_drsp [i]->pop(j);
32	}
33
34	//=============================================================================
35	//===== [ ICACHE - RESPONS ]===================================================
36	//=============================================================================
37	for (uint32_t i=0; i<param->nb_entity; i++)
38	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
39	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
40	{
41	_cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);
42
43	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
44	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
45	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read();
46	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
47	uint32_t size = param->iaccess_size_address [i]/8;
48
49	_cout(ENVIRONMENT," * information\n");
50	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
51	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
52	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
53	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
54	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
55
56	// search the entity
57	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
58
59	bool uncached ;
60	bool bus_error;
61	bool must_read = (type == ICACHE_TYPE_LOAD);
62	bool must_ack = (type == ICACHE_TYPE_LOAD);
63	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
64
65	// Test the type of the address : if != MEMORY -> error
66	if ((entity.present == true) and
67	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
68	{
69	_cout(ENVIRONMENT, " * OK !\n");
70	bus_error = false;
71	uncached = entity.segment->getUncached();
72
73	if (must_read == true) // Test if must read the ram
74	{
75	_cout(ENVIRONMENT, " * must read\n");
76	// Read all instruction
77	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
78	{
79	uint32_t addr = address+k*(size);
80	_cout(ENVIRONMENT, " * addr : %.8x\n",addr);
81
82	bus_error \|= !component_data->read(addr,size,read_iram[k]);
83
84	// Swap if endienness is different
85	if (endianness::isSameEndianness(context) == false)
86	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
87	}
88	}
89	}
90	else
91	{
92	_cout(ENVIRONMENT, " * KO !\n");
93	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
94	if (entity.present)
95	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
96
97	// entity is not present, or is present but is not a memory : have a bus error
98	bus_error = true;
99	uncached = true;
100	}
101
102	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
103	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
104	i,
105	j,
106	address,
107	context,
108	cache_type.type,
109	cache_type.direction);
110
111	_cout(ENVIRONMENT, " * latence : %d\n",latence);
112
113	// If is a respons -> compute the latence and push in the write_buffer
114	if (must_ack or (must_ack_on_error and bus_error))
115	{
116	_cout(ENVIRONMENT, " * must ack\n");
117
118	if (bus_error == true)
119	{
120	std::cout << "Icache : have a bus error" << std::endl
121	<< " * entity : " << i << std::endl
122	<< " * port : " << j << std::endl
123	<< std::hex
124	<< " * req_addr : " << address << std::endl
125	<< std::dec
126	<< " * req_trdid : " << context << std::endl
127	<< " * req_pktid : " << packet << std::endl;
128
129	// Write in instruction [0] the bad address (only 32bit ....)
130	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
131	}
132
133	// Simplification : the size of a line is a multiple of size_iword (no test)
134	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
135
136	irsp_t * rsp = new irsp_t(context,
137	packet,
138	param->iaccess_nb_instruction[i],
139	size,
140	read_iram,
141	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
142	component_buffer_irsp [i]->push(latence,rsp);
143	}
144
145	_cout(ENVIRONMENT, " * End request\n");
146	}
147
148	//=============================================================================
149	//===== [ DCACHE - REQUEST ]===================================================
150	//=============================================================================
151	for (uint32_t i=0; i<param->nb_entity; i++)
152	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
153	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
154	{
155	_cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);
156
157	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
158	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
159	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
160	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
161	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
162	uint32_t size = param->daccess_size_data [i]/8;
163
164	// _cout(ENVIRONMENT," * information\n");
165	// _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
166	// _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
167	// _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
168	// _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
169	// _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
170
171	// search the entity
172	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
173
174	std::cout << entity << std::endl;
175
176	bool uncached = false;
177	bool bus_error = false;
178
179	uint32_t nb_bytes = size;
180	bool must_read ;
181	bool must_write;
182	bool must_ack ;
183	bool must_ack_on_error;
184
185	switch (type)
186	{
187	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
188	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
189	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
190	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
191	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
192	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
193	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
194	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
195	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
196	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
197	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
198	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
199	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
200	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
201	}
202
203	// Test the type of the address
204	if (entity.present == true)
205	{
206	switch (entity.segment->getType())
207	{
208	//**************************************************************
209	//***[ TTY ]************************************************
210	//**************************************************************
211	case data::TYPE_TARGET_TTY :
212	{
213	// Can't read a tty, must write
214	if (must_write == false)
215	{
216	bus_error = true;
217	break;
218	}
219
220	uint32_t num_tty = (address - entity.segment->getBase())>>4;
221	uint32_t num_print = ((address>>2) & 0x3);
222	_cout(ENVIRONMENT," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
223
224	switch (num_print)
225	{
226	case 0 : // Write TTY
227	{
228	uint32_t num_component_tty = entity.segment->getIndex();
229	char char_write = static_cast<char>(wdata&0xff);
230	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
231	break;
232	}
233	case 1 : // STOP
234	{
235	printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
236	,static_cast<uint32_t>(sc_simulation_time())
237	,static_cast<uint32_t>(address )
238	,static_cast<uint32_t>((wdata>>24)&0xff)
239	,static_cast<uint32_t>((wdata>>16)&0xff)
240	,static_cast<uint32_t>((wdata>> 8)&0xff)
241	,static_cast<uint32_t>((wdata>> 0)&0xff)
242	);
243
244	// if (context_stop [context] == false)
245	// {
246	// context_stop [context] = true;
247	// nb_context_stop ++;
248
249	// if (nb_context_stop >= nb_context)
250	// sc_stop();
251	// }
252
253	break;
254	}
255	case 2 : // PRINT
256	{
257	printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
258	,static_cast<uint32_t>(sc_simulation_time())
259	,static_cast<uint32_t>(address )
260	,static_cast<uint32_t>((wdata>>24)&0xff)
261	,static_cast<uint32_t>((wdata>>16)&0xff)
262	,static_cast<uint32_t>((wdata>> 8)&0xff)
263	,static_cast<uint32_t>((wdata>> 0)&0xff)
264	);
265
266	break;
267	}
268	default :
269	{
270	printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
271	bus_error = true;
272	}
273	}
274	break;
275	}
276
277	//**************************************************************
278	//***[ MEMORY ]*********************************************
279	//**************************************************************
280	case data::TYPE_TARGET_MEMORY :
281	{
282	_cout(ENVIRONMENT,"MEMORY\n");
283	_cout(ENVIRONMENT,"access : %x\n",address);
284
285	if (must_read == true)
286	{
287	// Read
288	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
289	bus_error \|= !component_data->read(address,size,read_dram[0]); // always read a complete word
290
291	_cout(ENVIRONMENT," * Rdata : ");
292	for (uint32_t i=0; i<size; i++)
293	_cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
294	_cout(ENVIRONMENT,".\n");
295
296	// Multiple copy
297	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
298	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
299
300	// Permutation if problem of endianness
301	if (endianness::isSameEndianness(context) == false)
302	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
303	}
304
305	if (must_write == true)
306	{
307	// Write
308	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
309	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
310	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
311
312	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
313	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
314	}
315
316	break;
317	}
318	//**************************************************************
319	//***[ RAMLOCK ]********************************************
320	//**************************************************************
321	case data::TYPE_TARGET_RAMLOCK :
322	{
323	// Access is on a byte, else error
324	if (nb_bytes != 1)
325	{
326	bus_error = true;
327	break;
328	}
329
330	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
331	uint32_t num_component_ramlock = entity.segment->getIndex();
332
333	// No test : because out of range
334
335	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
336
337	// if (bus_error == true)
338	// break;
339
340	memset (read_dram[0],0,size);
341
342	if (must_read == true)
343	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
344	if (must_write == true)
345	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
346
347	break;
348	}
349
350	//**************************************************************
351	//***[ SIM2OS ]*********************************************
352	//**************************************************************
353	case data::TYPE_TARGET_SIM2OS :
354	{
355	// Mapping :
356	// [0] number of service - Wonly - A write in this register lunch the execution of service
357	// [1] result - Ronly - Content the result of the service
358	// [2] error - Ronly - Content the code of errno
359	// [3+] argument - Wonly - it's all argument to execute the service
360
361	uint32_t num_reg = (address - entity.segment->getBase())>>2;
362
363	switch (num_reg)
364	{
365	case 0 : // ---> number of service
366	{
367	if (must_write == false)
368	{
369	std::cerr << "<Environment::transition> SIM2OS[0] is not accessible in Read" << std::endl;
370	bus_error = true;
371	}
372	else
373	{
374	_cout(ENVIRONMENT,"<sim2os> service : %x\n",wdata);
375	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
376	}
377	break;
378	}
379	case 1 : // ---> result
380	{
381	if (must_read == false)
382	{
383	std::cerr << "<Environment::transition> SIM2OS[1] is not accessible in Write" << std::endl;
384	bus_error = true;
385	}
386	else
387	{
388	// Decomposition en groupe octect
389	Tdcache_data_t result = (Tdcache_data_t)(component_sim2os->result);
390	_cout(ENVIRONMENT,"<sim2os> result : %x\n",result);
391
392	itoa<Tdcache_data_t>(result,read_dram[0],size);
393	}
394	break;
395	}
396	case 2 : // ---> error
397	{
398	if (must_read == false)
399	{
400	std::cerr << "<Environment::transition> SIM2OS[2] is not accessible in Write" << std::endl;
401	bus_error = true;
402	}
403	else
404	{
405	// Decomposition en groupe octect
406	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
407	_cout(ENVIRONMENT,"<sim2os> error : %x\n",error);
408
409	itoa<Tdcache_data_t>(error,read_dram[0],size);
410	}
411
412	break;
413	}
414	default : //---> argument
415	{
416	if (must_write == false)
417	{
418	std::cerr << "<Environment::transition> SIM2OS[" << num_reg << "] is not accessible in Read" << std::endl;
419	bus_error = true;
420	}
421	else
422	{
423	_cout(ENVIRONMENT,"<sim2os> argument[%d] : %x\n",num_reg-1,wdata);
424	component_sim2os->parameter(num_reg-2,(void *)wdata);
425	}
426	break;
427	}
428	}
429
430	break;
431	}
432
433	default :
434	{
435	std::cerr << "<Environment::transition> Dcache_req : Unknow type" << std::endl;
436	exit(1);
437	break;
438	}
439	}
440	uncached \|= entity.segment->getUncached();
441	}
442	else
443	{
444	// entity is not present, or is present but is not a memory : have a bus error
445	bus_error = true;
446	uncached = true;
447	}
448
449	if ((must_write == true) and (bus_error == false))
450	{
451	// Permutation if problem of endianness
452	if (endianness::isSameEndianness(context) == false)
453	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
454
455	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
456	}
457
458	// Acces at the cache !!!
459	// Cache WRITE ALLOCATE (becauce compute latence always; )
460	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
461	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
462	i,
463	j,
464	address,
465	context,
466	cache_type.type,
467	cache_type.direction);
468
469	// If is a respons -> compute the latence and push in the write_buffer
470	if (must_ack or (must_ack_on_error and bus_error))
471	{
472	if (bus_error == true)
473	{
474	std::cout << "Dcache : have a bus error" << std::endl
475	<< " * entity : " << i << std::endl
476	<< " * port : " << j << std::endl
477	<< std::hex
478	<< " * req_addr : 0x" << address << std::endl
479	<< std::dec
480	<< " * req_trdid : " << context << std::endl
481	<< " * req_pktid : " << packet << std::endl;
482
483	// Write in data [0] the bad address (32bit or 64bits )
484	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
485	}
486
487	// Simplification : the size of a line is a multiple of size_iword (no test)
488	drsp_t * rsp = new drsp_t(context,
489	packet,
490	1,
491	size,
492	read_dram,
493	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
494	component_buffer_drsp [i]->push(latence,rsp);
495	}
496
497	}
498	//=============================================================================
499	//===== [ OTHERS ]=============================================================
500	//=============================================================================
501
502	// Transition for each component
503	component_cache -> transition();
504	for (uint32_t i=0; i<param->nb_entity; i++)
505	{
506	component_buffer_irsp [i]->transition();
507	component_buffer_drsp [i]->transition();
508	}
509	component_sim2os->transition();
510	}
511	}
512
513	// // ******************
514	// // *** DCACHE ***
515	// // ******************
516
517	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
518	// {
519	// // Test if transaction
520	// // cout << "[" << i << "]"
521	// // << "[" << j << "] "
522	// // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " "
523	// // << "dreq_ack : " << dreq_ack [i][j] << endl;
524
525	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
526	// continue;
527
528	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
529
530	// bool uncached = DCACHE [i][j].REQ_UNC.read();
531	// bool bus_error = false;
532
533	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
534	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
535	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
536	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
537	// // A lot of flag
538	// bool must_read = ((type == DTYPE_READ ));
539	// bool must_write = ((type == DTYPE_WRITE ) \|\|
540	// (type == DTYPE_WRITE_ACK ) );
541	// bool must_ack = ((type == DTYPE_READ ) \|\|
542	// (type == DTYPE_WRITE_ACK ) );
543
544	// // Test the type of the address
545	// if (entity.present == true)
546	// {
547	// switch (entity.segment->getType())
548	// {
549	// // ACCESS AT A RAM
550	// case data::TYPE_TARGET_MEMORY :
551	// {
552	// if (must_read == true)
553	// {
554	// // Read
555	// bus_error \|= !component_data->read(addr ,
556	// SIZE_DDATA/8 , // always read a complete word
557	// read_dram );
558
559	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
560	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
561
562	// // Permutation if problem of endianness
563	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
564	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
565	// }
566
567	// if (must_write == true)
568	// {
569	// // Write
570	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
571	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
572	// }
573	// break;
574	// }
575	// //ACCESS AT THE TTY
576	// case TYPE_TTY :
577	// {
578	// if (must_write == false)
579	// {
580	// bus_error = true;
581	// break;
582	// }
583	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
584	// uint32_t num_print = ((addr>>2) & 0x3);
585
586	// switch (num_print)
587	// {
588	// case 0 : // Write TTY
589	// {
590	// uint32_t num_component_tty = entity.segment->getIndex();
591	// char char_write = (char)wdata.range( 7, 0);
592	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
593	// break;
594	// }
595	// case 1 : // STOP
596	// {
597	// printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
598	// ,(unsigned int)sc_simulation_time()
599	// ,(unsigned int)addr
600	// ,(unsigned int)wdata.range(31,24)
601	// ,(unsigned int)wdata.range(23,16)
602	// ,(unsigned int)wdata.range(15, 8)
603	// ,(unsigned int)wdata.range( 7, 0)
604	// );
605
606	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
607
608	// if (context_stop [trdid] == false)
609	// {
610	// context_stop [trdid] = true;
611	// nb_context_stop ++;
612
613	// if (nb_context_stop >= nb_context)
614	// sc_stop();
615	// }
616
617	// break;
618	// }
619	// case 2 : // PRINT
620	// {
621	// printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
622	// ,(unsigned int)sc_simulation_time()
623	// ,(unsigned int)addr
624	// ,(unsigned int)wdata.range(31,24)
625	// ,(unsigned int)wdata.range(23,16)
626	// ,(unsigned int)wdata.range(15, 8)
627	// ,(unsigned int)wdata.range( 7, 0)
628	// );
629
630	// break;
631	// }
632	// default :
633	// {
634	// printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
635	// exit(1);
636	// }
637	// }
638
639	// break;
640	// }
641	// case TYPE_RAMLOCK :
642	// {
643	// // Access is on a byte, else error
644	// if (nb_bytes != 1)
645	// {
646	// bus_error = true;
647	// break;
648	// }
649	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
650	// uint32_t num_component_ramlock = entity.segment->getIndex();
651	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
652
653	// if (bus_error == true)
654	// break;
655
656	// memset (read_dram,0,SIZE_DDATA/8);
657
658	// if (must_read == true)
659	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
660	// if (must_write == true)
661	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
662
663	// /*
664	// printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
665	// printf(" * addr : %.8x\n" ,(uint32_t)addr);
666	// printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
667	// printf(" * r/w : %d/%d\n",must_read,must_write);
668	// printf(" * val : %d\n" ,(uint32_t)read_dram[0]);
669	// */
670	// break;
671	// }
672	// case TYPE_SIM2OS :
673	// {
674	// // Mapping :
675	// // [0] number of service - Wonly - A write in this register lunch the execution of service
676	// // [1] result - Ronly - Content the result of the service
677	// // [2] error - Ronly - Content the code of errno
678	// // [3+] argument - Wonly - it's all argument to execute the service
679
680	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
681
682	// switch (num_reg)
683	// {
684	// case 0 : // ---> number of service
685	// {
686	// if (must_write == false)
687	// {
688	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
689	// bus_error = true;
690	// }
691	// else
692	// {
693	// printf("<sim2os> service : %.8x\n",(uint32_t)wdata);
694	// component_sim2os->execute(int2service((uint32_t)wdata));
695	// }
696	// break;
697	// }
698	// case 1 : // ---> result
699	// {
700	// if (must_read == false)
701	// {
702	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
703	// bus_error = true;
704	// }
705	// else
706	// {
707	// // Decomposition en groupe octect
708	// uint32_t result = (uint32_t) component_sim2os->result;
709	// printf("<sim2os> result : %.8x (%d)\n",result,result);
710
711	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
712	// }
713	// break;
714	// }
715	// case 2 : // ---> error
716	// {
717	// if (must_read == false)
718	// {
719	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
720	// bus_error = true;
721	// }
722	// else
723	// {
724	// // Decomposition en groupe octect
725	// uint32_t error = (uint32_t) component_sim2os->error;
726	// printf("<sim2os> error : %.8x\n",error);
727	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
728	// }
729	// break;
730	// }
731	// default : // ---> argument
732	// {
733	// if (must_write == false)
734	// {
735	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
736	// bus_error = true;
737	// }
738	// else
739	// {
740	// uint32_t data = (uint32_t)wdata;
741	// printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
742	// component_sim2os->parameter(num_reg-2,(void *)data);
743	// }
744	// break;
745	// }
746	// }//end switch num_reg
747
748	// break;
749	// }
750	// default :
751	// {
752	// // Have a bus error
753	// bus_error = true;
754	// break;
755	// }
756	// }// switch
757	// uncached \|= entity.segment->getUncached();
758	// }
759	// else
760	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
761
762
763	// if ((must_write == true) && (bus_error == false))
764	// {
765	// // Permutation if problem of endianness
766	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
767	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
768
769	// bus_error \|= !component_data->write(addr ,
770	// nb_bytes, // take the good access
771	// write_dram );
772	// }
773
774
775	// // Acces at the cache !!!
776	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
777
778	// uint32_t latence = component_cache->latence(DATA_CACHE ,
779	// i ,
780	// j ,
781	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
782	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
783	// cache_type.type ,
784	// cache_type.direction );
785
786	// // If is a respons -> compute the latence and push in the write_buffer
787	// if ( must_ack == true)
788	// {
789	// if (bus_error == true)
790	// cout << "Dcache : have a bus error" << endl;
791	// component_buffer_drsp [i]->push(latence,
792	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
793	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
794	// 1 ,
795	// SIZE_DDATA/8 ,
796	// &read_dram ,
797	// (bus_error==true)?ERR_BUS:ERR_NO )
798	// );
799	// }
800	// }// dnb_port
801	// }//i
802
803
804	};

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