Context Navigation

source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 96

Last change on this file since 96 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 29.8 KB

Line
1	#include "../include/Environment.h"
2
3	using namespace morpheo;
4
5	namespace environment {
6
7	void Environment::transition (void)
8	{
9	if (NRESET->read() == 0)
10	{
11	reset ();
12	}
13	else
14	{
15	//=============================================================================
16	//===== [ ICACHE - RESPONS ]===================================================
17	//=============================================================================
18	for (uint32_t i = 0; i < param->nb_entity; i++)
19	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
20	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
21	{
22	delete component_buffer_irsp [i]->read(j)._data;
23	component_buffer_irsp [i]->pop(j);
24	}
25	//=============================================================================
26	//===== [ DCACHE - RESPONS ]===================================================
27	//=============================================================================
28	for (uint32_t i = 0; i < param->nb_entity; i++)
29	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
30	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
31	{
32	delete component_buffer_drsp [i]->read(j)._data;
33	component_buffer_drsp [i]->pop(j);
34	}
35
36	//=============================================================================
37	//===== [ ICACHE - RESPONS ]===================================================
38	//=============================================================================
39	for (uint32_t i=0; i<param->nb_entity; i++)
40	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
41	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
42	{
43	_cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);
44
45	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
46	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
47	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
48	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
49	uint32_t size = (param->iaccess_size_address [i]+2)/8;
50
51	_cout(ENVIRONMENT," * information\n");
52	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
53	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
54	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
55	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
56	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
57
58	// search the entity
59	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
60
61	bool uncached ;
62	bool bus_error;
63	bool must_read = (type == ICACHE_TYPE_LOAD);
64	bool must_ack = (type == ICACHE_TYPE_LOAD);
65	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
66
67	// Test the type of the address : if != MEMORY -> error
68	if ((entity.present == true) and
69	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
70	{
71	_cout(ENVIRONMENT," * OK !\n");
72	bus_error = false;
73	uncached = entity.segment->getUncached();
74
75	if (must_read == true) // Test if must read the ram
76	{
77	_cout(ENVIRONMENT," * must read\n");
78	// Read all instruction
79	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
80	{
81	uint32_t addr = address+k*(size);
82	_cout(ENVIRONMENT," * addr : %.8x\n",addr);
83
84	bus_error \|= !component_data->read(addr,size,read_iram[k]);
85
86	// Swap if endienness is different
87	if (endianness::isSameEndianness(context) == false)
88	{
89	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
90	}
91
92	_cout(ENVIRONMENT," * inst :");
93	for (int32_t cpt=(param->iaccess_size_instruction[context]/8)-1; cpt>=0; --cpt)
94	_cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
95	_cout(ENVIRONMENT, "\n");
96	}
97	}
98	}
99	else
100	{
101	_cout(ENVIRONMENT, " * KO !\n");
102	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
103	if (entity.present)
104	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
105
106	// entity is not present, or is present but is not a memory : have a bus error
107	bus_error = true;
108	uncached = true;
109	}
110
111	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
112	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
113	i,
114	j,
115	address,
116	context,
117	cache_type.type,
118	cache_type.direction);
119
120	_cout(ENVIRONMENT, " * latence : %d\n",latence);
121
122	// If is a respons -> compute the latence and push in the write_buffer
123	if (must_ack or (must_ack_on_error and bus_error))
124	{
125	_cout(ENVIRONMENT, " * must ack\n");
126
127	if (bus_error == true)
128	{
129	std::cout << "Icache : have a bus error" << std::endl
130	<< " * entity : " << i << std::endl
131	<< " * port : " << j << std::endl
132	<< std::hex
133	<< " * req_addr : " << address << std::endl
134	<< std::dec
135	<< " * req_trdid : " << context << std::endl
136	<< " * req_pktid : " << packet << std::endl;
137
138	// Write in instruction [0] the bad address (only 32bit ....)
139	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
140	}
141
142	// Simplification : the size of a line is a multiple of size_iword (no test)
143	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
144
145	irsp_t * rsp = new irsp_t(context,
146	packet,
147	param->iaccess_nb_instruction[i],
148	size,
149	read_iram,
150	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
151	component_buffer_irsp [i]->push(latence,rsp);
152	}
153
154	_cout(ENVIRONMENT, " * End request\n");
155	}
156
157	//=============================================================================
158	//===== [ DCACHE - REQUEST ]===================================================
159	//=============================================================================
160	for (uint32_t i=0; i<param->nb_entity; i++)
161	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
162	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
163	{
164	_cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);
165
166	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
167	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
168	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
169	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
170	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
171	uint32_t size = param->daccess_size_data [i]/8;
172
173	// _cout(ENVIRONMENT," * information\n");
174	// _cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
175	// _cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
176	// _cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
177	// _cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
178	// _cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
179
180	// search the entity
181	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
182
183	std::cout << entity << std::endl;
184
185	bool uncached = false;
186	bool bus_error = false;
187
188	uint32_t nb_bytes = size;
189	bool must_read ;
190	bool must_write;
191	bool must_ack ;
192	bool must_ack_on_error;
193
194	switch (type)
195	{
196	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
197	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
198	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
199	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
200	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
201	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
202	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
203	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
204	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
205	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
206	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
207	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
208	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
209	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
210	}
211
212	// Test the type of the address
213	if (entity.present == true)
214	{
215	switch (entity.segment->getType())
216	{
217	//**************************************************************
218	//***[ TTY ]************************************************
219	//**************************************************************
220	case data::TYPE_TARGET_TTY :
221	{
222	// Can't read a tty, must write
223	if (must_write == false)
224	{
225	bus_error = true;
226	break;
227	}
228
229	uint32_t num_tty = (address - entity.segment->getBase())>>4;
230	uint32_t num_print = ((address>>2) & 0x3);
231	_cout(ENVIRONMENT," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
232
233	switch (num_print)
234	{
235	case 0 : // Write TTY
236	{
237	uint32_t num_component_tty = entity.segment->getIndex();
238	char char_write = static_cast<char>(wdata&0xff);
239	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
240	break;
241	}
242	case 1 : // STOP
243	{
244	printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
245	,static_cast<uint32_t>(sc_simulation_time())
246	,static_cast<uint32_t>(address )
247	,static_cast<uint32_t>((wdata>>24)&0xff)
248	,static_cast<uint32_t>((wdata>>16)&0xff)
249	,static_cast<uint32_t>((wdata>> 8)&0xff)
250	,static_cast<uint32_t>((wdata>> 0)&0xff)
251	);
252
253	stop (context);
254
255	break;
256	}
257	case 2 : // PRINT
258	{
259	printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
260	,static_cast<uint32_t>(sc_simulation_time())
261	,static_cast<uint32_t>(address )
262	,static_cast<uint32_t>((wdata>>24)&0xff)
263	,static_cast<uint32_t>((wdata>>16)&0xff)
264	,static_cast<uint32_t>((wdata>> 8)&0xff)
265	,static_cast<uint32_t>((wdata>> 0)&0xff)
266	);
267
268	break;
269	}
270	default :
271	{
272	printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
273	bus_error = true;
274	}
275	}
276	break;
277	}
278
279	//**************************************************************
280	//***[ MEMORY ]*********************************************
281	//**************************************************************
282	case data::TYPE_TARGET_MEMORY :
283	{
284	_cout(ENVIRONMENT,"MEMORY\n");
285	_cout(ENVIRONMENT,"access : %x\n",address);
286
287	if (must_read == true)
288	{
289	// Read
290	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
291	bus_error \|= !component_data->read(address,size,read_dram[0]); // always read a complete word
292
293	_cout(ENVIRONMENT," * Rdata : ");
294	for (uint32_t i=0; i<size; i++)
295	_cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
296	_cout(ENVIRONMENT,".\n");
297
298	// Multiple copy
299	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
300	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
301
302	// Permutation if problem of endianness
303	if (endianness::isSameEndianness(context) == false)
304	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
305	}
306
307	if (must_write == true)
308	{
309	// Write
310	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
311	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
312	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
313
314	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
315	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
316	}
317
318	break;
319	}
320	//**************************************************************
321	//***[ RAMLOCK ]********************************************
322	//**************************************************************
323	case data::TYPE_TARGET_RAMLOCK :
324	{
325	// Access is on a byte, else error
326	if (nb_bytes != 1)
327	{
328	bus_error = true;
329	break;
330	}
331
332	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
333	uint32_t num_component_ramlock = entity.segment->getIndex();
334
335	// No test : because out of range
336
337	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
338
339	// if (bus_error == true)
340	// break;
341
342	memset (read_dram[0],0,size);
343
344	if (must_read == true)
345	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
346	if (must_write == true)
347	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
348
349	break;
350	}
351
352	//**************************************************************
353	//***[ SIM2OS ]*********************************************
354	//**************************************************************
355	case data::TYPE_TARGET_SIM2OS :
356	{
357	// Mapping :
358	// [0] number of service - Wonly - A write in this register lunch the execution of service
359	// [1] result - Ronly - Content the result of the service
360	// [2] error - Ronly - Content the code of errno
361	// [3+] argument - Wonly - it's all argument to execute the service
362
363	uint32_t num_reg = (address - entity.segment->getBase())>>2;
364
365	switch (num_reg)
366	{
367	case 0 : // ---> number of service
368	{
369	if (must_write == false)
370	{
371	std::cerr << "<Environment::transition> SIM2OS[0] is not accessible in Read" << std::endl;
372	bus_error = true;
373	}
374	else
375	{
376	_cout(ENVIRONMENT,"<sim2os> service : %x\n",wdata);
377	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
378	}
379	break;
380	}
381	case 1 : // ---> result
382	{
383	if (must_read == false)
384	{
385	std::cerr << "<Environment::transition> SIM2OS[1] is not accessible in Write" << std::endl;
386	bus_error = true;
387	}
388	else
389	{
390	// Decomposition en groupe octect
391	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
392	_cout(ENVIRONMENT,"<sim2os> result : %x\n",result);
393
394	itoa<Tdcache_data_t>(result,read_dram[0],size);
395	}
396	break;
397	}
398	case 2 : // ---> error
399	{
400	if (must_read == false)
401	{
402	std::cerr << "<Environment::transition> SIM2OS[2] is not accessible in Write" << std::endl;
403	bus_error = true;
404	}
405	else
406	{
407	// Decomposition en groupe octect
408	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
409	_cout(ENVIRONMENT,"<sim2os> error : %x\n",error);
410
411	itoa<Tdcache_data_t>(error,read_dram[0],size);
412	}
413
414	break;
415	}
416	default : //---> argument
417	{
418	if (must_write == false)
419	{
420	std::cerr << "<Environment::transition> SIM2OS[" << num_reg << "] is not accessible in Read" << std::endl;
421	bus_error = true;
422	}
423	else
424	{
425	_cout(ENVIRONMENT,"<sim2os> argument[%d] : %x\n",num_reg-1,wdata);
426	component_sim2os->parameter(num_reg-2,(void *)wdata);
427	}
428	break;
429	}
430	}
431
432	break;
433	}
434
435	default :
436	{
437	std::cerr << "<Environment::transition> Dcache_req : Unknow type" << std::endl;
438	exit(1);
439	break;
440	}
441	}
442	uncached \|= entity.segment->getUncached();
443	}
444	else
445	{
446	// entity is not present, or is present but is not a memory : have a bus error
447	bus_error = true;
448	uncached = true;
449	}
450
451	if ((must_write == true) and (bus_error == false))
452	{
453	// Permutation if problem of endianness
454	if (endianness::isSameEndianness(context) == false)
455	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
456
457	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
458	}
459
460	// Acces at the cache !!!
461	// Cache WRITE ALLOCATE (becauce compute latence always; )
462	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
463	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
464	i,
465	j,
466	address,
467	context,
468	cache_type.type,
469	cache_type.direction);
470
471	// If is a respons -> compute the latence and push in the write_buffer
472	if (must_ack or (must_ack_on_error and bus_error))
473	{
474	if (bus_error == true)
475	{
476	std::cout << "Dcache : have a bus error" << std::endl
477	<< " * entity : " << i << std::endl
478	<< " * port : " << j << std::endl
479	<< std::hex
480	<< " * req_addr : 0x" << address << std::endl
481	<< std::dec
482	<< " * req_trdid : " << context << std::endl
483	<< " * req_pktid : " << packet << std::endl;
484
485	// Write in data [0] the bad address (32bit or 64bits )
486	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
487	}
488
489	// Simplification : the size of a line is a multiple of size_iword (no test)
490	drsp_t * rsp = new drsp_t(context,
491	packet,
492	1,
493	size,
494	read_dram,
495	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
496	component_buffer_drsp [i]->push(latence,rsp);
497	}
498	}
499	//=============================================================================
500	//===== [ OTHERS ]=============================================================
501	//=============================================================================
502
503	// Transition for each component
504	component_cache -> transition();
505	for (uint32_t i=0; i<param->nb_entity; i++)
506	{
507	component_buffer_irsp [i]->transition();
508	component_buffer_drsp [i]->transition();
509	}
510	component_sim2os->transition();
511	}
512	}
513
514	// // ******************
515	// // *** DCACHE ***
516	// // ******************
517
518	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
519	// {
520	// // Test if transaction
521	// // cout << "[" << i << "]"
522	// // << "[" << j << "] "
523	// // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " "
524	// // << "dreq_ack : " << dreq_ack [i][j] << endl;
525
526	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
527	// continue;
528
529	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
530
531	// bool uncached = DCACHE [i][j].REQ_UNC.read();
532	// bool bus_error = false;
533
534	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
535	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
536	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
537	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
538	// // A lot of flag
539	// bool must_read = ((type == DTYPE_READ ));
540	// bool must_write = ((type == DTYPE_WRITE ) \|\|
541	// (type == DTYPE_WRITE_ACK ) );
542	// bool must_ack = ((type == DTYPE_READ ) \|\|
543	// (type == DTYPE_WRITE_ACK ) );
544
545	// // Test the type of the address
546	// if (entity.present == true)
547	// {
548	// switch (entity.segment->getType())
549	// {
550	// // ACCESS AT A RAM
551	// case data::TYPE_TARGET_MEMORY :
552	// {
553	// if (must_read == true)
554	// {
555	// // Read
556	// bus_error \|= !component_data->read(addr ,
557	// SIZE_DDATA/8 , // always read a complete word
558	// read_dram );
559
560	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
561	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
562
563	// // Permutation if problem of endianness
564	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
565	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
566	// }
567
568	// if (must_write == true)
569	// {
570	// // Write
571	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
572	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
573	// }
574	// break;
575	// }
576	// //ACCESS AT THE TTY
577	// case TYPE_TTY :
578	// {
579	// if (must_write == false)
580	// {
581	// bus_error = true;
582	// break;
583	// }
584	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
585	// uint32_t num_print = ((addr>>2) & 0x3);
586
587	// switch (num_print)
588	// {
589	// case 0 : // Write TTY
590	// {
591	// uint32_t num_component_tty = entity.segment->getIndex();
592	// char char_write = (char)wdata.range( 7, 0);
593	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
594	// break;
595	// }
596	// case 1 : // STOP
597	// {
598	// printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
599	// ,(unsigned int)sc_simulation_time()
600	// ,(unsigned int)addr
601	// ,(unsigned int)wdata.range(31,24)
602	// ,(unsigned int)wdata.range(23,16)
603	// ,(unsigned int)wdata.range(15, 8)
604	// ,(unsigned int)wdata.range( 7, 0)
605	// );
606
607	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
608
609	// if (context_stop [trdid] == false)
610	// {
611	// context_stop [trdid] = true;
612	// nb_context_stop ++;
613
614	// if (nb_context_stop >= nb_context)
615	// sc_stop();
616	// }
617
618	// break;
619	// }
620	// case 2 : // PRINT
621	// {
622	// printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
623	// ,(unsigned int)sc_simulation_time()
624	// ,(unsigned int)addr
625	// ,(unsigned int)wdata.range(31,24)
626	// ,(unsigned int)wdata.range(23,16)
627	// ,(unsigned int)wdata.range(15, 8)
628	// ,(unsigned int)wdata.range( 7, 0)
629	// );
630
631	// break;
632	// }
633	// default :
634	// {
635	// printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
636	// exit(1);
637	// }
638	// }
639
640	// break;
641	// }
642	// case TYPE_RAMLOCK :
643	// {
644	// // Access is on a byte, else error
645	// if (nb_bytes != 1)
646	// {
647	// bus_error = true;
648	// break;
649	// }
650	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
651	// uint32_t num_component_ramlock = entity.segment->getIndex();
652	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
653
654	// if (bus_error == true)
655	// break;
656
657	// memset (read_dram,0,SIZE_DDATA/8);
658
659	// if (must_read == true)
660	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
661	// if (must_write == true)
662	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
663
664	// /*
665	// printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
666	// printf(" * addr : %.8x\n" ,(uint32_t)addr);
667	// printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
668	// printf(" * r/w : %d/%d\n",must_read,must_write);
669	// printf(" * val : %d\n" ,(uint32_t)read_dram[0]);
670	// */
671	// break;
672	// }
673	// case TYPE_SIM2OS :
674	// {
675	// // Mapping :
676	// // [0] number of service - Wonly - A write in this register lunch the execution of service
677	// // [1] result - Ronly - Content the result of the service
678	// // [2] error - Ronly - Content the code of errno
679	// // [3+] argument - Wonly - it's all argument to execute the service
680
681	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
682
683	// switch (num_reg)
684	// {
685	// case 0 : // ---> number of service
686	// {
687	// if (must_write == false)
688	// {
689	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
690	// bus_error = true;
691	// }
692	// else
693	// {
694	// printf("<sim2os> service : %.8x\n",(uint32_t)wdata);
695	// component_sim2os->execute(int2service((uint32_t)wdata));
696	// }
697	// break;
698	// }
699	// case 1 : // ---> result
700	// {
701	// if (must_read == false)
702	// {
703	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
704	// bus_error = true;
705	// }
706	// else
707	// {
708	// // Decomposition en groupe octect
709	// uint32_t result = (uint32_t) component_sim2os->result;
710	// printf("<sim2os> result : %.8x (%d)\n",result,result);
711
712	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
713	// }
714	// break;
715	// }
716	// case 2 : // ---> error
717	// {
718	// if (must_read == false)
719	// {
720	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
721	// bus_error = true;
722	// }
723	// else
724	// {
725	// // Decomposition en groupe octect
726	// uint32_t error = (uint32_t) component_sim2os->error;
727	// printf("<sim2os> error : %.8x\n",error);
728	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
729	// }
730	// break;
731	// }
732	// default : // ---> argument
733	// {
734	// if (must_write == false)
735	// {
736	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
737	// bus_error = true;
738	// }
739	// else
740	// {
741	// uint32_t data = (uint32_t)wdata;
742	// printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
743	// component_sim2os->parameter(num_reg-2,(void *)data);
744	// }
745	// break;
746	// }
747	// }//end switch num_reg
748
749	// break;
750	// }
751	// default :
752	// {
753	// // Have a bus error
754	// bus_error = true;
755	// break;
756	// }
757	// }// switch
758	// uncached \|= entity.segment->getUncached();
759	// }
760	// else
761	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
762
763
764	// if ((must_write == true) && (bus_error == false))
765	// {
766	// // Permutation if problem of endianness
767	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
768	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
769
770	// bus_error \|= !component_data->write(addr ,
771	// nb_bytes, // take the good access
772	// write_dram );
773	// }
774
775
776	// // Acces at the cache !!!
777	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
778
779	// uint32_t latence = component_cache->latence(DATA_CACHE ,
780	// i ,
781	// j ,
782	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
783	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
784	// cache_type.type ,
785	// cache_type.direction );
786
787	// // If is a respons -> compute the latence and push in the write_buffer
788	// if ( must_ack == true)
789	// {
790	// if (bus_error == true)
791	// cout << "Dcache : have a bus error" << endl;
792	// component_buffer_drsp [i]->push(latence,
793	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
794	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
795	// 1 ,
796	// SIZE_DDATA/8 ,
797	// &read_dram ,
798	// (bus_error==true)?ERR_BUS:ERR_NO )
799	// );
800	// }
801	// }// dnb_port
802	// }//i
803
804
805	};

Note: See TracBrowser for help on using the repository browser.

Download in other formats: