[78] | 1 | #include <iostream> |
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| 2 | #include "../include/Cache.h" |
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| 3 | |
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| 4 | using namespace std; |
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| 5 | using namespace environnement; |
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| 6 | using namespace environnement::cache; |
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| 7 | |
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| 8 | #define TEST(x,y) \ |
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| 9 | { \ |
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| 10 | cout << "Line " << __LINE__ << " : "; \ |
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| 11 | if (x==y) \ |
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| 12 | { \ |
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| 13 | cout << "Test OK" << endl; \ |
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| 14 | } \ |
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| 15 | else \ |
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| 16 | { \ |
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| 17 | cout << "Test KO" << endl; \ |
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| 18 | exit (EXIT_FAILURE); \ |
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| 19 | } \ |
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| 20 | } while (0) |
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| 21 | |
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| 22 | |
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| 23 | |
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| 24 | int main (void) |
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| 25 | { |
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| 26 | cout << "<main> Begin" << endl; |
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| 27 | |
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| 28 | { |
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| 29 | cache_onelevel::Parameters * param = new cache_onelevel::Parameters |
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| 30 | ( |
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| 31 | 4, // nb_port |
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| 32 | 32, // nb_line |
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| 33 | 8, // size_line |
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| 34 | 4,// size_word |
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| 35 | 4, // associativity |
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| 36 | 2, // hit_latence |
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| 37 | 3 // miss_penality |
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| 38 | ); |
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| 39 | |
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| 40 | cout << *param << endl; |
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| 41 | |
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| 42 | cache_onelevel::Cache_OneLevel * cache = new cache_onelevel::Cache_OneLevel ("my_cache",param); |
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| 43 | cache->reset(); |
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| 44 | |
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| 45 | cout << *cache << endl; |
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| 46 | |
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| 47 | cache->transition(); |
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| 48 | cache->transition(); |
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| 49 | |
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| 50 | cout << *cache << endl; |
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| 51 | |
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| 52 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), MISS); |
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| 53 | TEST(cache->latence(0), 5); |
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| 54 | cache->transition(); // miss cycle 1 |
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| 55 | |
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| 56 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_WRITE_BUFFER); |
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| 57 | TEST(cache->latence(0), 4); |
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| 58 | cache->transition(); // miss cycle 2 |
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| 59 | |
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| 60 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_WRITE_BUFFER); |
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| 61 | TEST(cache->latence(0), 3); |
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| 62 | cache->transition(); // miss cycle 3 |
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| 63 | |
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| 64 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE); //word 0 |
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| 65 | TEST(cache->latence(0), 2); |
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| 66 | |
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| 67 | TEST(cache->access(0, 0x104, 0, CACHED, WRITE), HIT_CACHE); //word 1 |
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| 68 | TEST(cache->access(0, 0x108, 0, CACHED, WRITE), HIT_CACHE); //word 2 |
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| 69 | TEST(cache->access(0, 0x10c, 0, CACHED, WRITE), HIT_CACHE); //word 3 |
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| 70 | TEST(cache->access(0, 0x110, 0, CACHED, WRITE), HIT_CACHE); //word 4 |
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| 71 | TEST(cache->access(0, 0x114, 0, CACHED, WRITE), HIT_CACHE); //word 5 |
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| 72 | TEST(cache->access(0, 0x118, 0, CACHED, WRITE), HIT_CACHE); //word 6 |
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| 73 | TEST(cache->access(0, 0x11c, 0, CACHED, WRITE), HIT_CACHE); //word 7 |
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| 74 | TEST(cache->access(0, 0x120, 0, CACHED, WRITE), MISS ); |
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| 75 | TEST(cache->access(1, 0x140, 0, CACHED, WRITE), MISS ); |
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| 76 | TEST(cache->access(2, 0x160, 0, CACHED, WRITE), MISS ); |
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| 77 | TEST(cache->access(3, 0x144, 0, CACHED, WRITE), HIT_BYPASS); |
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| 78 | |
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| 79 | TEST(cache->latence(0), 5); |
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| 80 | TEST(cache->latence(1), 5); |
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| 81 | TEST(cache->latence(2), 5); |
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| 82 | TEST(cache->latence(3), 5); |
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| 83 | |
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| 84 | cache->transition(); // miss access |
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| 85 | TEST(cache->access(0, 0x180, 0, CACHED, WRITE), MISS ); |
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| 86 | TEST(cache->access(1, 0x1a0, 0, CACHED, WRITE), MISS ); |
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| 87 | TEST(cache->access(2, 0x1c0, 0, CACHED, WRITE), MISS ); |
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| 88 | TEST(cache->access(3, 0x1e0, 0, CACHED, WRITE), MISS ); |
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| 89 | |
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| 90 | cache->transition(); // miss cycle 1 |
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| 91 | cout << *cache << endl; |
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| 92 | |
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| 93 | TEST(cache->access(0, 0x200, 0, CACHED, WRITE), MISS ); |
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| 94 | TEST(cache->access(1, 0x300, 0, CACHED, WRITE), MISS ); |
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| 95 | TEST(cache->access(2, 0x400, 0, CACHED, WRITE), MISS ); |
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| 96 | |
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| 97 | cache->transition(); // miss cycle 0 |
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| 98 | cache->transition(); // miss cycle 1 |
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| 99 | cache->transition(); // miss cycle 2 |
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| 100 | cache->transition(); // miss cycle 3 |
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| 101 | cout << *cache << endl; |
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| 102 | |
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| 103 | // line 0 : all way is use |
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| 104 | TEST(cache->access(0, 0x118, 0, CACHED, WRITE), HIT_CACHE ); |
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| 105 | TEST(cache->access(1, 0x204, 0, CACHED, WRITE), HIT_CACHE ); |
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| 106 | TEST(cache->access(2, 0x100, 0,UNCACHED, WRITE), MISS ); |
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| 107 | TEST(cache->access(3, 0x118, 0, CACHED, WRITE), HIT_BYPASS); |
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| 108 | |
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| 109 | TEST(cache->latence(0), 2); |
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| 110 | TEST(cache->latence(1), 2); |
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| 111 | TEST(cache->latence(2), 5); |
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| 112 | TEST(cache->latence(3), 2); |
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| 113 | |
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| 114 | cache->transition(); |
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| 115 | cout << *cache << endl; |
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| 116 | |
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| 117 | TEST(cache->access(0, 0x500, 0, CACHED, WRITE), MISS ); |
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| 118 | |
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| 119 | cache->transition(); // miss cycle 1 |
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| 120 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 121 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 122 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 123 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), HIT_CACHE ); |
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| 124 | |
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| 125 | cache->transition(); // miss cycle 2 |
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| 126 | |
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| 127 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 128 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 129 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 130 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), HIT_CACHE ); |
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| 131 | |
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| 132 | cache->transition(); // miss cycle 3 |
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| 133 | TEST(cache->access(0, 0x100, 0, CACHED, WRITE), HIT_CACHE ); |
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| 134 | TEST(cache->access(1, 0x200, 0, CACHED, WRITE), HIT_CACHE ); |
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| 135 | TEST(cache->access(2, 0x300, 0, CACHED, WRITE), HIT_CACHE ); |
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| 136 | TEST(cache->access(3, 0x400, 0, CACHED, WRITE), MISS ); |
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| 137 | |
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| 138 | TEST(cache->latence(0), 2); |
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| 139 | TEST(cache->latence(1), 2); |
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| 140 | TEST(cache->latence(2), 2); |
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| 141 | TEST(cache->latence(3), 5); |
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| 142 | |
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| 143 | cout << *cache << endl; |
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| 144 | |
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| 145 | delete cache; |
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| 146 | delete param; |
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| 147 | } |
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| 148 | |
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| 149 | { |
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| 150 | uint32_t * nb_line = new uint32_t [3]; |
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| 151 | uint32_t * size_line = new uint32_t [3]; |
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| 152 | uint32_t * size_word = new uint32_t [3]; |
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| 153 | uint32_t * associativity = new uint32_t [3]; |
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| 154 | uint32_t * hit_latence = new uint32_t [3]; |
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| 155 | uint32_t * miss_penality = new uint32_t [3]; |
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| 156 | |
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| 157 | nb_line [0] = 4 ; nb_line [1] = 4 ; nb_line [2] = 4 ; |
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| 158 | size_line [0] = 8 ; size_line [1] = 8 ; size_line [2] = 8 ; |
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| 159 | size_word [0] = 4 ; size_word [1] = 4 ; size_word [2] = 4 ; |
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| 160 | associativity [0] = 1 ; associativity [1] = 2 ; associativity [2] = 4 ; |
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| 161 | hit_latence [0] = 1 ; hit_latence [1] = 2 ; hit_latence [2] = 2 ; |
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| 162 | miss_penality [0] = 3 ; miss_penality [1] = 5 ; miss_penality [2] = 7 ; |
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| 163 | |
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| 164 | cache_multilevel::Parameters * param = new cache_multilevel::Parameters |
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| 165 | ( |
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| 166 | 3, // nb_level |
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| 167 | 4, // nb_port |
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| 168 | nb_line , |
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| 169 | size_line , |
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| 170 | size_word , |
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| 171 | associativity, |
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| 172 | hit_latence , |
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| 173 | miss_penality |
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| 174 | ); |
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| 175 | |
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| 176 | cout << *param << endl; |
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| 177 | |
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| 178 | cache_multilevel::Cache_MultiLevel * cache = new cache_multilevel::Cache_MultiLevel ("my_cache",param); |
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| 179 | |
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| 180 | cout << *cache << endl; |
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| 181 | cache->reset(); |
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| 182 | cout << *cache << endl; |
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| 183 | |
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| 184 | cache_multilevel::Access access; |
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| 185 | |
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| 186 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 187 | cache->update_access(access); |
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| 188 | |
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| 189 | TEST(access.num_port , 0); |
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| 190 | TEST(access.hit , MISS); |
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| 191 | TEST(access.latence , 20); |
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| 192 | TEST(access.last_nb_level, 2); |
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| 193 | |
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| 194 | cache->transition(); //19 |
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| 195 | cache->transition(); //18 |
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| 196 | cache->transition(); //17 |
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| 197 | cache->transition(); //16 |
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| 198 | cache->transition(); //15 |
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| 199 | cache->transition(); //14 |
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| 200 | cache->transition(); //13 |
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| 201 | cache->transition(); //12 |
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| 202 | cache->transition(); //11 |
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| 203 | cache->transition(); //10 |
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| 204 | cout << *cache << endl; |
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| 205 | |
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| 206 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 207 | cache->update_access(access); |
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| 208 | |
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| 209 | TEST(access.num_port , 0); |
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| 210 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 211 | TEST(access.latence , 10); |
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| 212 | TEST(access.last_nb_level, 0); |
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| 213 | |
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| 214 | cache->transition(); // 9 |
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| 215 | cache->transition(); // 8 |
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| 216 | cache->transition(); // 7 |
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| 217 | cache->transition(); // 6 |
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| 218 | cache->transition(); // 5 |
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| 219 | cache->transition(); // 4 |
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| 220 | cache->transition(); // 3 |
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| 221 | cache->transition(); // 2 |
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| 222 | |
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| 223 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 224 | cache->update_access(access); |
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| 225 | |
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| 226 | TEST(access.num_port , 0); |
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| 227 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 228 | TEST(access.latence , 2); |
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| 229 | TEST(access.last_nb_level, 0); |
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| 230 | |
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| 231 | cache->transition(); // 1 |
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| 232 | |
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| 233 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 234 | cache->update_access(access); |
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| 235 | |
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| 236 | TEST(access.num_port , 0); |
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| 237 | TEST(access.hit , HIT_CACHE); |
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| 238 | TEST(access.latence , 1); |
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| 239 | TEST(access.last_nb_level, 0); |
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| 240 | cout << *cache << endl; |
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| 241 | |
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| 242 | cache->transition(); |
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| 243 | |
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| 244 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 245 | cache->update_access(access); |
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| 246 | |
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| 247 | TEST(access.num_port , 0); |
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| 248 | TEST(access.hit , HIT_CACHE); |
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| 249 | TEST(access.latence , 1); |
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| 250 | TEST(access.last_nb_level, 0); |
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| 251 | |
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| 252 | |
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| 253 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 254 | cache->update_access(access); |
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| 255 | |
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| 256 | TEST(access.num_port , 0); |
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| 257 | TEST(access.hit , HIT_CACHE); |
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| 258 | TEST(access.latence , 1); |
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| 259 | TEST(access.last_nb_level, 0); |
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| 260 | |
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| 261 | access = cache->access (1, 0x200, 0, CACHED, WRITE); |
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| 262 | cache->update_access(access); |
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| 263 | |
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| 264 | TEST(access.num_port , 1); |
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| 265 | TEST(access.hit , MISS); |
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| 266 | TEST(access.latence , 20); |
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| 267 | TEST(access.last_nb_level, 2); |
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| 268 | |
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| 269 | access = cache->access (2, 0x100, 0, CACHED, WRITE); |
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| 270 | cache->update_access(access); |
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| 271 | |
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| 272 | TEST(access.num_port , 2); |
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| 273 | TEST(access.hit , HIT_BYPASS); |
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| 274 | TEST(access.latence , 1); |
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| 275 | TEST(access.last_nb_level, 0); |
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| 276 | |
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| 277 | access = cache->access (3, 0x200, 0, CACHED, WRITE); |
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| 278 | cache->update_access(access); |
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| 279 | |
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| 280 | TEST(access.num_port , 3); |
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| 281 | TEST(access.hit , HIT_BYPASS); |
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| 282 | TEST(access.latence , 20); |
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| 283 | TEST(access.last_nb_level, 0); |
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| 284 | |
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| 285 | cache->transition(); //19 |
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| 286 | cache->transition(); //18 |
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| 287 | cache->transition(); //17 |
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| 288 | cache->transition(); //16 |
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| 289 | cache->transition(); //15 |
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| 290 | |
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| 291 | |
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| 292 | // access = cache->access (1, 0x300, 0, CACHED, WRITE); |
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| 293 | // cache->update_access(access); |
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| 294 | |
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| 295 | // TEST(access.num_port , 1); |
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| 296 | // TEST(access.hit , MISS); |
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| 297 | // TEST(access.latence , 20); |
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| 298 | // TEST(access.last_nb_level, 2); |
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| 299 | |
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| 300 | cache->transition(); //14 |
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| 301 | cache->transition(); //13 |
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| 302 | cache->transition(); //12 |
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| 303 | cache->transition(); //11 |
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| 304 | cache->transition(); //10 |
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| 305 | cout << *cache << endl; |
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| 306 | |
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| 307 | access = cache->access (0, 0x100, 0, CACHED, WRITE); |
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| 308 | cache->update_access(access); |
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| 309 | |
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| 310 | TEST(access.num_port , 0); |
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| 311 | TEST(access.hit , HIT_CACHE); |
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| 312 | TEST(access.latence , 1); |
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| 313 | TEST(access.last_nb_level, 0); |
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| 314 | |
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| 315 | access = cache->access (1, 0x200, 0, CACHED, WRITE); |
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| 316 | cache->update_access(access); |
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| 317 | |
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| 318 | TEST(access.num_port , 1); |
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| 319 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 320 | TEST(access.latence , 10); |
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| 321 | TEST(access.last_nb_level, 0); |
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| 322 | |
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| 323 | access = cache->access (2, 0x100, 0, CACHED, WRITE); |
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| 324 | cache->update_access(access); |
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| 325 | |
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| 326 | TEST(access.num_port , 2); |
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| 327 | TEST(access.hit , HIT_BYPASS); |
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| 328 | TEST(access.latence , 1); |
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| 329 | TEST(access.last_nb_level, 0); |
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| 330 | |
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| 331 | access = cache->access (3, 0x200, 0, CACHED, WRITE); |
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| 332 | cache->update_access(access); |
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| 333 | |
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| 334 | TEST(access.num_port , 3); |
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| 335 | TEST(access.hit , HIT_WRITE_BUFFER); |
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| 336 | TEST(access.latence , 10); |
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| 337 | TEST(access.last_nb_level, 0); |
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| 338 | |
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| 339 | cache->transition(); //9 |
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| 340 | |
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| 341 | access = cache->access (1, 0x400, 0, CACHED, WRITE); |
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| 342 | cache->update_access(access); |
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| 343 | |
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| 344 | TEST(access.num_port , 1); |
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| 345 | TEST(access.hit , MISS); |
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| 346 | TEST(access.latence , 20); |
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| 347 | TEST(access.last_nb_level, 2); |
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| 348 | |
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| 349 | cache->transition(); //8 |
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| 350 | cache->transition(); //7 |
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| 351 | cache->transition(); //6 |
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| 352 | cache->transition(); //5 |
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| 353 | cache->transition(); //4 |
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| 354 | cache->transition(); //3 |
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| 355 | cache->transition(); //2 |
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| 356 | cache->transition(); //1 |
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| 357 | cache->transition(); //0 |
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| 358 | |
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| 359 | access = cache->access (1, 0x100, 0, CACHED, WRITE); |
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| 360 | cout << access<< endl; |
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| 361 | |
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| 362 | cache->update_access(access); |
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| 363 | |
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| 364 | TEST(access.num_port , 1); |
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| 365 | TEST(access.hit , HIT_CACHE); |
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| 366 | TEST(access.latence , 6 ); |
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| 367 | TEST(access.last_nb_level, 1); |
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| 368 | |
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| 369 | cout << *cache << endl; |
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| 370 | delete cache; |
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| 371 | delete param; |
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| 372 | delete [] nb_line ; |
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| 373 | delete [] size_line ; |
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| 374 | delete [] size_word ; |
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| 375 | delete [] associativity; |
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| 376 | delete [] hit_latence ; |
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| 377 | delete [] miss_penality; |
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| 378 | } |
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| 379 | |
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| 380 | { |
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| 381 | uint32_t * cache_shared_nb_line = new uint32_t [1]; |
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| 382 | uint32_t * cache_shared_size_line = new uint32_t [1]; |
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| 383 | uint32_t * cache_shared_size_word = new uint32_t [1]; |
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| 384 | uint32_t * cache_shared_associativity = new uint32_t [1]; |
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| 385 | uint32_t * cache_shared_hit_latence = new uint32_t [1]; |
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| 386 | uint32_t * cache_shared_miss_penality = new uint32_t [1]; |
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| 387 | |
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| 388 | cache_shared_nb_line [0] = 8 ; |
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| 389 | cache_shared_size_line [0] = 8 ; |
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| 390 | cache_shared_size_word [0] = 4 ; |
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| 391 | cache_shared_associativity [0] = 4 ; |
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| 392 | cache_shared_hit_latence [0] = 2 ; |
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| 393 | cache_shared_miss_penality [0] = 5 ; |
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| 394 | |
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| 395 | uint32_t * icache_nb_level = new uint32_t [2]; |
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| 396 | uint32_t * icache_nb_port = new uint32_t [2]; |
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| 397 | uint32_t ** icache_nb_line = new uint32_t * [2]; |
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| 398 | uint32_t ** icache_size_line = new uint32_t * [2]; |
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| 399 | uint32_t ** icache_size_word = new uint32_t * [2]; |
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| 400 | uint32_t ** icache_associativity = new uint32_t * [2]; |
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| 401 | uint32_t ** icache_hit_latence = new uint32_t * [2]; |
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| 402 | uint32_t ** icache_miss_penality = new uint32_t * [2]; |
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| 403 | |
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| 404 | icache_nb_level [0] = 1; |
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| 405 | icache_nb_port [0] = 2; |
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| 406 | icache_nb_line [0] = new uint32_t [1]; |
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| 407 | icache_size_line [0] = new uint32_t [1]; |
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| 408 | icache_size_word [0] = new uint32_t [1]; |
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| 409 | icache_associativity [0] = new uint32_t [1]; |
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| 410 | icache_hit_latence [0] = new uint32_t [1]; |
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| 411 | icache_miss_penality [0] = new uint32_t [1]; |
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| 412 | |
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| 413 | icache_nb_line [0][0] = 8; |
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| 414 | icache_size_line [0][0] = 8; |
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| 415 | icache_size_word [0][0] = 4; |
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| 416 | icache_associativity [0][0] = 1; |
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| 417 | icache_hit_latence [0][0] = 1; |
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| 418 | icache_miss_penality [0][0] = 3; |
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| 419 | |
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| 420 | icache_nb_level [1] = 2; |
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| 421 | icache_nb_port [1] = 2; |
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| 422 | icache_nb_line [1] = new uint32_t [2]; |
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| 423 | icache_size_line [1] = new uint32_t [2]; |
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| 424 | icache_size_word [1] = new uint32_t [2]; |
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| 425 | icache_associativity [1] = new uint32_t [2]; |
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| 426 | icache_hit_latence [1] = new uint32_t [2]; |
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| 427 | icache_miss_penality [1] = new uint32_t [2]; |
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| 428 | |
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| 429 | icache_nb_line [1][0] = 4; |
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| 430 | icache_size_line [1][0] = 8; |
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| 431 | icache_size_word [1][0] = 4; |
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| 432 | icache_associativity [1][0] = 1; |
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| 433 | icache_hit_latence [1][0] = 1; |
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| 434 | icache_miss_penality [1][0] = 3; |
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| 435 | |
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| 436 | icache_nb_line [1][1] = 4; |
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| 437 | icache_size_line [1][1] = 8; |
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| 438 | icache_size_word [1][1] = 4; |
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| 439 | icache_associativity [1][1] = 4; |
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| 440 | icache_hit_latence [1][1] = 1; |
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| 441 | icache_miss_penality [1][1] = 4; |
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| 442 | |
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| 443 | uint32_t * dcache_nb_level = new uint32_t [2]; |
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| 444 | uint32_t * dcache_nb_port = new uint32_t [2]; |
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| 445 | uint32_t ** dcache_nb_line = new uint32_t * [2]; |
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| 446 | uint32_t ** dcache_size_line = new uint32_t * [2]; |
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| 447 | uint32_t ** dcache_size_word = new uint32_t * [2]; |
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| 448 | uint32_t ** dcache_associativity = new uint32_t * [2]; |
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| 449 | uint32_t ** dcache_hit_latence = new uint32_t * [2]; |
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| 450 | uint32_t ** dcache_miss_penality = new uint32_t * [2]; |
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| 451 | |
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| 452 | dcache_nb_level [0] = 1; |
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| 453 | dcache_nb_port [0] = 2; |
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| 454 | dcache_nb_line [0] = new uint32_t [1]; |
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| 455 | dcache_size_line [0] = new uint32_t [1]; |
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| 456 | dcache_size_word [0] = new uint32_t [1]; |
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| 457 | dcache_associativity [0] = new uint32_t [1]; |
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| 458 | dcache_hit_latence [0] = new uint32_t [1]; |
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| 459 | dcache_miss_penality [0] = new uint32_t [1]; |
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| 460 | |
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| 461 | dcache_nb_line [0][0] = 8; |
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| 462 | dcache_size_line [0][0] = 8; |
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| 463 | dcache_size_word [0][0] = 4; |
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| 464 | dcache_associativity [0][0] = 1; |
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| 465 | dcache_hit_latence [0][0] = 1; |
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| 466 | dcache_miss_penality [0][0] = 3; |
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| 467 | |
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| 468 | dcache_nb_level [1] = 2; |
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| 469 | dcache_nb_port [1] = 2; |
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| 470 | dcache_nb_line [1] = new uint32_t [2]; |
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| 471 | dcache_size_line [1] = new uint32_t [2]; |
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| 472 | dcache_size_word [1] = new uint32_t [2]; |
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| 473 | dcache_associativity [1] = new uint32_t [2]; |
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| 474 | dcache_hit_latence [1] = new uint32_t [2]; |
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| 475 | dcache_miss_penality [1] = new uint32_t [2]; |
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| 476 | |
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| 477 | dcache_nb_line [1][0] = 4; |
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| 478 | dcache_size_line [1][0] = 8; |
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| 479 | dcache_size_word [1][0] = 4; |
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| 480 | dcache_associativity [1][0] = 1; |
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| 481 | dcache_hit_latence [1][0] = 1; |
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| 482 | dcache_miss_penality [1][0] = 3; |
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| 483 | |
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| 484 | dcache_nb_line [1][1] = 4; |
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| 485 | dcache_size_line [1][1] = 8; |
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| 486 | dcache_size_word [1][1] = 4; |
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| 487 | dcache_associativity [1][1] = 4; |
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| 488 | dcache_hit_latence [1][1] = 1; |
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| 489 | dcache_miss_penality [1][1] = 4; |
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| 490 | |
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| 491 | Parameters * param = new Parameters |
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| 492 | (2,//nb_cache_dedicated |
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| 493 | |
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| 494 | icache_nb_level , |
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| 495 | icache_nb_port , |
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| 496 | icache_nb_line , |
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| 497 | icache_size_line , |
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| 498 | icache_size_word , |
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| 499 | icache_associativity , |
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| 500 | icache_hit_latence , |
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| 501 | icache_miss_penality , |
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| 502 | |
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| 503 | dcache_nb_level , |
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| 504 | dcache_nb_port , |
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| 505 | dcache_nb_line , |
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| 506 | dcache_size_line , |
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| 507 | dcache_size_word , |
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| 508 | dcache_associativity , |
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| 509 | dcache_hit_latence , |
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| 510 | dcache_miss_penality , |
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| 511 | |
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| 512 | 1, // nb_level |
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| 513 | cache_shared_nb_line , |
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| 514 | cache_shared_size_line , |
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| 515 | cache_shared_size_word , |
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| 516 | cache_shared_associativity, |
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| 517 | cache_shared_hit_latence , |
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| 518 | cache_shared_miss_penality |
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| 519 | ); |
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| 520 | |
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| 521 | cout << *param << endl; |
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| 522 | |
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| 523 | cache::Cache * cache = new cache::Cache ("my_cache",param); |
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| 524 | |
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| 525 | cout << *cache << endl; |
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| 526 | cache->reset(); |
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| 527 | cout << *cache << endl; |
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| 528 | |
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| 529 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 16); |
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| 530 | cache->transition(); |
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| 531 | TEST(cache->latence (DATA_CACHE, 1, 0, 0x100, 0, CACHED, WRITE), 15); |
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| 532 | cache->transition(); |
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| 533 | |
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| 534 | cout << *cache << endl; |
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| 535 | |
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| 536 | |
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| 537 | delete cache; |
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| 538 | delete param; |
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| 539 | delete [] cache_shared_nb_line ; |
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| 540 | delete [] cache_shared_size_line ; |
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| 541 | delete [] cache_shared_size_word ; |
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| 542 | delete [] cache_shared_associativity; |
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| 543 | delete [] cache_shared_hit_latence ; |
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| 544 | delete [] cache_shared_miss_penality; |
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| 545 | delete [] icache_nb_level ; |
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| 546 | delete [] icache_nb_port ; |
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| 547 | delete [] icache_nb_line [0]; |
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| 548 | delete [] icache_size_line [0]; |
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| 549 | delete [] icache_size_word [0]; |
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| 550 | delete [] icache_associativity [0]; |
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| 551 | delete [] icache_hit_latence [0]; |
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| 552 | delete [] icache_miss_penality [0]; |
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| 553 | delete [] icache_nb_line [1]; |
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| 554 | delete [] icache_size_line [1]; |
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| 555 | delete [] icache_size_word [1]; |
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| 556 | delete [] icache_associativity [1]; |
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| 557 | delete [] icache_hit_latence [1]; |
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| 558 | delete [] icache_miss_penality [1]; |
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| 559 | delete [] icache_nb_line ; |
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| 560 | delete [] icache_size_line ; |
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| 561 | delete [] icache_size_word ; |
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| 562 | delete [] icache_associativity ; |
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| 563 | delete [] icache_hit_latence ; |
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| 564 | delete [] icache_miss_penality ; |
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| 565 | delete [] dcache_nb_level ; |
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| 566 | delete [] dcache_nb_port ; |
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| 567 | delete [] dcache_nb_line [0]; |
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| 568 | delete [] dcache_size_line [0]; |
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| 569 | delete [] dcache_size_word [0]; |
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| 570 | delete [] dcache_associativity [0]; |
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| 571 | delete [] dcache_hit_latence [0]; |
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| 572 | delete [] dcache_miss_penality [0]; |
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| 573 | delete [] dcache_nb_line [1]; |
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| 574 | delete [] dcache_size_line [1]; |
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| 575 | delete [] dcache_size_word [1]; |
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| 576 | delete [] dcache_associativity [1]; |
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| 577 | delete [] dcache_hit_latence [1]; |
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| 578 | delete [] dcache_miss_penality [1]; |
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| 579 | delete [] dcache_nb_line ; |
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| 580 | delete [] dcache_size_line ; |
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| 581 | delete [] dcache_size_word ; |
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| 582 | delete [] dcache_associativity ; |
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| 583 | delete [] dcache_hit_latence ; |
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| 584 | delete [] dcache_miss_penality ; |
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| 585 | } |
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| 586 | |
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| 587 | cout << "<main> End" << endl; |
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| 588 | |
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| 589 | return EXIT_SUCCESS; |
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| 590 | } |
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