[2] | 1 | #ifndef CACHE_H |
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| 2 | #define CACHE_H |
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| 3 | |
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| 4 | #include <stdint.h> |
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| 5 | #include <stdarg.h> |
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| 6 | #include <iostream> |
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| 7 | #include "cache_multilevel.h" |
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| 8 | #include "cache_onelevel.h" |
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| 9 | #include "type_req_cache.h" |
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| 10 | #include "type_rsp_cache.h" |
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| 11 | |
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| 12 | using namespace std; |
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| 13 | using namespace hierarchy_memory::cache::cache_multilevel; |
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| 14 | |
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| 15 | |
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| 16 | namespace hierarchy_memory { |
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| 17 | namespace cache { |
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| 18 | typedef enum |
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| 19 | { |
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| 20 | INSTRUCTION_CACHE , |
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| 21 | DATA_CACHE |
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| 22 | } cache_t; |
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| 23 | |
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| 24 | class param_t |
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| 25 | { |
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| 26 | public : const char * name ; |
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| 27 | public : uint32_t nb_entity ; |
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| 28 | public : cache_multilevel::param_t * param_icache_dedicated; // 1 each entity |
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| 29 | public : cache_multilevel::param_t * param_dcache_dedicated; // 1 each entity |
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| 30 | public : cache_multilevel::param_t param_cache_shared ; // 1 to all entity and I/D is unify |
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| 31 | |
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| 32 | public : param_t () {}; |
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| 33 | |
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| 34 | public : param_t (const char * name , |
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| 35 | uint32_t nb_entity , |
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| 36 | cache_multilevel::param_t * param_icache_dedicated, |
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| 37 | cache_multilevel::param_t * param_dcache_dedicated, |
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| 38 | cache_multilevel::param_t param_cache_shared |
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| 39 | ) : |
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| 40 | name (name) |
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| 41 | { |
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| 42 | this->name = name ; |
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| 43 | this->nb_entity = nb_entity ; |
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| 44 | this->param_icache_dedicated = param_icache_dedicated ; |
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| 45 | this->param_dcache_dedicated = param_dcache_dedicated ; |
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| 46 | this->param_cache_shared = param_cache_shared ; |
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| 47 | } |
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| 48 | |
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| 49 | friend ostream& operator<< (ostream& output_stream, const param_t & x) |
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| 50 | { |
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| 51 | output_stream << "<" << x.name << ">" << endl |
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| 52 | << " * nb_entity : " << x.nb_entity << endl; |
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| 53 | |
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| 54 | for (uint32_t it = 0; it < x.nb_entity; it ++) |
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| 55 | output_stream << x.param_icache_dedicated [it] << endl; |
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| 56 | for (uint32_t it = 0; it < x.nb_entity; it ++) |
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| 57 | output_stream << x.param_dcache_dedicated [it] << endl; |
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| 58 | |
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| 59 | output_stream << x.param_cache_shared << endl; |
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| 60 | |
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| 61 | return output_stream; |
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| 62 | } |
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| 63 | |
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| 64 | };//end param_t |
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| 65 | |
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| 66 | |
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| 67 | class Cache |
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| 68 | { |
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| 69 | private : char * name ; |
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| 70 | protected: const uint32_t nb_entity ; |
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| 71 | protected: uint32_t nb_iport ; |
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| 72 | protected: uint32_t nb_dport ; |
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| 73 | |
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| 74 | protected: Cache_Multilevel ** icache_dedicated; |
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| 75 | protected: Cache_Multilevel ** dcache_dedicated; |
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| 76 | protected: Cache_Multilevel * cache_shared ; |
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| 77 | |
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| 78 | //*****[ constructor ]***** |
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| 79 | public : Cache (param_t param): |
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| 80 | nb_entity (param.nb_entity) |
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| 81 | { |
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| 82 | uint32_t size_name = strlen(param.name)+1; |
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| 83 | name = new char [size_name]; |
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| 84 | strncpy(name,param.name,size_name); |
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| 85 | |
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| 86 | cache_shared = new Cache_Multilevel (param.param_cache_shared); |
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| 87 | icache_dedicated = new Cache_Multilevel * [nb_entity]; |
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| 88 | dcache_dedicated = new Cache_Multilevel * [nb_entity]; |
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| 89 | |
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| 90 | nb_iport = 0; |
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| 91 | nb_dport = 0; |
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| 92 | for (uint32_t it = 0; it < nb_entity ; it++) |
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| 93 | { |
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| 94 | icache_dedicated [it] = new Cache_Multilevel (param.param_icache_dedicated[it]); |
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| 95 | dcache_dedicated [it] = new Cache_Multilevel (param.param_dcache_dedicated[it]); |
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| 96 | nb_iport += param.param_icache_dedicated[it].nb_port; |
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| 97 | nb_dport += param.param_dcache_dedicated[it].nb_port; |
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| 98 | } |
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| 99 | |
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| 100 | information(); |
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| 101 | }; |
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| 102 | |
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| 103 | //*****[ destructor ]***** |
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| 104 | public : ~Cache () |
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| 105 | { |
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| 106 | for (uint32_t it = 0; it < nb_entity ; it++) |
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| 107 | { |
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| 108 | delete icache_dedicated [it]; |
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| 109 | delete dcache_dedicated [it]; |
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| 110 | } |
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| 111 | delete cache_shared ; |
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| 112 | }; |
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| 113 | |
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| 114 | //*****[ reset ]***** |
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| 115 | void reset () |
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| 116 | { |
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| 117 | cache_shared -> reset(); |
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| 118 | // Reset buffer of respons |
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| 119 | for (uint32_t it = 0; it < nb_entity; it++) |
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| 120 | { |
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| 121 | icache_dedicated [it] ->reset(); |
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| 122 | dcache_dedicated [it] ->reset(); |
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| 123 | } |
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| 124 | }//end reset |
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| 125 | |
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| 126 | //*****[ transition ]***** |
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| 127 | void transition() |
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| 128 | { |
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| 129 | cache_shared -> transition(); |
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| 130 | // Transition buffer of respons |
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| 131 | for (uint32_t it = 0; it < nb_entity; it++) |
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| 132 | { |
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| 133 | icache_dedicated [it] ->transition(); |
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| 134 | dcache_dedicated [it] ->transition(); |
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| 135 | } |
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| 136 | }//end transition |
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| 137 | |
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| 138 | //*****[ range_port ]***** |
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| 139 | public : uint32_t range_port (cache_t type_cache, |
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| 140 | uint32_t num_entity) |
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| 141 | { |
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| 142 | uint32_t nb_port_dedicated = 0; |
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| 143 | |
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| 144 | if (type_cache == INSTRUCTION_CACHE) |
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| 145 | for (uint32_t it = 1; it < num_entity; it++ ) |
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| 146 | nb_port_dedicated += icache_dedicated [it]->nb_port; |
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| 147 | else |
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| 148 | { |
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| 149 | nb_port_dedicated = nb_iport; |
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| 150 | for (uint32_t it = 1; it < num_entity; it++) |
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| 151 | nb_port_dedicated += dcache_dedicated [it]->nb_port; |
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| 152 | } |
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| 153 | return nb_port_dedicated; |
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| 154 | } |
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| 155 | |
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| 156 | //*****[ latence ]***** |
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| 157 | // Return the time to have the data |
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| 158 | // latence is call on the same port in a single cycle, only the last access is save |
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| 159 | // { NOTE } : type_cache = 0 : icache, 1 : dcache |
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| 160 | public : uint32_t latence (cache_t type_cache, |
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| 161 | uint32_t num_entity, |
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| 162 | uint32_t num_port , |
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| 163 | uint32_t address , |
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| 164 | uint32_t trdid , |
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| 165 | type_req_cache_t type , |
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| 166 | direction_req_cache_t dir ) |
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| 167 | { |
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| 168 | if (num_entity >= nb_entity) |
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| 169 | { |
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| 170 | cerr << "<Cache.latence> {ERROR} num_entity ("<< num_entity << ") can be >= nb_entity (" << nb_entity << ")" << endl; |
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| 171 | exit (1); |
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| 172 | } |
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| 173 | |
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| 174 | Cache_Multilevel * cache; |
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| 175 | if (type_cache == INSTRUCTION_CACHE) |
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| 176 | cache = icache_dedicated [num_entity]; |
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| 177 | else |
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| 178 | cache = dcache_dedicated [num_entity]; |
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| 179 | |
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| 180 | if (num_port >= cache->nb_port) |
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| 181 | { |
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| 182 | cerr << "<Cache.latence> {ERROR} num_port ("<< num_port << ") can be >= nb_port (" << cache->nb_port << ")" << endl; |
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| 183 | exit (1); |
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| 184 | } |
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| 185 | // Make a access with this level "dedicated" |
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| 186 | |
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| 187 | access_t access_dedicated = cache->access(num_port,address,trdid,type,dir); |
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| 188 | |
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| 189 | // cout << "access_dedicated : " << access_dedicated << endl; |
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| 190 | |
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| 191 | if (access_dedicated.hit == MISS) |
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| 192 | { |
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| 193 | // Make a access with this level "shared" |
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| 194 | access_t access_shared = cache_shared->access(range_port (type_cache,num_entity)+num_port,address,trdid,type,dir); |
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| 195 | // cout << "access_shared : " << access_shared << endl; |
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| 196 | |
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| 197 | cache_shared->update_access (access_shared); |
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| 198 | |
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| 199 | access_dedicated.last_nb_level = cache->nb_level; // Update all cache |
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| 200 | access_dedicated.latence += access_shared.latence; |
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| 201 | |
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| 202 | // cout << "access_dedicated (after) : " << access_dedicated << endl; |
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| 203 | } |
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| 204 | |
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| 205 | cache->update_access (access_dedicated); |
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| 206 | return access_dedicated.latence; |
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| 207 | } |
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| 208 | |
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| 209 | //*****[ information ]***** |
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| 210 | public : void information (void) |
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| 211 | { |
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| 212 | cout << "<" << name << ">" << endl; |
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| 213 | |
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| 214 | for (uint32_t it = 0; it < nb_entity; it ++) |
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| 215 | icache_dedicated [it]->information(); |
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| 216 | for (uint32_t it = 0; it < nb_entity; it ++) |
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| 217 | dcache_dedicated [it]->information(); |
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| 218 | |
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| 219 | cache_shared->information(); |
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| 220 | } |
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| 221 | |
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| 222 | |
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| 223 | friend ostream& operator<< (ostream& output_stream, const Cache & x) |
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| 224 | { |
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| 225 | output_stream << "<" << x.name << ">" << endl; |
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| 226 | |
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| 227 | for (uint32_t it = 0; it < x.nb_entity; it ++) |
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| 228 | output_stream << *x.icache_dedicated [it] << endl; |
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| 229 | for (uint32_t it = 0; it < x.nb_entity; it ++) |
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| 230 | output_stream << *x.dcache_dedicated [it] << endl; |
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| 231 | |
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| 232 | output_stream << *x.cache_shared << endl; |
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| 233 | |
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| 234 | return output_stream; |
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| 235 | } |
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| 236 | |
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| 237 | };//end Cache |
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| 238 | };}; |
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| 239 | #endif //!CACHE_H |
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