1 | #ifndef CACHE_MULTILEVEL_H |
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2 | #define CACHE_MULTILEVEL_H |
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3 | |
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4 | #include <stdint.h> |
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5 | #include <stdarg.h> |
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6 | #include <iostream> |
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7 | #include "cache_onelevel.h" |
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8 | #include "type_req_cache.h" |
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9 | #include "type_rsp_cache.h" |
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10 | |
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11 | using namespace std; |
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12 | using namespace hierarchy_memory::cache::cache_multilevel::cache_onelevel; |
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13 | |
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14 | namespace hierarchy_memory { |
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15 | namespace cache { |
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16 | namespace cache_multilevel { |
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17 | |
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18 | class param_t |
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19 | { |
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20 | public : const char * name ; |
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21 | public : uint32_t nb_level ; |
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22 | public : uint32_t nb_port ; |
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23 | public : param_cache_t * param_cache ; |
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24 | |
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25 | public : param_t () {}; |
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26 | |
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27 | public : param_t (const char * name , |
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28 | uint32_t nb_level , |
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29 | uint32_t nb_port , |
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30 | param_cache_t * param_cache ) : |
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31 | name (name) |
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32 | { |
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33 | //this->name = name ; |
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34 | this->nb_level = nb_level ; |
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35 | this->nb_port = nb_port ; |
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36 | this->param_cache = param_cache ; |
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37 | } |
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38 | |
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39 | friend ostream& operator<< (ostream& output_stream, const param_t & x) |
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40 | { |
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41 | output_stream << "<" << x.name << "> " |
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42 | << x.nb_level << " " |
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43 | << x.nb_port; |
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44 | |
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45 | for (uint32_t it = 0; it < x.nb_level; it ++) |
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46 | output_stream << endl << x.param_cache [it]; |
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47 | return output_stream; |
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48 | } |
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49 | |
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50 | };//end param_t |
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51 | |
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52 | class access_t |
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53 | { |
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54 | public : uint32_t num_port ; |
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55 | public : type_rsp_cache_t hit ; // result of access |
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56 | public : uint32_t latence ; // Latence of access |
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57 | public : uint32_t last_nb_level; // if access is not a hit : last level of cache before a error |
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58 | |
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59 | public : access_t (uint32_t num_port , |
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60 | type_rsp_cache_t hit , |
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61 | uint32_t latence , |
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62 | uint32_t last_nb_level) |
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63 | { |
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64 | this->num_port = num_port ; |
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65 | this->hit = hit ; |
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66 | this->latence = latence ; |
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67 | this->last_nb_level = last_nb_level; |
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68 | } |
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69 | |
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70 | friend ostream& operator<< (ostream& output_stream, const access_t & x) |
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71 | { |
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72 | output_stream << "[" |
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73 | << x.num_port << "] " |
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74 | << x.hit << " " |
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75 | << x.latence << " " |
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76 | << x.last_nb_level; |
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77 | return output_stream; |
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78 | } |
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79 | };//access_t |
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80 | |
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81 | class Cache_Multilevel |
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82 | { |
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83 | private : char * name; |
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84 | protected : Cache_OneLevel ** hierarchy_cache; |
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85 | public : const uint32_t nb_level; |
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86 | public : const uint32_t nb_port ; |
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87 | |
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88 | //*****[ constructor ]***** |
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89 | public : Cache_Multilevel (param_t param) : |
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90 | nb_level (param.nb_level), |
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91 | nb_port (param.nb_port ) |
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92 | { |
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93 | uint32_t size_name = strlen(param.name)+1; |
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94 | name = new char [size_name]; |
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95 | strncpy(name,param.name,size_name); |
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96 | |
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97 | hierarchy_cache = new Cache_OneLevel * [nb_level]; |
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98 | |
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99 | // Creation of Cache hierarchy |
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100 | for (uint32_t it = 0; it < nb_level; it ++) |
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101 | hierarchy_cache [it] = new Cache_OneLevel (cache_onelevel::param_t(param.nb_port , |
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102 | param.param_cache [it])); |
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103 | } |
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104 | |
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105 | //*****[ destructor ]***** |
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106 | public : ~Cache_Multilevel () |
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107 | { |
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108 | for (uint32_t it = 0; it < nb_level; it ++) |
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109 | delete hierarchy_cache [it]; |
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110 | }; |
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111 | //*****[ reset ]***** |
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112 | public : void reset () |
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113 | { |
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114 | for (uint32_t it = 0; it < nb_level; it ++) |
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115 | hierarchy_cache [it]->reset(); |
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116 | } |
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117 | |
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118 | //*****[ transition ]***** |
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119 | public : void transition () |
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120 | { |
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121 | for (uint32_t it = 0; it < nb_level; it ++) |
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122 | hierarchy_cache [it]->transition(); |
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123 | } |
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124 | |
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125 | //*****[ access ]***** |
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126 | public : access_t access (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) |
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127 | { |
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128 | uint32_t time = 0; |
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129 | uint32_t last_nb_level = (nb_level==0)?0:(nb_level-1); |
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130 | type_rsp_cache_t hit = MISS; |
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131 | |
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132 | for (uint32_t it_nb_level = 0; it_nb_level < nb_level; it_nb_level ++) |
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133 | { |
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134 | hit = hierarchy_cache[it_nb_level]->access(num_port,address,trdid,type,dir); |
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135 | time += hierarchy_cache [it_nb_level]->latence (num_port); |
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136 | |
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137 | if ( (hit == HIT_CACHE) || |
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138 | (hit == HIT_WRITE_BUFFER) || |
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139 | (hit == HIT_BYPASS) ) |
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140 | { |
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141 | last_nb_level = it_nb_level; |
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142 | break; |
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143 | } |
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144 | } |
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145 | return access_t (num_port,hit,time,last_nb_level); |
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146 | } |
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147 | |
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148 | //*****[ update_access ]***** |
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149 | public : uint32_t update_access (access_t cur_access) |
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150 | { |
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151 | for (uint32_t it = 0; it < cur_access.last_nb_level; it ++) |
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152 | hierarchy_cache [it]->update_latence (cur_access.num_port,cur_access.latence); |
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153 | |
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154 | return cur_access.latence; |
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155 | } |
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156 | |
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157 | //*****[ latence ]***** |
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158 | // Return the time to have the data |
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159 | // latence is call on the same port in a single cycle, only the last access is save |
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160 | public : uint32_t latence (uint32_t num_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) |
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161 | { |
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162 | return update_access (access (num_port, address, trdid, type, dir)); |
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163 | } |
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164 | |
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165 | //*****[ information ]***** |
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166 | public : void information (void) |
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167 | { |
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168 | cout << "<" << name << ">" << endl; |
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169 | for (uint32_t it = 0; it < nb_level; it ++) |
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170 | hierarchy_cache [it]->information(); |
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171 | } |
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172 | |
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173 | friend ostream& operator<< (ostream& output_stream, const Cache_Multilevel & x) |
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174 | { |
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175 | output_stream << "<" << x.name << ">" << endl; |
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176 | |
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177 | for (uint32_t it = 0; it < x.nb_level; it ++) |
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178 | output_stream << *x.hierarchy_cache [it] << endl; |
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179 | |
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180 | return output_stream; |
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181 | } |
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182 | }; |
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183 | |
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184 | };};}; |
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185 | #endif //!CACHE_MULTILEVEL_H |
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186 | |
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