1 | #ifndef CACHE_ONELEVEL_H |
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2 | #define CACHE_ONELEVEL_H |
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3 | |
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4 | #include <stdint.h> |
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5 | #include <math.h> |
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6 | #include <iostream> |
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7 | #include <iomanip> |
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8 | #include "../file/sort_file_dynamic.h" |
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9 | #include "type_req_cache.h" |
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10 | #include "tag.h" |
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11 | #include "address.h" |
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12 | #include "access_port.h" |
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13 | #include "write_buffer.h" |
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14 | |
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15 | namespace hierarchy_memory { |
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16 | namespace cache { |
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17 | namespace cache_multilevel { |
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18 | namespace cache_onelevel { |
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19 | |
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20 | class param_cache_t |
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21 | { |
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22 | public : const char * name ; |
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23 | public : uint32_t nb_line ; |
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24 | public : uint32_t size_line ; |
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25 | public : uint32_t size_word ; |
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26 | public : uint32_t associativity; |
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27 | public : uint32_t hit_latence ; |
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28 | public : uint32_t miss_penality; |
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29 | |
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30 | public : param_cache_t () {}; |
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31 | |
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32 | public : param_cache_t (const char * name , |
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33 | uint32_t nb_line , |
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34 | uint32_t size_line , |
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35 | uint32_t size_word , |
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36 | uint32_t associativity, |
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37 | uint32_t hit_latence , |
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38 | uint32_t miss_penality |
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39 | ) : |
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40 | name (name) |
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41 | { |
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42 | //this->name = name ; |
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43 | this->nb_line = nb_line ; |
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44 | this->size_line = size_line ; |
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45 | this->size_word = size_word ; |
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46 | this->associativity = associativity; |
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47 | this->hit_latence = hit_latence ; |
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48 | this->miss_penality = miss_penality; |
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49 | } |
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50 | |
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51 | friend ostream& operator<< (ostream& output_stream, const param_cache_t & x) |
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52 | { |
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53 | output_stream << "<" << x.name << "> " |
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54 | << x.nb_line << " " |
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55 | << x.size_line << " " |
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56 | << x.size_word << " " |
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57 | << x.associativity << " " |
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58 | << x.hit_latence << " " |
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59 | << x.miss_penality; |
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60 | |
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61 | return output_stream; |
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62 | } |
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63 | };//end param_cache_t |
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64 | |
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65 | class param_t |
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66 | { |
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67 | public : uint32_t nb_port ; |
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68 | public : param_cache_t param_cache; |
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69 | |
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70 | public : param_t (uint32_t nb_port , |
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71 | param_cache_t param_cache) |
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72 | { |
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73 | this->nb_port = nb_port ; |
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74 | this->param_cache = param_cache ; |
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75 | } |
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76 | |
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77 | friend ostream& operator<< (ostream& output_stream, const param_t & x) |
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78 | { |
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79 | output_stream << x.nb_port << " " |
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80 | << x.param_cache; |
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81 | return output_stream; |
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82 | } |
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83 | |
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84 | };//end param_t |
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85 | |
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86 | class Cache_OneLevel |
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87 | { |
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88 | protected : const uint32_t nb_port ; |
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89 | protected : const uint32_t nb_line ; |
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90 | protected : const uint32_t size_line ; |
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91 | protected : const uint32_t size_word ; |
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92 | protected : const uint32_t associativity ; |
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93 | protected : const uint32_t hit_latence ; |
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94 | protected : const uint32_t miss_penality ; |
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95 | |
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96 | private : char * name; |
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97 | private : tag_t ** tag; |
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98 | private : access_port_t * access_port; |
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99 | private : address_t size_address; |
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100 | private : Sort_File_Dynamic<write_buffer_t> * write_buffer; |
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101 | |
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102 | //*****[ constructor ]***** |
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103 | public : Cache_OneLevel (param_t param): |
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104 | nb_port (param.nb_port ), |
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105 | nb_line (param.param_cache.nb_line ), |
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106 | size_line (param.param_cache.size_line ), |
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107 | size_word (param.param_cache.size_word ), |
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108 | associativity (param.param_cache.associativity), |
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109 | hit_latence (param.param_cache.hit_latence ), |
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110 | miss_penality (param.param_cache.miss_penality) |
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111 | { |
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112 | uint32_t size_name = strlen(param.param_cache.name)+1; |
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113 | name = new char [size_name]; |
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114 | strncpy(name,param.param_cache.name,size_name); |
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115 | |
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116 | if ((nb_line * size_line * associativity) == 0) |
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117 | { |
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118 | cerr << "<" << name << ".{Cache_OneLevel}> all parameter must be greater that 0" << endl; |
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119 | cerr << " nb_line : " << nb_line << endl; |
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120 | cerr << " size_line : " << size_line << endl; |
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121 | cerr << " associativity : " << associativity << endl; |
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122 | exit(1); |
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123 | } |
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124 | if ((nb_line % associativity) != 0) |
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125 | { |
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126 | cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of associativity" << endl; |
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127 | cerr << " * nb_line : " << nb_line << endl; |
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128 | cerr << " * associativity : " << associativity << endl; |
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129 | exit(1); |
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130 | } |
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131 | |
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132 | if ((double)nb_line != ::pow(2,::log2(nb_line))) |
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133 | { |
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134 | cerr << "<" << name << ".{Cache_OneLevel}> nb_line must be a mutiple of 2^n" << endl; |
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135 | cerr << " * nb_line : " << nb_line << endl; |
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136 | exit(1); |
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137 | } |
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138 | |
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139 | if ((double)size_line != ::pow(2,::log2(size_line))) |
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140 | { |
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141 | cerr << "<" << name << ".{Cache_OneLevel}> size_line must be a mutiple of 2^n" << endl; |
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142 | cerr << " * size_line : " << size_line << endl; |
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143 | exit(1); |
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144 | } |
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145 | |
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146 | if ((double)size_word != ::pow(2,::log2(size_word))) |
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147 | { |
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148 | cerr << "<" << name << ".{Cache_OneLevel}> size_word must be a mutiple of 2^n" << endl; |
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149 | cerr << " * size_word : " << size_word << endl; |
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150 | exit(1); |
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151 | } |
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152 | |
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153 | write_buffer= new Sort_File_Dynamic<write_buffer_t> (sort_file::param_t("write_buffer",5)); |
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154 | access_port = new access_port_t [nb_port]; |
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155 | tag = new tag_t * [nb_line/associativity]; |
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156 | for (uint32_t it = 0; it < nb_line/associativity; it ++) |
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157 | tag [it] = new tag_t [associativity]; |
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158 | |
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159 | size_address.offset = (uint32_t) log2(size_line * size_word); |
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160 | size_address.familly = (uint32_t) log2(nb_line/associativity); |
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161 | size_address.tag = 32 - size_address.familly - size_address.offset; |
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162 | } |
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163 | |
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164 | //*****[ destructor ]***** |
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165 | public : ~Cache_OneLevel () |
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166 | { |
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167 | // delete tag; |
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168 | // delete access_port; |
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169 | }; |
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170 | |
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171 | //*****[ reset ]***** |
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172 | public : void reset () |
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173 | { |
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174 | for (uint32_t x = 0; x < nb_port; x ++) |
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175 | access_port[x].valid = false; |
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176 | |
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177 | for (uint32_t x = 0; x < nb_line/associativity; x ++) |
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178 | for (uint32_t y = 0; y < associativity; y ++) |
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179 | { |
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180 | tag[x][y].valid = false; |
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181 | tag[x][y].index_lru = y; |
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182 | } |
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183 | write_buffer->reset(); |
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184 | } |
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185 | |
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186 | //*****[ transition ]***** |
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187 | public : void transition () |
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188 | { |
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189 | // scan all port - test if have a transaction |
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190 | for (int32_t x = nb_port-1; x >= 0; x --) |
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191 | { |
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192 | if (access_port[x].valid == true) |
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193 | { |
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194 | access_port[x].valid = false; |
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195 | |
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196 | // Update LRU |
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197 | // * hit : now |
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198 | // * miss : after the return of next cache |
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199 | |
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200 | if (access_port[x].hit == HIT_CACHE) |
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201 | {// Hit |
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202 | update_lru(access_port[x].address.familly,access_port[x].num_associativity); |
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203 | } |
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204 | |
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205 | if (access_port[x].hit == MISS) |
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206 | {// Miss |
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207 | // Write in write_buffer |
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208 | write_buffer->push(access_port[x].latence,write_buffer_t(access_port[x].address,access_port[x].trdid)); |
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209 | } |
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210 | } |
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211 | } |
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212 | |
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213 | // Test if a write_buffer have the result |
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214 | while ((write_buffer->empty() == false) && (write_buffer->read(0).delay == 0)) |
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215 | { |
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216 | // Save in the cache |
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217 | write_buffer_t val = write_buffer->pop(); |
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218 | |
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219 | uint32_t num_tag = val.address.tag; |
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220 | uint32_t num_familly = val.address.familly; |
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221 | uint32_t num_associativity = index_victim(num_familly); |
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222 | |
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223 | tag [num_familly][num_associativity].valid = true; |
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224 | tag [num_familly][num_associativity].address = num_tag; |
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225 | tag [num_familly][num_associativity].trdid = val.trdid; |
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226 | |
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227 | update_lru(num_familly,num_associativity); |
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228 | } |
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229 | |
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230 | write_buffer->transition(); |
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231 | } |
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232 | //*****[ update_lru ]***** |
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233 | private : void update_lru (uint32_t familly, uint32_t num_associativity) |
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234 | { |
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235 | uint32_t current_lru = tag [familly][num_associativity].index_lru; |
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236 | |
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237 | for (uint32_t k = 0; k < associativity; k ++) |
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238 | if (tag [familly][k].index_lru < current_lru) |
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239 | tag [familly][k].index_lru ++; |
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240 | tag [familly][num_associativity].index_lru = 0; |
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241 | } |
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242 | |
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243 | //*****[ index_victim ]***** |
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244 | // return the index of the nex victim |
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245 | public : uint32_t index_victim (uint32_t familly) |
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246 | { |
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247 | uint32_t victim = 0; |
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248 | while (tag [familly][victim].index_lru != (associativity-1)) |
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249 | { |
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250 | victim ++; |
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251 | } |
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252 | |
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253 | return victim; |
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254 | } |
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255 | |
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256 | //*****[ translate_address ]***** |
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257 | private : address_t translate_address (uint32_t address) |
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258 | { |
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259 | address_t address_translated; |
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260 | uint32_t shift; |
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261 | |
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262 | address_translated.offset = (address & ((uint32_t)-1 >> (32-(size_address.offset )))); |
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263 | address -= address_translated.offset; |
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264 | shift = size_address.offset; |
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265 | address_translated.familly = (address & ((uint32_t)-1 >> (32-(size_address.familly + shift))))>>shift; |
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266 | address -= address_translated.familly; |
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267 | shift += size_address.familly; |
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268 | address_translated.tag = (address & ((uint32_t)-1 >> (32-(size_address.tag + shift))))>>shift; |
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269 | |
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270 | return address_translated; |
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271 | } |
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272 | |
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273 | //******************** |
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274 | //******************** |
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275 | |
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276 | //*****[ access ]***** |
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277 | // Return hit (true) |
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278 | // uncache is to stocke the address on the cache |
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279 | public : type_rsp_cache_t access (uint32_t nb_port, uint32_t address, uint32_t trdid, type_req_cache_t type, direction_req_cache_t dir) |
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280 | { |
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281 | switch (type) |
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282 | { |
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283 | case UNCACHED : return access_uncached (nb_port,address,trdid ); break; |
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284 | case INVALIDATE : return access_invalidate (nb_port,address,trdid ); break; |
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285 | case FLUSH : return access_flush (nb_port,address,trdid ); break; |
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286 | case PREFETCH : // no difference with the simple read cached (have no add a prefetch cache) |
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287 | case CACHED : return access_cached (nb_port,address,trdid,dir); break; |
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288 | default : cout << "<Cache_Onelevel.access> unkonow type : " << endl; exit(1); break; |
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289 | } |
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290 | } |
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291 | |
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292 | // *****[ access_cached ]***** |
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293 | public : type_rsp_cache_t access_cached (uint32_t nb_port, uint32_t address, uint32_t trdid, direction_req_cache_t dir) |
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294 | { |
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295 | address_t address_translate = translate_address(address); |
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296 | uint32_t num_associativity = hit_cache (trdid, address_translate); |
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297 | uint32_t num_port = hit_access_port (trdid, address_translate); |
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298 | uint32_t num_write_buffer = hit_write_buffer (trdid, address_translate); |
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299 | |
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300 | if (num_port == this->nb_port) |
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301 | num_port = nb_port; |
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302 | |
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303 | uint32_t latence ; |
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304 | type_rsp_cache_t res = MISS; |
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305 | |
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306 | bool is_in_cache = (num_associativity != associativity); |
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307 | bool is_in_access_port = (num_port != nb_port); |
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308 | bool is_in_write_buffer = false; |
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309 | |
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310 | if (is_in_access_port == true) |
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311 | { |
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312 | res = HIT_BYPASS; |
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313 | latence = access_port[num_port].latence; //already compute |
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314 | } |
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315 | else |
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316 | if (is_in_cache == true) |
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317 | { |
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318 | res = HIT_CACHE; |
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319 | latence = 0; // Hit !!! |
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320 | } |
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321 | else |
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322 | { |
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323 | // Search in the write buffer, and test if have a miss |
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324 | if ( num_write_buffer == write_buffer->nb_slot_use()) |
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325 | { |
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326 | res = MISS; |
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327 | latence = miss_penality; // miss -> access at down of cache, + respons at the up of cache |
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328 | } |
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329 | else |
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330 | { |
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331 | res = HIT_WRITE_BUFFER; |
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332 | is_in_write_buffer = true; |
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333 | latence = write_buffer->read(num_write_buffer).delay; |
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334 | } |
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335 | } |
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336 | |
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337 | // access_port valid = there are a new request to update |
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338 | // -> no previous request in the same cycle (hit in a access port) |
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339 | // -> no previous request in the previous cycle (hit in the write buffer) |
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340 | |
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341 | access_port[nb_port].valid = ((is_in_access_port || is_in_write_buffer) == false); |
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342 | access_port[nb_port].address = address_translate; |
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343 | access_port[nb_port].trdid = trdid; |
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344 | access_port[nb_port].hit = res; |
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345 | access_port[nb_port].num_associativity = num_associativity; |
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346 | access_port[nb_port].latence = latence; |
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347 | |
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348 | return res; |
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349 | } |
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350 | |
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351 | // *****[ access_uncached ]***** |
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352 | public : type_rsp_cache_t access_uncached (uint32_t nb_port, uint32_t address, uint32_t trdid) |
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353 | { |
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354 | access_port[nb_port].valid = false; |
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355 | access_port[nb_port].trdid = trdid; |
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356 | access_port[nb_port].hit = MISS; |
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357 | access_port[nb_port].latence = miss_penality; |
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358 | |
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359 | return MISS; |
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360 | } |
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361 | // *****[ access_invalidate ]***** |
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362 | public : type_rsp_cache_t access_invalidate (uint32_t nb_port, uint32_t address, uint32_t trdid) |
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363 | { |
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364 | cerr << "<" << name << ".{Cache_OneLevel}.access_invalidate> Not implemented" << endl; |
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365 | exit (0); |
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366 | return MISS; |
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367 | } |
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368 | |
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369 | // *****[ access_flush ]***** |
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370 | public : type_rsp_cache_t access_flush (uint32_t nb_port, uint32_t address, uint32_t trdid) |
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371 | { |
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372 | cerr << "<" << name << ".{Cache_OneLevel}.access_flush> Not implemented" << endl; |
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373 | exit (0); |
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374 | return MISS; |
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375 | } |
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376 | |
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377 | //****************************** |
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378 | //****************************** |
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379 | |
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380 | //*****[ hit_write_buffer ]***** |
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381 | |
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382 | // If a instruction is in the write_buffer, return the position |
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383 | // else, return the number of elt in the write_buffer |
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384 | public : uint32_t hit_write_buffer (uint32_t trdid, address_t address) |
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385 | { |
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386 | uint32_t num_write_buffer = 0; |
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387 | // Scan the write_buffer |
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388 | for (num_write_buffer = 0; num_write_buffer < write_buffer->nb_slot_use(); num_write_buffer ++) |
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389 | { |
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390 | slot_t<write_buffer_t> val = write_buffer->read(num_write_buffer); |
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391 | |
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392 | if ( (val.data.trdid == trdid ) && |
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393 | (val.data.address.tag == address.tag ) && |
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394 | (val.data.address.familly == address.familly)) |
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395 | break; |
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396 | } |
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397 | |
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398 | return num_write_buffer; |
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399 | } |
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400 | |
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401 | //*****[ hit_access_port ]***** |
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402 | // return the number of associativity if hit |
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403 | // return nb_accosiativity if miss |
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404 | public : uint32_t hit_cache (uint32_t trdid, address_t address) |
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405 | { |
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406 | uint32_t num_associativity; |
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407 | for (num_associativity = 0; num_associativity < associativity; num_associativity ++) |
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408 | // Hit if : |
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409 | // * in the line |
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410 | // * in a way associative |
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411 | // -> there are the same tag |
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412 | // the same trdid |
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413 | // is valid |
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414 | if ( (tag [address.familly][num_associativity].address == address.tag) && |
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415 | (tag [address.familly][num_associativity].valid == true ) && |
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416 | (tag [address.familly][num_associativity].trdid == trdid ) ) |
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417 | break; |
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418 | |
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419 | return num_associativity; |
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420 | } |
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421 | |
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422 | //*****[ hit_access_port ]***** |
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423 | // Return the number of port if hit |
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424 | // Return nb_port if miss |
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425 | public : uint32_t hit_access_port (uint32_t trdid, address_t address) |
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426 | { |
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427 | uint32_t it_num_port = 0; |
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428 | |
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429 | // scan all port - test if have a transaction |
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430 | for (it_num_port = 0; it_num_port < nb_port; it_num_port ++) |
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431 | if ( (access_port[it_num_port].valid == true ) && |
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432 | (access_port[it_num_port].trdid == trdid ) && |
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433 | (access_port[it_num_port].address.tag == address.tag ) && |
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434 | (access_port[it_num_port].address.familly == address.familly)) |
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435 | break; |
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436 | |
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437 | return it_num_port; |
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438 | } |
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439 | |
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440 | //*****[ need_slot ]***** |
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441 | public : uint32_t need_slot () |
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442 | { |
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443 | uint32_t res = 0; |
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444 | // scan all port - test if have a transaction |
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445 | for (uint32_t x = 0; x < nb_port; x ++) |
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446 | if (access_port[x].valid == true) |
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447 | res ++; |
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448 | |
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449 | return res; |
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450 | } |
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451 | |
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452 | //*****[ latence ]***** |
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453 | // Return the time to have the data |
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454 | // uncache is to stocke the address on the cache |
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455 | public : uint32_t latence (uint32_t num_port) |
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456 | { |
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457 | uint32_t res = hit_latence + access_port[num_port].latence; |
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458 | |
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459 | return res; |
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460 | } |
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461 | |
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462 | //*****[ update_latence ]***** |
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463 | // Return the time to have the data |
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464 | // uncache is to stocke the address on the cache |
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465 | public : bool update_latence (uint32_t nb_port, uint32_t latence) |
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466 | { |
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467 | access_port[nb_port].latence = latence-hit_latence; |
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468 | return access_port[nb_port].valid; |
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469 | } |
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470 | |
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471 | //*****[ information ]***** |
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472 | public : void information (void) |
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473 | { |
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474 | cout << "<" << name << ">" << endl |
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475 | << " * Information" << endl |
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476 | << " * Capacity : " << nb_line * size_line * size_word << " bytes" << endl |
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477 | << " * Nb line : " << nb_line << endl |
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478 | << " * Size line : " << size_line << endl |
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479 | << " * Size word : " << size_word << endl |
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480 | << " * Associativity : " << associativity << endl |
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481 | << " * Timing : " << endl |
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482 | << " * Hit latence : " << hit_latence << endl |
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483 | << " * Miss penality : " << miss_penality << endl |
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484 | << " * Nb port : " << nb_port << endl |
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485 | << endl; |
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486 | } |
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487 | |
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488 | friend ostream& operator<< (ostream& output_stream, const Cache_OneLevel & x) |
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489 | { |
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490 | output_stream << "<" << x.name << ">" << endl |
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491 | << " * Capacity : " << x.nb_line * x.size_line * x.size_word << " bytes" << endl |
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492 | << " * Nb line : " << x.nb_line << endl |
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493 | << " * Size line : " << x.size_line << endl |
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494 | << " * Size word : " << x.size_word << endl |
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495 | << " * Associativity : " << x.associativity << endl |
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496 | << " * Timing : " << endl |
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497 | << " * Hit latence : " << x.hit_latence << endl |
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498 | << " * Miss penality : " << x.miss_penality << endl |
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499 | << " * Nb port : " << x.nb_port << endl |
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500 | << endl; |
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501 | |
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502 | output_stream << " * Tag" << endl; |
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503 | for (uint32_t i = 0; i < x.nb_line / x.associativity; i ++) |
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504 | { |
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505 | for (uint32_t j = 0; j < x.associativity; j ++) |
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506 | output_stream << x.tag [i][j] << " | "; |
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507 | output_stream << endl; |
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508 | } |
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509 | |
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510 | output_stream << endl; |
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511 | output_stream << *x.write_buffer << endl; |
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512 | |
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513 | return output_stream; |
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514 | } |
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515 | |
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516 | }; |
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517 | };};};}; |
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518 | #endif //!CACHE_ONELEVEL_H |
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519 | |
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