source: trunk/IPs/systemC/hierarchy_memory/cache/main.cpp@ 20

Last change on this file since 20 was 2, checked in by kane, 20 years ago

Import Morpheo
File size: 27.9 KB
Line 
1#include "cache.h"
2#include "type_req_cache.h"
3#include <iostream>
4using namespace hierarchy_memory;
5using namespace hierarchy_memory::cache;
6using namespace std;
7
8//-----[ Routine de test ]---------------------------------------
9
10void test_ko (char * file, uint32_t line)
11{
12 cerr << "***** Test KO *****" << endl
13 << " - File : " << file << endl
14 << " - Line : " << line << endl;
15 exit (line);
16};
17
18void test_ok ()
19{
20 cout << "***** Test OK *****" << endl;
21 exit (0);
22};
23
24template <class T>
25void test(T exp1, T exp2, char * file, uint32_t line)
26{
27 if (exp1 != exp2)
28 {
29 cerr << "Expression is different : " << endl
30 << " - exp1 : " << exp1 << endl
31 << " - exp2 : " << exp2 << endl;
32
33 test_ko (file,line);
34 }
35};
36
37#define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0)
38
39//-----[ main ]--------------------------------------------------
40int main ()
41{
42 cout << "<main> Begin" << endl;
43
44 // name , nb_line, size_line, size_word, associativity, hit_latence, miss_penality
45#define L1a_CACHE "L1a_CACHE", 4, 2, 4, 4, 1, 5
46#define L1b_CACHE "L1b_CACHE", 4, 4, 4, 2, 2, 4
47#define L1c_CACHE "L1c_CACHE", 4, 2, 4, 1, 1, 6
48#define L1d_CACHE "L1d_CACHE", 4, 2, 4, 4, 2, 3
49#define L2_CACHE "L2_CACHE" , 8, 4, 4, 2, 2, 8
50#define L3_CACHE "L3_CACHE" , 16, 8, 4, 1, 3, 15
51
52 cout << " * 3 caches" << endl;
53 cout << " * L1 : 4 lines - 2 words - associtivity 4 ways" << endl;
54 cout << " * L2 : 8 lines - 4 words - associtivity 2 ways" << endl;
55 cout << " * L3 : 16 lines - 8 words - associtivity 1 ways" << endl;
56
57 {
58 const uint32_t NB_CACHE = 2;
59 const uint32_t NB_PORT = 3;
60
61 cout << "<main> Test de \"Cache_Multilevel\"" << endl;
62
63 param_cache_t param_cache [NB_CACHE] = { param_cache_t (L1a_CACHE) ,
64 param_cache_t (L2_CACHE) };
65 Cache_Multilevel my_cache (cache_multilevel::param_t("my_cache_multilevel",NB_CACHE, NB_PORT, param_cache));
66
67 my_cache.reset();
68
69 cout << "**************************************" << endl;
70 cout << "********** TRANSITION [ 0] **********" << endl;
71 cout << "**************************************" << endl;
72 my_cache.transition();
73 //cout << my_cache << endl;
74
75 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
76 for (uint32_t i = 0; i < NB_PORT; i ++)
77 {
78 uint address = 0x100+i*4;
79 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
80 }
81
82 cout << "**************************************" << endl;
83 cout << "********** TRANSITION [ 1] **********" << endl;
84 cout << "**************************************" << endl;
85 my_cache.transition();
86 //cout << my_cache << endl;
87
88 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
89
90 for (uint32_t i = 0; i < NB_PORT; i ++)
91 {
92 uint address = 0x100+i*4;
93 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),15);
94 }
95
96 cout << "**************************************" << endl;
97 cout << "********** TRANSITION [ 2] **********" << endl;
98 cout << "**************************************" << endl;
99 my_cache.transition();
100 //cout << my_cache << endl;
101
102 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
103
104 for (uint32_t i = 0; i < NB_PORT; i ++)
105 {
106 uint address = 0x100+i*4;
107 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),14);
108 }
109
110 cout << "**************************************" << endl;
111 cout << "********** TRANSITION [ 3] **********" << endl;
112 cout << "**************************************" << endl;
113 my_cache.transition();
114 //cout << my_cache << endl;
115
116 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
117
118 for (uint32_t i = 0; i < NB_PORT; i ++)
119 {
120 uint address = 0x200+i*4;
121 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
122 }
123
124 cout << "**************************************" << endl;
125 cout << "********** TRANSITION [ 4] **********" << endl;
126 cout << "**************************************" << endl;
127 my_cache.transition();
128 //cout << my_cache << endl;
129
130 cout << "**************************************" << endl;
131 cout << "********** TRANSITION [ 5] **********" << endl;
132 cout << "**************************************" << endl;
133 my_cache.transition();
134 //cout << my_cache << endl;
135
136 cout << "**************************************" << endl;
137 cout << "********** TRANSITION [ 6] **********" << endl;
138 cout << "**************************************" << endl;
139 my_cache.transition();
140 //cout << my_cache << endl;
141
142 cout << "**************************************" << endl;
143 cout << "********** TRANSITION [ 7] **********" << endl;
144 cout << "**************************************" << endl;
145 my_cache.transition();
146 //cout << my_cache << endl;
147
148 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
149
150 for (uint32_t i = 0; i < NB_PORT; i ++)
151 {
152 uint address = 0x100+i*4;
153 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),9);
154 }
155
156 cout << "**************************************" << endl;
157 cout << "********** TRANSITION [ 8] **********" << endl;
158 cout << "**************************************" << endl;
159 my_cache.transition();
160 //cout << my_cache << endl;
161
162 cout << "**************************************" << endl;
163 cout << "********** TRANSITION [ 9] **********" << endl;
164 cout << "**************************************" << endl;
165 my_cache.transition();
166 //cout << my_cache << endl;
167
168 cout << "**************************************" << endl;
169 cout << "********** TRANSITION [ 10] **********" << endl;
170 cout << "**************************************" << endl;
171 my_cache.transition();
172 //cout << my_cache << endl;
173
174 cout << "**************************************" << endl;
175 cout << "********** TRANSITION [ 11] **********" << endl;
176 cout << "**************************************" << endl;
177 my_cache.transition();
178 //cout << my_cache << endl;
179
180 cout << "**************************************" << endl;
181 cout << "********** TRANSITION [ 12] **********" << endl;
182 cout << "**************************************" << endl;
183 my_cache.transition();
184 //cout << my_cache << endl;
185
186 cout << "**************************************" << endl;
187 cout << "********** TRANSITION [ 13] **********" << endl;
188 cout << "**************************************" << endl;
189 my_cache.transition();
190 //cout << my_cache << endl;
191
192 cout << "**************************************" << endl;
193 cout << "********** TRANSITION [ 14] **********" << endl;
194 cout << "**************************************" << endl;
195 my_cache.transition();
196 //cout << my_cache << endl;
197
198 cout << "**************************************" << endl;
199 cout << "********** TRANSITION [ 15] **********" << endl;
200 cout << "**************************************" << endl;
201 my_cache.transition();
202 //cout << my_cache << endl;
203
204 cout << "**************************************" << endl;
205 cout << "********** TRANSITION [ 16] **********" << endl;
206 cout << "**************************************" << endl;
207 my_cache.transition();
208 //cout << my_cache << endl;
209
210 cout << "**************************************" << endl;
211 cout << "********** TRANSITION [ 17] **********" << endl;
212 cout << "**************************************" << endl;
213 my_cache.transition();
214 //cout << my_cache << endl;
215
216 cout << "**************************************" << endl;
217 cout << "********** TRANSITION [ 18] **********" << endl;
218 cout << "**************************************" << endl;
219 my_cache.transition();
220 //cout << my_cache << endl;
221
222 cout << "**************************************" << endl;
223 cout << "********** TRANSITION [ 19] **********" << endl;
224 cout << "**************************************" << endl;
225 my_cache.transition();
226 //cout << my_cache << endl;
227
228 cout << "**************************************" << endl;
229 cout << "********** TRANSITION [ 20] **********" << endl;
230 cout << "**************************************" << endl;
231 my_cache.transition();
232 //cout << my_cache << endl;
233
234 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
235
236 for (uint32_t i = 0; i < NB_PORT; i ++)
237 {
238 uint address = 0x100+i*4;
239 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1);
240 }
241
242 cout << "**************************************" << endl;
243 cout << "********** TRANSITION [ 21] **********" << endl;
244 cout << "**************************************" << endl;
245 my_cache.transition();
246 //cout << my_cache << endl;
247
248 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
249
250 for (uint32_t i = 0; i < NB_PORT; i ++)
251 {
252 uint address = 0x200+i*4;
253 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),1);
254 }
255
256 cout << "**************************************" << endl;
257 cout << "********** TRANSITION [ 22] **********" << endl;
258 cout << "**************************************" << endl;
259 my_cache.transition();
260 //cout << my_cache << endl;
261
262 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
263
264 for (uint32_t i = 0; i < NB_PORT; i ++)
265 {
266 uint address = 0x300+i*4;
267 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
268 }
269
270 cout << "**************************************" << endl;
271 cout << "********** TRANSITION [ 23] **********" << endl;
272 cout << "**************************************" << endl;
273 my_cache.transition();
274 //cout << my_cache << endl;
275
276 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
277
278 for (uint32_t i = 0; i < NB_PORT; i ++)
279 {
280 uint address = 0x400+i*4;
281 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
282 }
283
284 cout << "**************************************" << endl;
285 cout << "********** TRANSITION [ 24] **********" << endl;
286 cout << "**************************************" << endl;
287 my_cache.transition();
288 //cout << my_cache << endl;
289
290 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
291
292 for (uint32_t i = 0; i < NB_PORT; i ++)
293 {
294 uint address = 0x500+i*4;
295 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),(uint32_t)16);
296 }
297
298 cout << "**************************************" << endl;
299 cout << "********** TRANSITION [+40] **********" << endl;
300 cout << "**************************************" << endl;
301 for (uint32_t it = 24; it < 40; it ++)
302 {
303 cout << it << endl;
304 my_cache.transition();
305 }
306
307 cout << "**************************************" << endl;
308 cout << "********** TRANSITION [ 40] **********" << endl;
309 cout << "**************************************" << endl;
310 my_cache.transition();
311 cout << my_cache << endl;
312
313 cout << "***** Read of " << NB_PORT << " consecutive address *****" << endl;
314
315 for (uint32_t i = 0; i < NB_PORT; i ++)
316 {
317 uint address = 0x100+i*4;
318 TEST(uint32_t, my_cache.latence (i,address,0,CACHED,READ),16);
319 }
320
321 }//end test Cache_Multilevel
322
323 cout << "-------------------------------------------------------------------------" << endl;
324 cout << "-------------------------------------------------------------------------" << endl;
325 cout << "-------------------------------------------------------------------------" << endl;
326
327 {
328 const uint32_t nb_entity = 2;
329 const uint32_t nb_iport = 3;
330 const uint32_t nb_dport = 2;
331
332 cout << "<main> Test de \"Cache\"" << endl;
333
334 param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) };
335 param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) };
336 param_cache_t param_cache_1c [1] = { param_cache_t (L1c_CACHE) };
337 param_cache_t param_cache_1d [1] = { param_cache_t (L1d_CACHE) };
338 param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) ,
339 param_cache_t (L3_CACHE) };
340
341 cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a),
342 cache_multilevel::param_t ("param_icache_dedicated[1]",1,nb_iport,param_cache_1b)};
343
344 cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1c),
345 cache_multilevel::param_t ("param_dcache_dedicated[1]",1,nb_dport,param_cache_1d)};
346
347 cache_multilevel::param_t param_cache_shared ("param_cache_shared", 2, nb_entity*(nb_iport+nb_dport), param_cache_2);
348
349 cache::param_t param_cache ("cache" ,
350 nb_entity ,
351 param_icache_dedicated ,
352 param_dcache_dedicated ,
353 param_cache_shared );
354
355 Cache my_cache (param_cache);
356
357 ////cout << my_cache << endl;
358 my_cache.reset();
359
360 cout << "**************************************" << endl;
361 cout << "********** TRANSITION [ 0] **********" << endl;
362 cout << "**************************************" << endl;
363 my_cache.transition();
364 //cout << my_cache << endl;
365
366 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
367 for (uint32_t i = 0; i < nb_iport; i ++)
368 {
369 uint address = 0x100+i*4;
370 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34);
371 }
372
373 cout << "**************************************" << endl;
374 cout << "********** TRANSITION [ 1] **********" << endl;
375 cout << "**************************************" << endl;
376 my_cache.transition();
377 // cout << my_cache << endl;
378
379 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
380 for (uint32_t i = 0; i < nb_iport; i ++)
381 {
382 uint address = 0x200+i*4;
383 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),34);
384 }
385
386 cout << "**************************************" << endl;
387 cout << "********** TRANSITION [ 2] **********" << endl;
388 cout << "**************************************" << endl;
389 my_cache.transition();
390 //cout << my_cache << endl;
391
392 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
393 for (uint32_t i = 0; i < nb_iport; i ++)
394 {
395 uint address = 0x300+i*4;
396 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),(uint32_t)34);
397 }
398
399 cout << "**************************************" << endl;
400 cout << "********** TRANSITION [ 3] **********" << endl;
401 cout << "**************************************" << endl;
402 my_cache.transition();
403 cout << my_cache << endl;
404
405 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
406 for (uint32_t i = 0; i < nb_iport; i ++)
407 {
408 uint address = 0x100+i*4;
409 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ),31);
410 }
411
412 //cout << my_cache << endl;
413
414 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
415 for (uint32_t i = 0; i < nb_dport; i ++)
416 {
417 uint address = 0x100+i*4;
418 TEST(uint32_t, my_cache.latence (DATA_CACHE,1,i,address,0,CACHED,READ),30); // miss penality is 3
419 }
420
421 //cout << my_cache << endl;
422
423 cout << "**************************************" << endl;
424 cout << "********** TRANSITION [ 4] **********" << endl;
425 cout << "**************************************" << endl;
426 my_cache.transition();
427 cout << my_cache << endl;
428
429 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
430 for (uint32_t i = 0; i < nb_iport; i ++)
431 {
432 uint address = 0x100+i*4;
433 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,1,CACHED,READ),(uint32_t)34);
434 }
435
436 cout << "**************************************" << endl;
437 cout << "********** TRANSITION [+34] **********" << endl;
438 cout << "**************************************" << endl;
439 for (uint32_t it = 0; it < 30; it ++)
440 {
441 cout << it << endl;
442 my_cache.transition();
443 if (it == 0)
444 cout << my_cache << endl;
445
446 }
447
448 cout << "**************************************" << endl;
449 cout << "********** TRANSITION [ 34] **********" << endl;
450 cout << "**************************************" << endl;
451 my_cache.transition();
452 cout << my_cache << endl;
453
454 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
455 for (uint32_t i = 0; i < nb_iport; i ++)
456 {
457 uint address = 0x200+i*4;
458 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,1,i,address,0,CACHED,READ), 2);
459 }
460
461 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
462 for (uint32_t i = 0; i < nb_dport; i ++)
463 {
464 uint address = 0x200+i*4;
465 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,0,CACHED,READ),20); // Miss L1-L2 Hit L3
466 }
467
468
469 }//end test Cache
470
471 cout << "-------------------------------------------------------------------------" << endl;
472 cout << "-------------------------------------------------------------------------" << endl;
473 cout << "-------------------------------------------------------------------------" << endl;
474
475
476 {
477 const uint32_t nb_entity = 1;
478 const uint32_t nb_iport = 3;
479 const uint32_t nb_dport = 2;
480
481 cout << "<main> Test de \"Cache\"" << endl;
482
483 param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) };
484 param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) };
485
486 cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)};
487
488 cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)};
489
490 cache_multilevel::param_t param_cache_shared ("param_cache_shared",0, 0, NULL);
491
492 cache::param_t param_cache ("cache" ,
493 nb_entity ,
494 param_icache_dedicated ,
495 param_dcache_dedicated ,
496 param_cache_shared );
497
498 Cache my_cache (param_cache);
499
500 cout << my_cache << endl;
501
502 my_cache.reset();
503
504 cout << "**************************************" << endl;
505 cout << "********** TRANSITION [ 0] **********" << endl;
506 cout << "**************************************" << endl;
507 my_cache.transition();
508 //cout << my_cache << endl;
509
510 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
511 for (uint32_t i = 0; i < nb_iport; i ++)
512 {
513 uint address = 0x100+i*4;
514 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
515 }
516
517 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
518 for (uint32_t i = 0; i < nb_dport; i ++)
519 {
520 uint address = 0x100+i*4;
521 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
522 }
523
524 cout << "**************************************" << endl;
525 cout << "********** TRANSITION [ 1] **********" << endl;
526 cout << "**************************************" << endl;
527 my_cache.transition();
528 //cout << my_cache << endl;
529
530 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
531 for (uint32_t i = 0; i < nb_iport; i ++)
532 {
533 uint address = 0x100+i*4;
534 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)5);
535 }
536
537
538 }
539
540 {
541 const uint32_t nb_entity = 1;
542 const uint32_t nb_iport = 3;
543 const uint32_t nb_dport = 2;
544
545 cout << "<main> Test de \"Cache\"" << endl;
546
547 param_cache_t param_cache_2 [1] = { param_cache_t (L2_CACHE)};
548
549 cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",0,nb_iport,NULL)};
550
551 cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",0,nb_dport,NULL)};
552
553 cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, nb_entity * (nb_iport + nb_dport), param_cache_2);
554
555 cache::param_t param_cache ("cache" ,
556 nb_entity ,
557 param_icache_dedicated ,
558 param_dcache_dedicated ,
559 param_cache_shared );
560
561 Cache my_cache (param_cache);
562
563 cout << my_cache << endl;
564
565 my_cache.reset();
566
567 cout << "**************************************" << endl;
568 cout << "********** TRANSITION [ 0] **********" << endl;
569 cout << "**************************************" << endl;
570 my_cache.transition();
571 //cout << my_cache << endl;
572
573 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
574 for (uint32_t i = 0; i < nb_iport; i ++)
575 {
576 uint address = 0x100+i*4;
577 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)10);
578 }
579
580 cout << "**************************************" << endl;
581 cout << "********** TRANSITION [ 1] **********" << endl;
582 cout << "**************************************" << endl;
583 my_cache.transition();
584 //cout << my_cache << endl;
585
586 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
587 for (uint32_t i = 0; i < nb_iport; i ++)
588 {
589 uint address = 0x100+i*4;
590 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9);
591 }
592
593 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
594 for (uint32_t i = 0; i < nb_dport; i ++)
595 {
596 uint address = 0x100+i*4;
597 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)9);
598 }
599
600
601 }
602
603 cout << "-------------------------------------------------------------------------" << endl;
604 cout << "-------------------------------------------------------------------------" << endl;
605 cout << "-------------------------------------------------------------------------" << endl;
606
607 {
608 const uint32_t nb_entity = 1;
609 const uint32_t nb_iport = 3;
610 const uint32_t nb_dport = 2;
611
612 cout << "<main> Test des Types et direction" << endl;
613
614 param_cache_t param_cache_1a [1] = { param_cache_t (L1a_CACHE) };
615 param_cache_t param_cache_1b [1] = { param_cache_t (L1b_CACHE) };
616 param_cache_t param_cache_2 [1] = { param_cache_t (L2_CACHE) };
617
618 cache_multilevel::param_t param_icache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_icache_dedicated[0]",1,nb_iport,param_cache_1a)};
619 cache_multilevel::param_t param_dcache_dedicated [nb_entity] = {cache_multilevel::param_t ("param_dcache_dedicated[0]",1,nb_dport,param_cache_1b)};
620 cache_multilevel::param_t param_cache_shared ("param_cache_shared",1, nb_entity*(nb_iport+nb_dport), param_cache_2);
621
622 cache::param_t param_cache ("cache" ,
623 nb_entity ,
624 param_icache_dedicated ,
625 param_dcache_dedicated ,
626 param_cache_shared );
627
628 Cache my_cache (param_cache);
629
630 // cout << my_cache << endl;
631 my_cache.reset();
632
633
634 cout << "**************************************" << endl;
635 cout << "********** TRANSITION [ 0] **********" << endl;
636 cout << "**************************************" << endl;
637 my_cache.transition();
638 //cout << my_cache << endl;
639
640 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
641 for (uint32_t i = 0; i < nb_iport; i ++)
642 {
643 uint address = 0x100+i*4;
644 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16);
645 }
646
647 cout << "**************************************" << endl;
648 cout << "********** TRANSITION [+ 9] **********" << endl;
649 cout << "**************************************" << endl;
650 for (uint32_t it = 1; it < 9; it ++)
651 {
652 cout << it << endl;
653 my_cache.transition();
654 }
655
656 cout << "**************************************" << endl;
657 cout << "********** TRANSITION [ 9] **********" << endl;
658 cout << "**************************************" << endl;
659 my_cache.transition();
660 cout << my_cache << endl;
661
662 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
663 for (uint32_t i = 0; i < nb_iport; i ++)
664 {
665 uint address = 0x200+i*4;
666 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)16);
667 }
668
669 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
670 for (uint32_t i = 0; i < nb_dport; i ++)
671 {
672 uint address = 0x100+i*4;
673 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8);
674 }
675
676 cout << "**************************************" << endl;
677 cout << "********** TRANSITION [ 5] **********" << endl;
678 cout << "**************************************" << endl;
679 my_cache.transition();
680// cout << my_cache << endl;
681
682 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
683 for (uint32_t i = 0; i < nb_iport; i ++)
684 {
685 uint address = 0x100+i*4;
686 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)6);
687 }
688
689 cout << "**************************************" << endl;
690 cout << "********** TRANSITION [ 6] **********" << endl;
691 cout << "**************************************" << endl;
692 my_cache.transition();
693// cout << my_cache << endl;
694
695 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
696 for (uint32_t i = 0; i < nb_iport; i ++)
697 {
698 uint address = 0x100+i*4;
699 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,UNCACHED,READ),(uint32_t)16);
700 }
701
702 cout << "**************************************" << endl;
703 cout << "********** TRANSITION [ 7] **********" << endl;
704 cout << "**************************************" << endl;
705 my_cache.transition();
706// cout << my_cache << endl;
707
708 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
709 for (uint32_t i = 0; i < nb_iport; i ++)
710 {
711 uint address = 0x100+i*4;
712 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)4);
713 }
714
715 cout << "**************************************" << endl;
716 cout << "********** TRANSITION [+18] **********" << endl;
717 cout << "**************************************" << endl;
718 for (uint32_t it = 8; it < 18; it ++)
719 {
720 cout << it << endl;
721 my_cache.transition();
722 }
723
724 cout << "**************************************" << endl;
725 cout << "********** TRANSITION [ 18] **********" << endl;
726 cout << "**************************************" << endl;
727 my_cache.transition();
728// cout << my_cache << endl;
729
730 cout << "***** Read of " << nb_iport << " consecutive address *****" << endl;
731 for (uint32_t i = 0; i < nb_iport; i ++)
732 {
733 uint address = 0x100+i*4;
734 TEST(uint32_t, my_cache.latence (INSTRUCTION_CACHE,0,i,address,1,CACHED,READ),(uint32_t)1);
735 }
736
737 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
738 for (uint32_t i = 0; i < nb_dport; i ++)
739 {
740 uint address = 0x200+i*4;
741 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)8);
742 }
743
744 cout << "**************************************" << endl;
745 cout << "********** TRANSITION [ 19] **********" << endl;
746 cout << "**************************************" << endl;
747 my_cache.transition();
748// cout << my_cache << endl;
749
750 cout << "***** Read of " << nb_dport << " consecutive address *****" << endl;
751 for (uint32_t i = 0; i < nb_dport; i ++)
752 {
753 uint address = 0x200+i;
754 TEST(uint32_t, my_cache.latence (DATA_CACHE,0,i,address,1,CACHED,READ),(uint32_t)7);
755 }
756
757 }
758
759 test_ok ();
760}//end main
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