1 | #ifndef HIERARCHY_MEMORY_H |
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2 | #define HIERARCHY_MEMORY_H |
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3 | #include <iostream> |
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4 | #include <stdint.h> |
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5 | #include <stdarg.h> |
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6 | |
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7 | #include <systemc.h> |
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8 | #include "shared/soclib_segment_table.h" |
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9 | #include "shared/soclib_caches_interfaces.h" |
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10 | |
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11 | #include "hierarchy_memory/data/data.h" |
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12 | #include "hierarchy_memory/file/sort_file.h" |
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13 | #include "hierarchy_memory/file/entry.h" |
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14 | #include "hierarchy_memory/cache/cache.h" |
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15 | #include "hierarchy_memory/ramlock/ramlock.h" |
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16 | #include "hierarchy_memory/tty/tty.h" |
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17 | #include "hierarchy_memory/sim2os/sim2os.h" |
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18 | |
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19 | #include "hierarchy_memory/cache/type_req_cache.h" |
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20 | |
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21 | using namespace std; |
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22 | using namespace hierarchy_memory::data; |
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23 | using namespace hierarchy_memory::sort_file; |
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24 | using namespace hierarchy_memory::cache; |
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25 | using namespace hierarchy_memory::ramlock; |
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26 | using namespace hierarchy_memory::tty; |
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27 | using namespace hierarchy_memory::sim2os; |
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28 | |
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29 | namespace hierarchy_memory |
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30 | { |
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31 | template <class T> |
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32 | class param_entity_t |
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33 | { |
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34 | public : uint32_t address ; |
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35 | public : uint32_t size ; |
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36 | public : T param ; |
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37 | |
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38 | public : param_entity_t () {}; |
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39 | |
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40 | public : param_entity_t (uint32_t address , |
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41 | uint32_t size , |
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42 | T param ) |
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43 | { |
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44 | this->address = address ; |
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45 | this->size = size ; |
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46 | this->param = param ; |
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47 | } |
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48 | };//end param_entity_t |
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49 | |
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50 | class param_t |
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51 | { |
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52 | public : uint32_t nb_entity_tty; |
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53 | public : param_entity_t <tty::param_t> * param_tty; |
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54 | public : uint32_t nb_entity_ramlock; |
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55 | public : param_entity_t <ramlock::param_t> * param_ramlock; |
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56 | public : param_entity_t <sim2os::param_t> param_sim2os; |
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57 | public : cache::param_t param_cache; |
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58 | |
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59 | public : param_t () {}; |
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60 | |
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61 | public : param_t (uint32_t nb_entity_tty , |
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62 | param_entity_t <tty::param_t> * param_tty , |
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63 | uint32_t nb_entity_ramlock , |
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64 | param_entity_t <ramlock::param_t> * param_ramlock , |
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65 | param_entity_t <sim2os::param_t> param_sim2os , |
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66 | cache::param_t param_cache) |
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67 | { |
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68 | this->nb_entity_tty = nb_entity_tty; |
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69 | this->param_tty = param_tty; |
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70 | this->nb_entity_ramlock = nb_entity_ramlock; |
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71 | this->param_ramlock = param_ramlock; |
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72 | this->param_sim2os = param_sim2os; |
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73 | this->param_cache = param_cache; |
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74 | } |
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75 | };//end param_t |
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76 | |
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77 | template<uint32_t SIZE_TRDID , |
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78 | uint32_t SIZE_IPKTID , |
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79 | uint32_t SIZE_IADDR , |
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80 | uint32_t SIZE_IDATA , |
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81 | uint32_t NB_IWORD , |
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82 | uint32_t SIZE_DPKTID , |
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83 | uint32_t SIZE_DADDR , |
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84 | uint32_t SIZE_DDATA |
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85 | > |
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86 | |
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87 | class HIERARCHY_MEMORY : sc_module |
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88 | { |
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89 | //--------------------------------------------------------------------------------------------- |
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90 | //-----[ PORT ]-------------------------------------------------------------------------------- |
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91 | //--------------------------------------------------------------------------------------------- |
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92 | |
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93 | public : sc_in_clk CLK; |
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94 | public : sc_in<bool> NRESET; |
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95 | public : ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> ** ICACHE; |
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96 | public : DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA> ** DCACHE; |
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97 | |
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98 | //--------------------------------------------------------------------------------------------- |
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99 | //-----[ INTERNAL SIGNAL ]--------------------------------------------------------------------- |
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100 | //--------------------------------------------------------------------------------------------- |
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101 | private: bool ** irsp_val; |
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102 | private: bool ** drsp_val; |
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103 | |
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104 | private: bool ** ireq_ack; |
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105 | private: bool ** dreq_ack; |
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106 | |
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107 | //--------------------------------------------------------------------------------------------- |
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108 | //-----[ COMPONENT ]--------------------------------------------------------------------------- |
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109 | //--------------------------------------------------------------------------------------------- |
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110 | private: Data * component_data; |
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111 | private: Sort_File<Entry> ** component_buffer_irsp; |
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112 | private: Sort_File<Entry> ** component_buffer_drsp; |
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113 | |
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114 | private: Sim2os * component_sim2os; |
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115 | private: Tty ** component_tty; |
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116 | private: Ramlock ** component_ramlock; |
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117 | |
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118 | private: Cache * component_cache; |
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119 | //--------------------------------------------------------------------------------------------- |
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120 | //-----[ VARIABLE ] --------------------------------------------------------------------------- |
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121 | //--------------------------------------------------------------------------------------------- |
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122 | |
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123 | private: char * NAME; // instance name |
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124 | private: uint32_t * nb_iport; |
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125 | private: uint32_t * nb_dport; |
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126 | private: const uint32_t nb_context; |
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127 | private: const uint32_t nb_entity; |
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128 | private: const uint32_t nb_entity_tty; |
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129 | private: const uint32_t nb_entity_ramlock; |
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130 | |
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131 | private: char ** read_iram; |
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132 | private: char * read_dram; |
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133 | private: char * write_dram; |
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134 | |
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135 | private: bool * context_stop; // to determine which context have send the signal stop (a same thread can send many signal) |
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136 | private: uint32_t nb_context_stop; // stop the simulation when all context have send the stop signal |
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137 | //--------------------------------------------------------------------------------------------- |
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138 | //-----[ CONSTRUCTOR ]------------------------------------------------------------------------- |
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139 | //--------------------------------------------------------------------------------------------- |
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140 | SC_HAS_PROCESS(HIERARCHY_MEMORY); |
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141 | |
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142 | public : HIERARCHY_MEMORY (// Fixe parameter |
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143 | sc_module_name insname , |
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144 | uint32_t globalIndex , // VCI target index |
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145 | uint32_t localIndex , |
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146 | SOCLIB_SEGMENT_TABLE * segtab , // segment table pointer |
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147 | // variable parameter |
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148 | uint32_t nb_entity , |
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149 | uint32_t nb_context , |
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150 | //*****[ buffer respons ]***** |
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151 | uint32_t size_buffer_irsp , |
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152 | uint32_t size_buffer_drsp , |
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153 | //*****[ entity_param ]***** |
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154 | param_t param |
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155 | ): |
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156 | nb_context (nb_context ), |
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157 | nb_entity (nb_entity ), |
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158 | nb_entity_tty (param.nb_entity_tty ), |
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159 | nb_entity_ramlock (param.nb_entity_ramlock) |
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160 | { |
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161 | uint32_t size_name = strlen(insname)+1; |
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162 | NAME = new char [size_name]; |
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163 | strncpy(NAME,insname,size_name); |
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164 | |
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165 | // *****[ Signal creation ]***** |
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166 | ICACHE = new ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> * [nb_entity]; |
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167 | DCACHE = new DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA> * [nb_entity]; |
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168 | |
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169 | nb_iport = new uint32_t [nb_entity]; |
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170 | nb_dport = new uint32_t [nb_entity]; |
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171 | |
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172 | irsp_val = new bool * [nb_entity]; |
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173 | drsp_val = new bool * [nb_entity]; |
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174 | |
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175 | ireq_ack = new bool * [nb_entity]; |
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176 | dreq_ack = new bool * [nb_entity]; |
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177 | |
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178 | for (uint32_t it = 0; it < nb_entity; it++) |
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179 | { |
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180 | nb_iport [it] = param.param_cache.param_icache_dedicated [it].nb_port; |
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181 | nb_dport [it] = param.param_cache.param_dcache_dedicated [it].nb_port; |
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182 | |
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183 | irsp_val [it] = new bool [nb_iport[it]]; |
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184 | drsp_val [it] = new bool [nb_dport[it]]; |
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185 | |
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186 | ireq_ack [it] = new bool [nb_iport[it]]; |
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187 | dreq_ack [it] = new bool [nb_dport[it]]; |
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188 | |
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189 | ICACHE [it] = new ICACHE_CACHE_PORTS<SIZE_TRDID, SIZE_IPKTID, SIZE_IADDR, SIZE_IDATA, NB_IWORD> [nb_iport [it]]; |
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190 | DCACHE [it] = new DCACHE_CACHE_PORTS<SIZE_TRDID, SIZE_DPKTID, SIZE_DADDR, SIZE_DDATA> [nb_dport [it]]; |
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191 | } |
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192 | |
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193 | read_iram = new char * [NB_IWORD]; |
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194 | for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++) |
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195 | read_iram [num_word] = new char [SIZE_IDATA/8]; |
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196 | |
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197 | read_dram = new char [SIZE_DDATA/8]; |
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198 | write_dram = new char [SIZE_DDATA/8]; |
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199 | |
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200 | // *****[ Create internal structure ]***** |
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201 | |
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202 | component_data = new Data (data::param_t("component_data", 16, globalIndex, localIndex, segtab)); |
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203 | component_buffer_irsp = new Sort_File<Entry> * [nb_entity]; |
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204 | component_buffer_drsp = new Sort_File<Entry> * [nb_entity]; |
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205 | |
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206 | for (uint32_t it = 0; it < nb_entity; it++) |
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207 | { |
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208 | char name [100]; |
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209 | sprintf(name,"component_buffer_irsp[%d]",it); |
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210 | component_buffer_irsp [it] = new Sort_File<Entry> (sort_file::param_t(name,size_buffer_irsp)); |
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211 | sprintf(name,"component_buffer_drsp[%d]",it); |
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212 | component_buffer_drsp [it] = new Sort_File<Entry> (sort_file::param_t(name,size_buffer_drsp)); |
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213 | |
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214 | } |
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215 | |
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216 | component_cache = new Cache (param.param_cache); |
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217 | component_tty = new Tty * [nb_entity_tty ]; |
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218 | component_ramlock = new Ramlock * [nb_entity_ramlock]; |
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219 | |
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220 | for (uint32_t it = 0; it < nb_entity_tty ; it++) |
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221 | { |
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222 | component_tty [it] = new Tty (param.param_tty[it] .param); |
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223 | entity_t entity = component_data->entity(param.param_tty[it].address, param.param_tty[it].size); |
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224 | |
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225 | if (entity.present == false) |
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226 | { |
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227 | cerr << "<HIERARCHY_MEMORY> the tty [" << it << "] have not a segment in the segment table" << endl; |
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228 | exit (1); |
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229 | } |
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230 | |
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231 | entity.segment->define_target(TYPE_TTY,it); |
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232 | } |
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233 | |
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234 | for (uint32_t it = 0; it < nb_entity_ramlock; it++) |
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235 | { |
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236 | component_ramlock [it] = new Ramlock (param.param_ramlock[it].param); |
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237 | entity_t entity = component_data->entity(param.param_ramlock[it].address, param.param_ramlock[it].size); |
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238 | |
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239 | if (entity.present == false) |
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240 | { |
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241 | cerr << "<HIERARCHY_MEMORY> the ramlock [" << it << "] have not a segment in the segment table" << endl; |
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242 | exit (1); |
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243 | } |
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244 | |
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245 | entity.segment->define_target(TYPE_RAMLOCK,it); |
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246 | } |
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247 | |
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248 | component_sim2os = new Sim2os (param.param_sim2os.param); |
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249 | entity_t entity = component_data->entity(param.param_sim2os.address, param.param_sim2os.size); |
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250 | |
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251 | if (entity.present == false) |
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252 | { |
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253 | cerr << "<HIERARCHY_MEMORY> the sim2os have not a segment in the segment table" << endl; |
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254 | exit (1); |
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255 | } |
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256 | |
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257 | entity.segment->define_target(TYPE_SIM2OS,0); |
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258 | |
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259 | nb_context_stop = 0; |
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260 | context_stop = new bool [1<<SIZE_TRDID]; // the number of context is include in the REQ_TRDID |
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261 | for (uint32_t num_thread = 0; num_thread < (1<<SIZE_TRDID); num_thread ++) |
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262 | context_stop [num_thread] = false; |
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263 | |
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264 | // *****[ Definition of method ]***** |
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265 | SC_METHOD (transition); |
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266 | sensitive_pos << CLK; |
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267 | |
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268 | SC_METHOD (genMoore); |
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269 | sensitive_neg << CLK; |
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270 | |
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271 | cout << "<" << NAME << "> Successful Instanciation" << endl; |
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272 | }; |
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273 | |
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274 | //--------------------------------------------------------------------------------------------- |
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275 | //-----[ DESTRUCTOR ]-------------------------------------------------------------------------- |
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276 | //--------------------------------------------------------------------------------------------- |
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277 | public : ~HIERARCHY_MEMORY () |
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278 | { |
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279 | for (uint32_t it = 0; it < nb_entity_ramlock; it++) |
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280 | delete component_ramlock [it]; |
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281 | for (uint32_t it = 0; it < nb_entity_tty ; it++) |
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282 | delete component_tty [it]; |
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283 | |
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284 | for (uint32_t it = 0; it < nb_entity ; it++) |
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285 | { |
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286 | delete component_buffer_drsp [it]; |
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287 | delete component_buffer_irsp [it]; |
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288 | } |
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289 | |
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290 | delete component_cache ; |
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291 | delete component_data ; |
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292 | delete component_sim2os ; |
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293 | } |
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294 | |
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295 | //--------------------------------------------------------------------------------------------- |
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296 | //-----[ req_type2cache_type ]----------------------------------------------------------------- |
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297 | //--------------------------------------------------------------------------------------------- |
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298 | |
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299 | class req_type2cache_type_t |
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300 | { |
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301 | public : type_req_cache_t type ; |
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302 | public : direction_req_cache_t direction ; |
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303 | |
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304 | public : req_type2cache_type_t () {}; |
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305 | |
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306 | public : req_type2cache_type_t (type_req_cache_t type , |
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307 | direction_req_cache_t direction ) |
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308 | { |
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309 | this->type = type ; |
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310 | this->direction = direction; |
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311 | }; |
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312 | }; |
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313 | |
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314 | req_type2cache_type_t ireq_type2cache_type (uint32_t ireq_type, bool uncached) |
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315 | { |
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316 | type_req_cache_t type ; |
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317 | direction_req_cache_t direction; |
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318 | |
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319 | switch (ireq_type) |
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320 | { |
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321 | case ITYPE_READ : direction=READ ; type=CACHED ; break; |
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322 | case ITYPE_INVALIDATE : direction=NONE ; type=INVALIDATE; break; |
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323 | case ITYPE_PREFETCH : direction=NONE ; type=PREFETCH ; break; |
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324 | default : cerr << "<HIERARCHY_MEMORY.ireq_type2cache_type> Unkown type (" << type << ")" << endl; exit(1); |
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325 | } |
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326 | |
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327 | return req_type2cache_type_t (type,direction); |
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328 | } |
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329 | |
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330 | req_type2cache_type_t dreq_type2cache_type (uint32_t dreq_type, bool uncached) |
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331 | { |
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332 | type_req_cache_t type ; |
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333 | direction_req_cache_t direction; |
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334 | |
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335 | switch (dreq_type) |
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336 | { |
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337 | case DTYPE_READ : direction=READ ; type=((uncached==true)?UNCACHED:CACHED); break; |
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338 | case DTYPE_INVALIDATE : direction=NONE ; type=INVALIDATE ; break; |
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339 | case DTYPE_WRITE : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break; |
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340 | case DTYPE_WRITE_ACK : direction=WRITE; type=((uncached==true)?UNCACHED:CACHED); break; |
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341 | case DTYPE_FLUSH : direction=NONE ; type=FLUSH ; break; |
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342 | case DTYPE_PREFETCH : direction=NONE ; type=INVALIDATE ; break; |
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343 | |
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344 | default : cerr << "<HIERARCHY_MEMORY.ireq_type2cache_type> Unkown type (" << type << ")" << endl; exit(1); |
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345 | } |
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346 | |
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347 | return req_type2cache_type_t (type,direction); |
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348 | } |
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349 | //--------------------------------------------------------------------------------------------- |
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350 | //-----[ init ]-------------------------------------------------------------------------------- |
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351 | //--------------------------------------------------------------------------------------------- |
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352 | public : bool init (char * section, const char * filename, const char ** list_section) |
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353 | { |
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354 | return component_data->init(section,filename,list_section); |
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355 | } |
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356 | //--------------------------------------------------------------------------------------------- |
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357 | //-----[ reset ]------------------------------------------------------------------------------- |
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358 | //--------------------------------------------------------------------------------------------- |
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359 | public : void reset () |
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360 | { |
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361 | component_cache -> reset(); |
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362 | // Reset buffer of respons |
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363 | for (uint32_t it = 0; it < nb_entity; it++) |
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364 | { |
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365 | component_buffer_irsp [it] ->reset(); |
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366 | component_buffer_drsp [it] ->reset(); |
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367 | } |
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368 | for (uint32_t it = 0; it < nb_entity_ramlock; it++) |
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369 | component_ramlock [it] ->reset(); |
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370 | for (uint32_t it = 0; it < nb_entity_tty ; it++) |
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371 | component_tty [it] ->reset(); |
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372 | }//end reset |
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373 | |
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374 | //--------------------------------------------------------------------------------------------- |
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375 | //-----[ itoa ]-------------------------------------------------------------------------------- |
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376 | //--------------------------------------------------------------------------------------------- |
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377 | private :char * itoa (uint32_t int_src, char * string_dest, uint32_t size) |
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378 | { |
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379 | for (unsigned int it_size = 0; it_size < size; it_size ++) |
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380 | { |
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381 | string_dest [it_size] = (int_src & 0xFF); |
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382 | //string_dest [size-it_size-1] = (int_src & 0xFF); |
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383 | |
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384 | int_src >>= 8; |
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385 | } |
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386 | return string_dest; |
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387 | } |
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388 | |
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389 | //--------------------------------------------------------------------------------------------- |
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390 | //-----[ stop ]-------------------------------------------------------------------------------- |
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391 | //--------------------------------------------------------------------------------------------- |
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392 | public : bool stop () |
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393 | { |
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394 | return (nb_context_stop >= nb_context); |
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395 | } |
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396 | |
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397 | //--------------------------------------------------------------------------------------------- |
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398 | //-----[ transition ]-------------------------------------------------------------------------- |
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399 | //--------------------------------------------------------------------------------------------- |
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400 | public : void transition() |
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401 | { |
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402 | if (NRESET.read() == false) |
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403 | { |
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404 | reset (); |
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405 | return; |
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406 | } |
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407 | |
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408 | //~~~~~[ respons ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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409 | // POP All buffer of respons |
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410 | for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) |
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411 | { |
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412 | for (uint32_t num_port = nb_iport [num_entity]; num_port > 0 ; num_port --) |
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413 | if ((irsp_val[num_entity][num_port-1] && ICACHE [num_entity][num_port-1].RSP_ACK.read())==true) |
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414 | component_buffer_irsp [num_entity]->pop(num_port-1); |
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415 | |
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416 | for (uint32_t num_port = nb_dport [num_entity]; num_port > 0 ; num_port --) |
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417 | if ((drsp_val[num_entity][num_port-1] && DCACHE [num_entity][num_port-1].RSP_ACK.read())==true) |
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418 | component_buffer_drsp [num_entity]->pop(num_port-1); |
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419 | } |
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420 | |
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421 | //~~~~~[ request ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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422 | // cout << "<HIERARCHY_MEMORY.transition>" << endl; |
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423 | for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) |
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424 | { |
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425 | // ****************** |
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426 | // ***** ICACHE ***** |
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427 | // ****************** |
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428 | for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) |
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429 | { |
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430 | // Test if transaction |
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431 | if ( (ICACHE [num_entity][num_port].REQ_VAL.read() && ireq_ack [num_entity][num_port]) == false) |
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432 | continue; |
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433 | |
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434 | entity_t entity = component_data->entity((uint32_t)ICACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_IDATA/8); |
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435 | bool uncached = false; |
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436 | bool bus_error = false; |
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437 | |
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438 | sc_uint<2> type = ICACHE[num_entity][num_port].REQ_TYPE .read(); |
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439 | // A lot of flag |
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440 | bool must_read = ((type == DTYPE_READ ) ); |
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441 | bool must_ack = ((type == DTYPE_READ ) ); |
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442 | |
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443 | // Test the type of the address : if != MEMORY -> error |
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444 | if ((entity.present == true) && (entity.segment->getType() == TYPE_MEMORY)) |
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445 | { |
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446 | if (must_read == true) // Test if must read the ram |
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447 | for (unsigned int num_word = 0; num_word < NB_IWORD; num_word ++) |
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448 | { |
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449 | uint32_t addr = (uint32_t) ICACHE [num_entity][num_port].REQ_ADDR.read()+num_word*(SIZE_IDATA/8); |
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450 | bus_error |= !component_data->read(addr , |
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451 | SIZE_IDATA/8 , |
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452 | read_iram[num_word]); |
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453 | |
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454 | if (isSameEndianness((uint32_t)ICACHE[num_entity][num_port].REQ_TRDID.read()) == false) |
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455 | read_iram[num_word] = swapBytes(read_iram[num_word],SIZE_IDATA/8,4); |
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456 | } |
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457 | uncached = entity.segment->getUncached(); |
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458 | } |
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459 | else |
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460 | { |
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461 | // Have a bus error |
---|
462 | bus_error = true; |
---|
463 | uncached = true; |
---|
464 | } |
---|
465 | |
---|
466 | req_type2cache_type_t cache_type = ireq_type2cache_type ((uint32_t)type,uncached); |
---|
467 | // Simplification : the size of a line is a multiple of size_iword (no test) |
---|
468 | uint32_t latence = component_cache->latence(INSTRUCTION_CACHE , |
---|
469 | num_entity , |
---|
470 | num_port , |
---|
471 | (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() , |
---|
472 | (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() , |
---|
473 | cache_type.type , |
---|
474 | cache_type.direction ); |
---|
475 | |
---|
476 | // If is a respons -> compute the latence and push in the write_buffer |
---|
477 | if (must_ack == true) |
---|
478 | { |
---|
479 | if (bus_error == true) |
---|
480 | cout << "Icache : have a bus error" << endl |
---|
481 | << " * num_entity : " << num_entity << endl |
---|
482 | << " * num_port : " << num_port << endl |
---|
483 | << hex |
---|
484 | << " * req_addr : " << (uint32_t)ICACHE [num_entity][num_port].REQ_ADDR .read() << endl |
---|
485 | << dec |
---|
486 | << " * req_trdid : " << (uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() << endl |
---|
487 | << " * req_pktid : " << (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() << endl; |
---|
488 | |
---|
489 | component_buffer_irsp [num_entity]->push(latence, |
---|
490 | Entry((uint32_t)ICACHE [num_entity][num_port].REQ_TRDID.read() , |
---|
491 | (uint32_t)ICACHE [num_entity][num_port].REQ_PKTID.read() , |
---|
492 | NB_IWORD , |
---|
493 | SIZE_IDATA/8 , |
---|
494 | read_iram , |
---|
495 | (bus_error==true)?ERR_BUS:ERR_NO ) |
---|
496 | ); |
---|
497 | } |
---|
498 | }//num_port |
---|
499 | |
---|
500 | // ****************** |
---|
501 | // ***** DCACHE ***** |
---|
502 | // ****************** |
---|
503 | |
---|
504 | for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) |
---|
505 | { |
---|
506 | // Test if transaction |
---|
507 | // cout << "[" << num_entity << "]" |
---|
508 | // << "[" << num_port << "] " |
---|
509 | // << "dreq_val : " << DCACHE [num_entity][num_port].REQ_VAL.read() << " " |
---|
510 | // << "dreq_ack : " << dreq_ack [num_entity][num_port] << endl; |
---|
511 | |
---|
512 | if ( (DCACHE [num_entity][num_port].REQ_VAL.read() && dreq_ack [num_entity][num_port]) == false) |
---|
513 | continue; |
---|
514 | |
---|
515 | entity_t entity = component_data->entity((uint32_t)DCACHE [num_entity][num_port].REQ_ADDR.read(), SIZE_DDATA/8); |
---|
516 | |
---|
517 | bool uncached = DCACHE [num_entity][num_port].REQ_UNC.read(); |
---|
518 | bool bus_error = false; |
---|
519 | |
---|
520 | uint32_t addr = (uint32_t) DCACHE [num_entity][num_port].REQ_ADDR.read(); |
---|
521 | sc_uint<SIZE_DDATA> wdata = DCACHE[num_entity][num_port].REQ_WDATA .read(); |
---|
522 | sc_uint<3> type = DCACHE[num_entity][num_port].REQ_TYPE .read(); |
---|
523 | uint32_t nb_bytes = access_nb_bytes(DCACHE[num_entity][num_port].REQ_ACCESS.read()); |
---|
524 | // A lot of flag |
---|
525 | bool must_read = ((type == DTYPE_READ )); |
---|
526 | bool must_write = ((type == DTYPE_WRITE ) || |
---|
527 | (type == DTYPE_WRITE_ACK ) ); |
---|
528 | bool must_ack = ((type == DTYPE_READ ) || |
---|
529 | (type == DTYPE_WRITE_ACK ) ); |
---|
530 | |
---|
531 | // Test the type of the address |
---|
532 | if (entity.present == true) |
---|
533 | { |
---|
534 | switch (entity.segment->getType()) |
---|
535 | { |
---|
536 | // ACCESS AT A RAM |
---|
537 | case TYPE_MEMORY : |
---|
538 | { |
---|
539 | if (must_read == true) |
---|
540 | { |
---|
541 | // Read |
---|
542 | bus_error |= !component_data->read(addr , |
---|
543 | SIZE_DDATA/8 , // always read a complete word |
---|
544 | read_dram ); |
---|
545 | |
---|
546 | for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes) |
---|
547 | memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes); |
---|
548 | |
---|
549 | // Permutation if problem of endianness |
---|
550 | if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) |
---|
551 | read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes); |
---|
552 | } |
---|
553 | |
---|
554 | if (must_write == true) |
---|
555 | { |
---|
556 | // Write |
---|
557 | for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++) |
---|
558 | write_dram [it_nb_bytes] = wdata.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes); |
---|
559 | } |
---|
560 | break; |
---|
561 | } |
---|
562 | //ACCESS AT THE TTY |
---|
563 | case TYPE_TTY : |
---|
564 | { |
---|
565 | if (must_write == false) |
---|
566 | { |
---|
567 | bus_error = true; |
---|
568 | break; |
---|
569 | } |
---|
570 | uint32_t num_tty = (addr - entity.segment->getBase())>>4; |
---|
571 | uint32_t num_print = ((addr>>2) & 0x3); |
---|
572 | |
---|
573 | switch (num_print) |
---|
574 | { |
---|
575 | case 0 : // Write TTY |
---|
576 | { |
---|
577 | uint32_t num_component_tty = entity.segment->getIndex(); |
---|
578 | char char_write = (char)wdata.range( 7, 0); |
---|
579 | bus_error |= !component_tty [num_component_tty]->write(num_tty,char_write); |
---|
580 | break; |
---|
581 | } |
---|
582 | case 1 : // STOP |
---|
583 | { |
---|
584 | printf("\n\t***** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x *****\n" |
---|
585 | ,(unsigned int)sc_simulation_time() |
---|
586 | ,(unsigned int)addr |
---|
587 | ,(unsigned int)wdata.range(31,24) |
---|
588 | ,(unsigned int)wdata.range(23,16) |
---|
589 | ,(unsigned int)wdata.range(15, 8) |
---|
590 | ,(unsigned int)wdata.range( 7, 0) |
---|
591 | ); |
---|
592 | |
---|
593 | uint32_t trdid = (uint32_t) DCACHE[num_entity][num_port].REQ_TRDID.read(); |
---|
594 | |
---|
595 | if (context_stop [trdid] == false) |
---|
596 | { |
---|
597 | context_stop [trdid] = true; |
---|
598 | nb_context_stop ++; |
---|
599 | |
---|
600 | if (nb_context_stop >= nb_context) |
---|
601 | sc_stop(); |
---|
602 | } |
---|
603 | |
---|
604 | break; |
---|
605 | } |
---|
606 | case 2 : // PRINT |
---|
607 | { |
---|
608 | printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n" |
---|
609 | ,(unsigned int)sc_simulation_time() |
---|
610 | ,(unsigned int)addr |
---|
611 | ,(unsigned int)wdata.range(31,24) |
---|
612 | ,(unsigned int)wdata.range(23,16) |
---|
613 | ,(unsigned int)wdata.range(15, 8) |
---|
614 | ,(unsigned int)wdata.range( 7, 0) |
---|
615 | ); |
---|
616 | |
---|
617 | break; |
---|
618 | } |
---|
619 | default : |
---|
620 | { |
---|
621 | printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print); |
---|
622 | exit(1); |
---|
623 | } |
---|
624 | } |
---|
625 | |
---|
626 | break; |
---|
627 | } |
---|
628 | case TYPE_RAMLOCK : |
---|
629 | { |
---|
630 | // Access is on a byte, else error |
---|
631 | if (nb_bytes != 1) |
---|
632 | { |
---|
633 | bus_error = true; |
---|
634 | break; |
---|
635 | } |
---|
636 | uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access |
---|
637 | uint32_t num_component_ramlock = entity.segment->getIndex(); |
---|
638 | bus_error |= !component_ramlock [num_component_ramlock]->test(num_ramlock); |
---|
639 | |
---|
640 | if (bus_error == true) |
---|
641 | break; |
---|
642 | |
---|
643 | memset (read_dram,0,SIZE_DDATA/8); |
---|
644 | |
---|
645 | if (must_read == true) |
---|
646 | read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock); |
---|
647 | if (must_write == true) |
---|
648 | read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock); |
---|
649 | |
---|
650 | /* |
---|
651 | printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time()); |
---|
652 | printf(" * addr : %.8x\n" ,(uint32_t)addr); |
---|
653 | printf(" * trdid : %d\n" ,(uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()); |
---|
654 | printf(" * r/w : %d/%d\n",must_read,must_write); |
---|
655 | printf(" * val : %d\n" ,(uint32_t)read_dram[0]); |
---|
656 | */ |
---|
657 | break; |
---|
658 | } |
---|
659 | case TYPE_SIM2OS : |
---|
660 | { |
---|
661 | // Mapping : |
---|
662 | // [0] number of service - Wonly - A write in this register lunch the execution of service |
---|
663 | // [1] result - Ronly - Content the result of the service |
---|
664 | // [2] error - Ronly - Content the code of errno |
---|
665 | // [3+] argument - Wonly - it's all argument to execute the service |
---|
666 | |
---|
667 | uint32_t num_reg = (addr - entity.segment->getBase())>>2; |
---|
668 | |
---|
669 | switch (num_reg) |
---|
670 | { |
---|
671 | case 0 : // ---> number of service |
---|
672 | { |
---|
673 | if (must_write == false) |
---|
674 | { |
---|
675 | cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl; |
---|
676 | bus_error = true; |
---|
677 | } |
---|
678 | else |
---|
679 | { |
---|
680 | printf("<sim2os> service : %.8x\n",(uint32_t)wdata); |
---|
681 | component_sim2os->execute(int2service((uint32_t)wdata)); |
---|
682 | } |
---|
683 | break; |
---|
684 | } |
---|
685 | case 1 : // ---> result |
---|
686 | { |
---|
687 | if (must_read == false) |
---|
688 | { |
---|
689 | cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl; |
---|
690 | bus_error = true; |
---|
691 | } |
---|
692 | else |
---|
693 | { |
---|
694 | // Decomposition en groupe octect |
---|
695 | uint32_t result = (uint32_t) component_sim2os->result; |
---|
696 | printf("<sim2os> result : %.8x (%d)\n",result,result); |
---|
697 | |
---|
698 | read_dram = itoa(result,read_dram,SIZE_DDATA/8); |
---|
699 | } |
---|
700 | break; |
---|
701 | } |
---|
702 | case 2 : // ---> error |
---|
703 | { |
---|
704 | if (must_read == false) |
---|
705 | { |
---|
706 | cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl; |
---|
707 | bus_error = true; |
---|
708 | } |
---|
709 | else |
---|
710 | { |
---|
711 | // Decomposition en groupe octect |
---|
712 | uint32_t error = (uint32_t) component_sim2os->error; |
---|
713 | printf("<sim2os> error : %.8x\n",error); |
---|
714 | read_dram = itoa(error ,read_dram,SIZE_DDATA/8); |
---|
715 | } |
---|
716 | break; |
---|
717 | } |
---|
718 | default : // ---> argument |
---|
719 | { |
---|
720 | if (must_write == false) |
---|
721 | { |
---|
722 | cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl; |
---|
723 | bus_error = true; |
---|
724 | } |
---|
725 | else |
---|
726 | { |
---|
727 | uint32_t data = (uint32_t)wdata; |
---|
728 | printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data); |
---|
729 | component_sim2os->parameter(num_reg-2,(void *)data); |
---|
730 | } |
---|
731 | break; |
---|
732 | } |
---|
733 | }//end switch num_reg |
---|
734 | |
---|
735 | break; |
---|
736 | } |
---|
737 | default : |
---|
738 | { |
---|
739 | // Have a bus error |
---|
740 | bus_error = true; |
---|
741 | break; |
---|
742 | } |
---|
743 | }// switch |
---|
744 | uncached |= entity.segment->getUncached(); |
---|
745 | } |
---|
746 | else |
---|
747 | uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist |
---|
748 | |
---|
749 | |
---|
750 | if ((must_write == true) && (bus_error == false)) |
---|
751 | { |
---|
752 | // Permutation if problem of endianness |
---|
753 | if (isSameEndianness((uint32_t)DCACHE[num_entity][num_port].REQ_TRDID.read()) == false) |
---|
754 | write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes); |
---|
755 | |
---|
756 | bus_error |= !component_data->write(addr , |
---|
757 | nb_bytes, // take the good access |
---|
758 | write_dram ); |
---|
759 | } |
---|
760 | |
---|
761 | |
---|
762 | // Acces at the cache !!! |
---|
763 | req_type2cache_type_t cache_type = dreq_type2cache_type (type, uncached); |
---|
764 | |
---|
765 | uint32_t latence = component_cache->latence(DATA_CACHE , |
---|
766 | num_entity , |
---|
767 | num_port , |
---|
768 | (uint32_t)DCACHE [num_entity][num_port].REQ_ADDR .read() , |
---|
769 | (uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() , |
---|
770 | cache_type.type , |
---|
771 | cache_type.direction ); |
---|
772 | |
---|
773 | // If is a respons -> compute the latence and push in the write_buffer |
---|
774 | if ( must_ack == true) |
---|
775 | { |
---|
776 | if (bus_error == true) |
---|
777 | cout << "Dcache : have a bus error" << endl; |
---|
778 | component_buffer_drsp [num_entity]->push(latence, |
---|
779 | Entry((uint32_t)DCACHE [num_entity][num_port].REQ_TRDID.read() , |
---|
780 | (uint32_t)DCACHE [num_entity][num_port].REQ_PKTID.read() , |
---|
781 | 1 , |
---|
782 | SIZE_DDATA/8 , |
---|
783 | &read_dram , |
---|
784 | (bus_error==true)?ERR_BUS:ERR_NO ) |
---|
785 | ); |
---|
786 | } |
---|
787 | }// dnb_port |
---|
788 | }//num_entity |
---|
789 | |
---|
790 | // Transition for each component |
---|
791 | component_cache -> transition(); |
---|
792 | // Transition buffer of respons |
---|
793 | for (uint32_t it = 0; it < nb_entity; it++) |
---|
794 | { |
---|
795 | component_buffer_irsp [it] ->transition(); |
---|
796 | component_buffer_drsp [it] ->transition(); |
---|
797 | } |
---|
798 | component_sim2os->transition(); |
---|
799 | |
---|
800 | }//end transition |
---|
801 | |
---|
802 | //--------------------------------------------------------------------------------------------- |
---|
803 | //-----[ genMoore ]---------------------------------------------------------------------------- |
---|
804 | //--------------------------------------------------------------------------------------------- |
---|
805 | public : void genMoore() |
---|
806 | { |
---|
807 | //Scan all entity and for each entity scan all port |
---|
808 | for (uint32_t num_entity = 0; num_entity < nb_entity; num_entity++) |
---|
809 | { |
---|
810 | //##### REQUEST ##### |
---|
811 | uint32_t nb_slot_free = component_buffer_irsp [num_entity]->nb_slot_free (); |
---|
812 | for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) |
---|
813 | { |
---|
814 | ireq_ack [num_entity][num_port] = (num_port < nb_slot_free); |
---|
815 | |
---|
816 | ICACHE [num_entity][num_port].REQ_ACK.write (ireq_ack [num_entity][num_port]); |
---|
817 | } |
---|
818 | |
---|
819 | nb_slot_free = component_buffer_drsp [num_entity]->nb_slot_free (); |
---|
820 | for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) |
---|
821 | { |
---|
822 | dreq_ack [num_entity][num_port] = (num_port < nb_slot_free ); |
---|
823 | |
---|
824 | DCACHE [num_entity][num_port].REQ_ACK.write (dreq_ack [num_entity][num_port]); |
---|
825 | } |
---|
826 | |
---|
827 | //##### RESPONS ##### |
---|
828 | // ~~~~~> ICACHE <~~~~~ |
---|
829 | for (uint32_t num_port = 0; num_port < nb_iport [num_entity]; num_port ++) |
---|
830 | { |
---|
831 | // Test the number of element in the respons's buffer |
---|
832 | if (num_port >= component_buffer_irsp [num_entity]->nb_slot_use()) |
---|
833 | { |
---|
834 | irsp_val[num_entity][num_port] = 0; // No respons |
---|
835 | } |
---|
836 | else |
---|
837 | { |
---|
838 | slot_t<Entry> slot = component_buffer_irsp [num_entity]->read(num_port); |
---|
839 | |
---|
840 | irsp_val[num_entity][num_port] = (slot.delay == 0); // respons if have a result |
---|
841 | ICACHE [num_entity][num_port].RSP_TRDID.write((sc_uint<SIZE_TRDID> )slot.data.trdid); |
---|
842 | ICACHE [num_entity][num_port].RSP_PKTID.write((sc_uint<SIZE_IPKTID>)slot.data.pktid); |
---|
843 | ICACHE [num_entity][num_port].RSP_ERR .write((sc_uint<2> )slot.data.error); |
---|
844 | |
---|
845 | for (uint32_t num_word = 0; num_word < NB_IWORD; num_word ++) |
---|
846 | { |
---|
847 | sc_uint<SIZE_IDATA> data; |
---|
848 | |
---|
849 | for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_IDATA / 8; it_nb_bytes ++) |
---|
850 | { |
---|
851 | #if defined(systemcass) |
---|
852 | RANGE_SET_VAL(SIZE_IDATA , |
---|
853 | data , |
---|
854 | 8*(it_nb_bytes+1)-1, |
---|
855 | 8*it_nb_bytes , |
---|
856 | slot.data.data [num_word][it_nb_bytes]); |
---|
857 | #else //#elif defined(systemc) |
---|
858 | data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [num_word][it_nb_bytes]; |
---|
859 | #endif |
---|
860 | } |
---|
861 | ICACHE [num_entity][num_port].RSP_INS [num_word].write(data); |
---|
862 | } |
---|
863 | } |
---|
864 | |
---|
865 | ICACHE [num_entity][num_port].RSP_VAL.write(irsp_val[num_entity][num_port]); |
---|
866 | }//end nb_iport |
---|
867 | |
---|
868 | // ~~~~~> DCACHE <~~~~~ |
---|
869 | for (uint32_t num_port = 0; num_port < nb_dport [num_entity]; num_port ++) |
---|
870 | { |
---|
871 | if (num_port >= component_buffer_drsp [num_entity]->nb_slot_use()) |
---|
872 | { |
---|
873 | drsp_val[num_entity][num_port] = 0; // No respons |
---|
874 | } |
---|
875 | else |
---|
876 | { |
---|
877 | slot_t<Entry> slot = component_buffer_drsp [num_entity]->read(num_port); |
---|
878 | |
---|
879 | drsp_val[num_entity][num_port] = (slot.delay == 0); |
---|
880 | DCACHE [num_entity][num_port].RSP_TRDID = (sc_uint<SIZE_TRDID> )slot.data.trdid; |
---|
881 | DCACHE [num_entity][num_port].RSP_PKTID = (sc_uint<SIZE_DPKTID>)slot.data.pktid; |
---|
882 | DCACHE [num_entity][num_port].RSP_ERR = (sc_uint<2> )slot.data.error; |
---|
883 | |
---|
884 | sc_uint<SIZE_DDATA> data; |
---|
885 | |
---|
886 | for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++) |
---|
887 | { |
---|
888 | #if defined(systemcass) |
---|
889 | RANGE_SET_VAL(SIZE_DDATA , |
---|
890 | data , |
---|
891 | 8*(it_nb_bytes+1)-1, |
---|
892 | 8*it_nb_bytes , |
---|
893 | slot.data.data [0][it_nb_bytes]); |
---|
894 | #else //#elif defined(systemc) |
---|
895 | data.range(8*(it_nb_bytes+1)-1,8*it_nb_bytes) = slot.data.data [0][it_nb_bytes]; |
---|
896 | #endif |
---|
897 | } |
---|
898 | DCACHE [num_entity][num_port].RSP_RDATA.write(data); |
---|
899 | } |
---|
900 | DCACHE [num_entity][num_port].RSP_VAL = drsp_val[num_entity][num_port]; |
---|
901 | }//nb_dport |
---|
902 | }//nb_entity |
---|
903 | }//end genMoore |
---|
904 | |
---|
905 | //--------------------------------------------------------------------------------------------- |
---|
906 | //-----[ operator<< ]-------------------------------------------------------------------------- |
---|
907 | //--------------------------------------------------------------------------------------------- |
---|
908 | |
---|
909 | friend ostream& operator<< (ostream& output_stream, const HIERARCHY_MEMORY &x) |
---|
910 | { |
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911 | output_stream << "<" << x.NAME << ">" << endl |
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912 | << " * nb_entity : " << x.nb_entity << endl; |
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913 | |
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914 | output_stream << " -----[ component_data ]-----------------------------------" << endl; |
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915 | output_stream << *x.component_data << endl; |
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916 | |
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917 | output_stream << " -----[ component_cache ]----------------------------------" << endl; |
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918 | output_stream << *x.component_cache; |
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919 | |
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920 | output_stream << " -----[ component_buffer_irsp ]----------------------------" << endl; |
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921 | for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++) |
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922 | { |
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923 | output_stream << " * nb_iport [" << num_entity << "] : " << x.nb_iport [num_entity] << endl; |
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924 | output_stream << *x.component_buffer_irsp [num_entity]; |
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925 | } |
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926 | |
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927 | output_stream << " -----[ component_buffer_drsp ]----------------------------" << endl; |
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928 | for (uint32_t num_entity = 0; num_entity < x.nb_entity; num_entity++) |
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929 | { |
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930 | output_stream << " * nb_dport [" << num_entity << "] : " << x.nb_dport [num_entity] << endl; |
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931 | output_stream << *x.component_buffer_drsp [num_entity]; |
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932 | } |
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933 | |
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934 | // output_stream << " -----[ component_ramlock ]--------------------------------" << endl; |
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935 | // output_stream << " * nb_entity_ramlock : " << x.nb_entity_ramlock << endl; |
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936 | // for (uint32_t it = 0; it < x.nb_entity_ramlock; it++) |
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937 | // output_stream << *x.component_ramlock [it]; |
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938 | |
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939 | // output_stream << " -----[ component_tty ]------------------------------------" << endl; |
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940 | // output_stream << " * nb_entity_tty : " << x.nb_entity_tty << endl; |
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941 | // for (uint32_t it = 0; it < x.nb_entity_tty ; it++) |
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942 | // output_stream << *x.component_tty [it]; |
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943 | |
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944 | // output_stream << *x.component_sim2os; |
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945 | |
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946 | return output_stream; |
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947 | } |
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948 | |
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949 | };//class |
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950 | }; |
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951 | |
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952 | #endif //!HIERARCHY_MEMORY_H |
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