[2] | 1 | #include "hierarchy_memory.h" |
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| 2 | #include <systemc.h> |
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| 3 | #include <iostream> |
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| 4 | |
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| 5 | #define TEXT_BASE 0x00000000 |
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| 6 | #define TEXT_SIZE 0x00005000 |
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| 7 | |
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| 8 | #define DATA_CACHED_BASE 0x10000000 |
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| 9 | #define DATA_CACHED_SIZE 0x00000100 |
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| 10 | |
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| 11 | #define DATA_UNCACHED_BASE 0x40000000 |
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| 12 | #define DATA_UNCACHED_SIZE 0x00000100 |
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| 13 | |
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| 14 | #define STACK_BASE 0x50000000 |
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| 15 | #define STACK_SIZE 0x00000200 |
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| 16 | |
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| 17 | #define TTY1_BASE 0x60000000 |
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| 18 | #define TTY1_SIZE 0x00000100 |
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| 19 | |
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| 20 | #define TTY2_BASE 0x60000100 |
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| 21 | #define TTY2_SIZE 0x00000200 |
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| 22 | |
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| 23 | #define SIM2OS_BASE 0x70000000 |
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| 24 | #define SIM2OS_SIZE 0x00000100 |
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| 25 | |
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| 26 | #define RAMLOCK_BASE 0x80000000 |
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| 27 | #define RAMLOCK_SIZE 0x00000100 |
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| 28 | |
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| 29 | // using namespace hierarchy_memory::data; |
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| 30 | using namespace std; |
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| 31 | using namespace hierarchy_memory; |
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| 32 | |
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| 33 | //-----[ Routine de test ]--------------------------------------- |
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| 34 | |
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| 35 | void test_ko (char * file, uint32_t line) |
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| 36 | { |
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| 37 | cerr << "***** Test KO *****" << endl |
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| 38 | << " - File : " << file << endl |
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| 39 | << " - Line : " << line << endl; |
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| 40 | exit (line); |
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| 41 | }; |
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| 42 | |
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| 43 | void test_ok () |
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| 44 | { |
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| 45 | cout << "***** Test OK *****" << endl; |
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| 46 | exit (0); |
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| 47 | }; |
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| 48 | |
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| 49 | template <class T> |
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| 50 | void test(T exp1, T exp2, char * file, uint32_t line) |
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| 51 | { |
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| 52 | if (exp1 != exp2) |
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| 53 | { |
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| 54 | cerr << "Expression is different : " << endl |
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| 55 | << " - exp1 : " << exp1 << endl |
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| 56 | << " - exp2 : " << exp2 << endl; |
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| 57 | |
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| 58 | test_ko (file,line); |
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| 59 | } |
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| 60 | }; |
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| 61 | |
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| 62 | #define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0) |
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| 63 | |
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| 64 | int sc_main(int argc, char* argv[]) |
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| 65 | { |
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| 66 | cout << "<main> Test de \"HIERARCHY_MEMORY\"" << endl; |
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| 67 | |
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| 68 | /********************************************************************* |
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| 69 | * Declarations des constantes |
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| 70 | *********************************************************************/ |
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| 71 | const uint32_t nb_context = 6; |
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| 72 | const uint32_t nb_cluster = 2; |
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| 73 | const uint32_t nb_iport = 1; |
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| 74 | const uint32_t nb_dport = 3; |
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| 75 | const uint32_t size_trdid = 5; |
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| 76 | const uint32_t size_ipktid = 4; |
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| 77 | const uint32_t size_iaddr = 32; |
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| 78 | const uint32_t size_idata = 32; |
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| 79 | const uint32_t nb_iword = 2; |
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| 80 | const uint32_t size_dpktid = 2; |
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| 81 | const uint32_t size_daddr = 32; |
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| 82 | const uint32_t size_ddata = 32; |
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| 83 | |
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| 84 | const uint32_t size_buffer_irsp = 9; |
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| 85 | const uint32_t size_buffer_drsp = 7; |
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| 86 | /********************************************************************* |
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| 87 | * Declarations des signaux |
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| 88 | *********************************************************************/ |
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| 89 | cout << " * Declaration of signals" << endl; |
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| 90 | sc_clock CLK ("clock",1,0.5); |
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| 91 | sc_signal<bool> NRESET; |
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| 92 | |
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| 93 | ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> ** icache_signals; |
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| 94 | DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> ** dcache_signals; |
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| 95 | |
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| 96 | icache_signals = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> * [nb_cluster]; |
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| 97 | dcache_signals = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> * [nb_cluster]; |
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| 98 | |
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| 99 | for (uint32_t x = 0; x < nb_cluster; x ++) |
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| 100 | { |
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| 101 | icache_signals[x] = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> [nb_iport]; |
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| 102 | dcache_signals[x] = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> [nb_dport]; |
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| 103 | } |
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| 104 | |
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| 105 | /********************************************************************* |
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| 106 | * Segmentation table |
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| 107 | *********************************************************************/ |
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| 108 | cout << " * Segment_table" << endl; |
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| 109 | |
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| 110 | SOCLIB_SEGMENT_TABLE segtable; |
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| 111 | segtable.setMSBNumber (8); |
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| 112 | segtable.setDefaultTarget(0,0); |
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| 113 | |
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| 114 | // Add a segment :name , address of base , size , global index , local index, uncache |
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| 115 | segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false); |
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| 116 | segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false); |
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| 117 | segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true ); |
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| 118 | segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false); |
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| 119 | segtable.addSegment("tty1" , TTY1_BASE , TTY1_SIZE , 0 ,0 , true ); |
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| 120 | segtable.addSegment("tty2" , TTY2_BASE , TTY2_SIZE , 0 ,0 , true ); |
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| 121 | segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true ); |
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| 122 | segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true ); |
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| 123 | |
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| 124 | const char * sections_text [] = {".text",NULL}; |
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| 125 | const char * sections_data [] = {".data",".rodata",".sdata",".sbss",".bss", NULL}; |
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| 126 | const char * sections_stack [] = {".stack",NULL}; |
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| 127 | const char * filename = "soft.x"; |
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| 128 | |
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| 129 | /********************************************************************* |
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| 130 | * Declaration of component |
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| 131 | *********************************************************************/ |
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| 132 | char * name_tty1[nb_context/2] = { "tty_0", |
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| 133 | "tty_1", |
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| 134 | "tty_2"}; |
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| 135 | |
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| 136 | char * name_tty2[nb_context/2] = { "tty_3", |
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| 137 | "tty_4", |
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| 138 | "tty_5"}; |
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| 139 | |
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| 140 | // nb_line, size_line, size_word, associativity, hit_latence, miss_penality |
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| 141 | #define L1_ICACHE "L1_ICACHE", 4, 2, 4, 4, 1, 4 |
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| 142 | #define L1_DCACHE "L1_DCACHE", 4, 2, 4, 4, 1, 4 |
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| 143 | #define L2_CACHE "L2_CACHE", 8, 4, 4, 2, 2, 7 |
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| 144 | #define L3_CACHE "L3_CACHE", 16, 8, 4, 1, 3, 12 |
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| 145 | |
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| 146 | param_cache_t param_icache_1 [1] = { param_cache_t (L1_ICACHE) }; |
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| 147 | param_cache_t param_dcache_1 [1] = { param_cache_t (L1_DCACHE) }; |
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| 148 | param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) , |
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| 149 | param_cache_t (L3_CACHE) }; |
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| 150 | |
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| 151 | cache::cache_multilevel::param_t param_icache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_icache_dedicated[0]",1, nb_iport, param_icache_1), |
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| 152 | cache::cache_multilevel::param_t ("param_icache_dedicated[1]",1, nb_iport, param_icache_1), |
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| 153 | }; |
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| 154 | |
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| 155 | cache::cache_multilevel::param_t param_dcache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_dcache_dedicated[0]",1, nb_dport, param_dcache_1), |
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| 156 | cache::cache_multilevel::param_t ("param_dcache_dedicated[1]",1, nb_dport, param_dcache_1), |
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| 157 | }; |
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| 158 | |
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| 159 | cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",2, nb_cluster*(nb_iport+nb_dport), param_cache_2); |
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| 160 | |
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| 161 | cache::param_t param_cache ("cache" , |
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| 162 | nb_cluster , |
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| 163 | param_icache_dedicated, |
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| 164 | param_dcache_dedicated, |
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| 165 | param_cache_shared ); |
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| 166 | param_entity_t<tty::param_t> param_tty [2] = {param_entity_t<tty::param_t> (TTY1_BASE , TTY1_SIZE , tty::param_t ("tty1" , nb_context/2, name_tty1,true)), |
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| 167 | param_entity_t<tty::param_t> (TTY2_BASE , TTY2_SIZE , tty::param_t ("tty2" , nb_context/2, name_tty2,true))}; |
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| 168 | param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t>(RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))}; |
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| 169 | |
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| 170 | |
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| 171 | param_entity_t<sim2os::param_t> param_sim2os = param_entity_t<sim2os::param_t>(SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable)); |
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| 172 | |
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| 173 | #define PARAM_MEMORY 2,param_tty,1,param_ramlock,param_sim2os,param_cache |
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| 174 | #define PARAM "memory", 0,0, &segtable,nb_cluster, nb_context,size_buffer_irsp, size_buffer_drsp, hierarchy_memory::param_t(PARAM_MEMORY) |
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| 175 | #define TEMPLATE size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword, size_dpktid, size_daddr, size_ddata |
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| 176 | |
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| 177 | HIERARCHY_MEMORY <TEMPLATE> * memory = new HIERARCHY_MEMORY <TEMPLATE> (PARAM); |
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| 178 | |
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| 179 | /********************************************************************* |
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| 180 | * Instanciation |
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| 181 | *********************************************************************/ |
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| 182 | memory->CLK (CLK); |
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| 183 | memory->NRESET (NRESET); |
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| 184 | |
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| 185 | for (uint32_t x = 0; x < nb_cluster; x ++) |
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| 186 | { |
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| 187 | for (uint32_t y = 0; y < nb_iport; y ++) |
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| 188 | memory->ICACHE[x][y] (icache_signals [x][y]); |
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| 189 | for (uint32_t y = 0; y < nb_dport; y ++) |
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| 190 | memory->DCACHE[x][y] (dcache_signals [x][y]); |
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| 191 | } |
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| 192 | |
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| 193 | cout << " * Create a HIERARCHY_MEMORY" << endl; |
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| 194 | |
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| 195 | TEST(bool,memory->init("text" , filename, sections_text) ,true); |
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| 196 | TEST(bool,memory->init("stack" , filename, sections_stack),true); |
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| 197 | TEST(bool,memory->init("data" , filename, sections_data) ,true); |
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| 198 | |
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| 199 | /******************************************************** |
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| 200 | * Simulation - Begin |
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| 201 | ********************************************************/ |
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| 202 | |
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| 203 | cout << " * simulation" << endl; |
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| 204 | // Initialisation |
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| 205 | sc_start(0); |
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| 206 | |
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| 207 | // Init control signal |
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| 208 | for (uint32_t x = 0; x < nb_cluster; x ++) |
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| 209 | { |
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| 210 | for (uint32_t y = 0; y < nb_iport; y ++) |
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| 211 | { |
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| 212 | icache_signals [x][y].REQ_VAL.write (false); |
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| 213 | icache_signals [x][y].RSP_ACK.write (false); |
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| 214 | } |
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| 215 | for (uint32_t y = 0; y < nb_dport; y ++) |
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| 216 | { |
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| 217 | dcache_signals [x][y].REQ_VAL.write (false); |
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| 218 | dcache_signals [x][y].RSP_ACK.write (false); |
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| 219 | } |
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| 220 | } |
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| 221 | |
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| 222 | // Reset |
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| 223 | uint32_t iaddr = 0x2000; |
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| 224 | |
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| 225 | #define CYCLE(n) do {sc_start(n); cout << "*****{ " << setw(5) << (uint32_t) sc_simulation_time() << " }*****" << endl;} while(0) |
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| 226 | #define NEXT_CYCLE() do {CYCLE(1); getchar();} while(0) |
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| 227 | |
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| 228 | NRESET.write(false); |
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| 229 | CYCLE(5); |
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| 230 | NRESET.write(true); |
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| 231 | |
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| 232 | { |
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| 233 | cout << " -> Test of Icache" << endl; |
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| 234 | iaddr = 0x100; |
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| 235 | icache_signals [0][0].REQ_VAL .write(true); |
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| 236 | icache_signals [0][0].REQ_TRDID.write(1); |
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| 237 | icache_signals [0][0].REQ_PKTID.write(0); |
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| 238 | icache_signals [0][0].REQ_ADDR .write(iaddr); |
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| 239 | icache_signals [0][0].REQ_TYPE .write(ITYPE_READ); |
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| 240 | |
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| 241 | icache_signals [0][0].RSP_ACK .write(false); |
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| 242 | |
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| 243 | CYCLE(1); |
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| 244 | iaddr = 0x2000; |
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| 245 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 246 | |
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| 247 | CYCLE(1); |
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| 248 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 249 | |
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| 250 | CYCLE(1); |
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| 251 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 252 | |
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| 253 | CYCLE(1); |
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| 254 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 255 | |
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| 256 | CYCLE(1); |
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| 257 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 258 | |
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| 259 | CYCLE(1); |
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| 260 | |
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| 261 | icache_signals [0][0].REQ_VAL .write(false); |
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| 262 | |
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| 263 | CYCLE(22); |
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| 264 | |
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| 265 | icache_signals [0][0].RSP_ACK .write(true ); |
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| 266 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false); |
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| 267 | |
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| 268 | CYCLE(1); |
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| 269 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 270 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x18400000); |
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| 271 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa8422000); |
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| 272 | |
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| 273 | CYCLE(1); |
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| 274 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 275 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x182051ff); |
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| 276 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa821fffc); |
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| 277 | |
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| 278 | CYCLE(1); |
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| 279 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 280 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd); |
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| 281 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624); |
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| 282 | |
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| 283 | CYCLE(1); |
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| 284 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 285 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003); |
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| 286 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050); |
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| 287 | |
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| 288 | CYCLE(1); |
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| 289 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 290 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000); |
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| 291 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306); |
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| 292 | |
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| 293 | CYCLE(1); |
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| 294 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 295 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002); |
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| 296 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004); |
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| 297 | |
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| 298 | CYCLE(1); |
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| 299 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false); |
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| 300 | |
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| 301 | iaddr = 0x2008; |
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| 302 | icache_signals [0][0].REQ_VAL .write(true); |
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| 303 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 304 | |
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| 305 | CYCLE(1); |
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| 306 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 307 | |
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| 308 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 309 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd); |
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| 310 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624); |
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| 311 | |
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| 312 | CYCLE(1); |
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| 313 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 314 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 315 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003); |
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| 316 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050); |
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| 317 | |
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| 318 | CYCLE(1); |
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| 319 | icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8); |
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| 320 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 321 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000); |
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| 322 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306); |
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| 323 | |
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| 324 | CYCLE(1); |
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| 325 | icache_signals [0][0].REQ_VAL .write(false); |
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| 326 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true); |
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| 327 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002); |
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| 328 | TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004); |
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| 329 | |
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| 330 | CYCLE(1); |
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| 331 | TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false); |
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| 332 | |
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| 333 | } |
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| 334 | { |
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| 335 | { |
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| 336 | CYCLE(50); |
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| 337 | |
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| 338 | cout << " -> Test of Dcache - Read" << endl; |
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| 339 | |
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| 340 | uint32_t daddr = 0x10000000; |
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| 341 | |
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| 342 | dcache_signals [0][0].REQ_VAL .write(true); |
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| 343 | dcache_signals [0][0].REQ_TRDID .write(1); |
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| 344 | dcache_signals [0][0].REQ_PKTID .write(0); |
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| 345 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
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| 346 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
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| 347 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
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| 348 | dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf); |
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| 349 | |
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| 350 | dcache_signals [0][0].RSP_ACK .write(false); |
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| 351 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
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| 352 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
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| 353 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
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| 354 | |
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| 355 | CYCLE(1); |
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| 356 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
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| 357 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
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| 358 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
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| 359 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
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| 360 | |
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| 361 | CYCLE(1); |
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| 362 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
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| 363 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16); |
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| 364 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
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| 365 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 366 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 367 | |
---|
| 368 | CYCLE(1); |
---|
| 369 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 370 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8); |
---|
| 371 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 372 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 373 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 374 | |
---|
| 375 | CYCLE(1); |
---|
| 376 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 377 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
---|
| 378 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 379 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 380 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 381 | |
---|
| 382 | CYCLE(1); |
---|
| 383 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 384 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 385 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 386 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 387 | |
---|
| 388 | CYCLE(1); |
---|
| 389 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 390 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 391 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 392 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 393 | |
---|
| 394 | CYCLE(1); |
---|
| 395 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 396 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false); |
---|
| 397 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 398 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 399 | |
---|
| 400 | CYCLE(1); |
---|
| 401 | dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8); |
---|
| 402 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false); |
---|
| 403 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 404 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 405 | |
---|
| 406 | CYCLE(1); |
---|
| 407 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 408 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false); |
---|
| 409 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 410 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 411 | |
---|
| 412 | CYCLE(19); |
---|
| 413 | |
---|
| 414 | dcache_signals [0][0].RSP_ACK .write(true ); |
---|
| 415 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 416 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false); |
---|
| 417 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 418 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 419 | |
---|
| 420 | CYCLE(1); |
---|
| 421 | |
---|
| 422 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 423 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573); |
---|
| 424 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false); |
---|
| 425 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 426 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 427 | |
---|
| 428 | CYCLE(1); |
---|
| 429 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 430 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x745f696e); |
---|
| 431 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true ); |
---|
| 432 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false); |
---|
| 433 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 434 | |
---|
| 435 | CYCLE(1); |
---|
| 436 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 437 | printf("%.8x\n",(uint32_t)dcache_signals [0][0].RSP_RDATA .read()); |
---|
| 438 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74657465); |
---|
| 439 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true ); |
---|
| 440 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true ); |
---|
| 441 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false); |
---|
| 442 | |
---|
| 443 | CYCLE(1); |
---|
| 444 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 445 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x69696969); |
---|
| 446 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true ); |
---|
| 447 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true ); |
---|
| 448 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true ); |
---|
| 449 | |
---|
| 450 | CYCLE(1); |
---|
| 451 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 452 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x20546573); |
---|
| 453 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true ); |
---|
| 454 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true ); |
---|
| 455 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true ); |
---|
| 456 | |
---|
| 457 | CYCLE(1); |
---|
| 458 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 459 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74206973); |
---|
| 460 | |
---|
| 461 | CYCLE(1); |
---|
| 462 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 463 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x204b6f00); |
---|
| 464 | |
---|
| 465 | CYCLE(1); |
---|
| 466 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 467 | } |
---|
| 468 | { |
---|
| 469 | CYCLE(50); |
---|
| 470 | |
---|
| 471 | cout << " -> Test of Dcache - Write" << endl; |
---|
| 472 | |
---|
| 473 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 474 | dcache_signals [0][0].REQ_TRDID .write(1); |
---|
| 475 | dcache_signals [0][0].REQ_PKTID .write(0); |
---|
| 476 | dcache_signals [0][0].REQ_ADDR .write(0x10000000); |
---|
| 477 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 478 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
---|
| 479 | dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf); |
---|
| 480 | |
---|
| 481 | CYCLE(1); |
---|
| 482 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 483 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573); |
---|
| 484 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE); |
---|
| 485 | |
---|
| 486 | CYCLE(1); |
---|
| 487 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 488 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ ); |
---|
| 489 | |
---|
| 490 | CYCLE(1); |
---|
| 491 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 492 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0xdeadbeaf); |
---|
| 493 | dcache_signals [0][0].REQ_ADDR .write(0x10000000); |
---|
| 494 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE); |
---|
| 495 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16); |
---|
| 496 | dcache_signals [0][0].REQ_WDATA .write(0x0bad0bad); |
---|
| 497 | |
---|
| 498 | CYCLE(1); |
---|
| 499 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 500 | dcache_signals [0][0].REQ_ADDR .write(0x10000000); |
---|
| 501 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 502 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
---|
| 503 | |
---|
| 504 | CYCLE(1); |
---|
| 505 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 506 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbeaf); |
---|
| 507 | dcache_signals [0][0].REQ_ADDR .write(0x10000002); |
---|
| 508 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK); |
---|
| 509 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16); |
---|
| 510 | dcache_signals [0][0].REQ_WDATA .write(0xbebebebe); |
---|
| 511 | |
---|
| 512 | CYCLE(1); |
---|
| 513 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 514 | dcache_signals [0][0].REQ_ADDR .write(0x10000000); |
---|
| 515 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 516 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
---|
| 517 | |
---|
| 518 | CYCLE(1); |
---|
| 519 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 520 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true); |
---|
| 521 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbebe); |
---|
| 522 | |
---|
| 523 | CYCLE(1); |
---|
| 524 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 525 | |
---|
| 526 | CYCLE(1); |
---|
| 527 | dcache_signals [0][0].RSP_ACK .write(false); |
---|
| 528 | } |
---|
| 529 | } |
---|
| 530 | { |
---|
| 531 | CYCLE(50); |
---|
| 532 | cout << " -> Test of TTY" << endl; |
---|
| 533 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 534 | dcache_signals [0][0].REQ_TRDID .write(1); |
---|
| 535 | dcache_signals [0][0].REQ_PKTID .write(0); |
---|
| 536 | dcache_signals [0][0].REQ_ADDR .write(0x60000000); |
---|
| 537 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE); |
---|
| 538 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8); |
---|
| 539 | dcache_signals [0][0].REQ_WDATA .write(0x30303030); |
---|
| 540 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 541 | |
---|
| 542 | CYCLE(1); |
---|
| 543 | dcache_signals [0][0].REQ_ADDR .write(0x60000004); |
---|
| 544 | |
---|
| 545 | CYCLE(1); |
---|
| 546 | dcache_signals [0][0].REQ_ADDR .write(0x60000010); |
---|
| 547 | dcache_signals [0][0].REQ_WDATA .write(0x31313131); |
---|
| 548 | |
---|
| 549 | CYCLE(1); |
---|
| 550 | dcache_signals [0][0].REQ_ADDR .write(0x60000110); |
---|
| 551 | dcache_signals [0][0].REQ_WDATA .write(0x32323232); |
---|
| 552 | |
---|
| 553 | CYCLE(1); |
---|
| 554 | dcache_signals [0][0].REQ_ADDR .write(0x60000128); |
---|
| 555 | dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf); |
---|
| 556 | |
---|
| 557 | CYCLE(1); |
---|
| 558 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 559 | } |
---|
| 560 | { |
---|
| 561 | CYCLE(50); |
---|
| 562 | cout << " -> Test of RAMLOCK" << endl; |
---|
| 563 | dcache_signals [0][0].RSP_ACK .write(true ); |
---|
| 564 | dcache_signals [0][1].RSP_ACK .write(true ); |
---|
| 565 | dcache_signals [0][2].RSP_ACK .write(true ); |
---|
| 566 | |
---|
| 567 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 568 | dcache_signals [0][0].REQ_TRDID .write(1); |
---|
| 569 | dcache_signals [0][0].REQ_PKTID .write(0); |
---|
| 570 | dcache_signals [0][0].REQ_ADDR .write(0x8000000C); |
---|
| 571 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 572 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8); |
---|
| 573 | dcache_signals [0][0].REQ_WDATA .write(0); |
---|
| 574 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 575 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 576 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 577 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 578 | |
---|
| 579 | CYCLE(1); |
---|
| 580 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 581 | |
---|
| 582 | CYCLE(28); |
---|
| 583 | |
---|
| 584 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 585 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 586 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 587 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK); |
---|
| 588 | |
---|
| 589 | CYCLE(1); |
---|
| 590 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 591 | dcache_signals [0][0].REQ_ADDR .write(0x8000000C); |
---|
| 592 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 593 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 594 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 595 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 596 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 597 | |
---|
| 598 | CYCLE(1); |
---|
| 599 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 600 | |
---|
| 601 | CYCLE(28); |
---|
| 602 | |
---|
| 603 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 604 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 605 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 606 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK); |
---|
| 607 | |
---|
| 608 | CYCLE(1); |
---|
| 609 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 610 | dcache_signals [0][0].REQ_ADDR .write(0x8000000C); |
---|
| 611 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK); |
---|
| 612 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 613 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 614 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 615 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 616 | |
---|
| 617 | CYCLE(1); |
---|
| 618 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 619 | |
---|
| 620 | CYCLE(28); |
---|
| 621 | |
---|
| 622 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 623 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 624 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 625 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK); |
---|
| 626 | |
---|
| 627 | CYCLE(1); |
---|
| 628 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 629 | dcache_signals [0][0].REQ_ADDR .write(0x8000000C); |
---|
| 630 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK); |
---|
| 631 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 632 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 633 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 634 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 635 | |
---|
| 636 | CYCLE(1); |
---|
| 637 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 638 | |
---|
| 639 | CYCLE(28); |
---|
| 640 | |
---|
| 641 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 642 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 643 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 644 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK); |
---|
| 645 | |
---|
| 646 | CYCLE(1); |
---|
| 647 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 648 | dcache_signals [0][0].REQ_ADDR .write(0x8000000C); |
---|
| 649 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ); |
---|
| 650 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 651 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 652 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 653 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 654 | |
---|
| 655 | CYCLE(1); |
---|
| 656 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 657 | |
---|
| 658 | CYCLE(28); |
---|
| 659 | |
---|
| 660 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 661 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 662 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 663 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK); |
---|
| 664 | |
---|
| 665 | CYCLE(1); |
---|
| 666 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 667 | dcache_signals [0][1].REQ_VAL .write(true); |
---|
| 668 | dcache_signals [0][2].REQ_VAL .write(true); |
---|
| 669 | dcache_signals [0][0].REQ_ADDR .write(0x8000000E); |
---|
| 670 | dcache_signals [0][1].REQ_ADDR .write(0x8000000E); |
---|
| 671 | dcache_signals [0][2].REQ_ADDR .write(0x8000000E); |
---|
| 672 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ ); |
---|
| 673 | dcache_signals [0][1].REQ_TYPE .write(DTYPE_READ ); |
---|
| 674 | dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ ); |
---|
| 675 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 676 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 677 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 678 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 679 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 680 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 681 | |
---|
| 682 | CYCLE(1); |
---|
| 683 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 684 | dcache_signals [0][1].REQ_VAL .write(false); |
---|
| 685 | dcache_signals [0][2].REQ_VAL .write(false); |
---|
| 686 | |
---|
| 687 | CYCLE(28); |
---|
| 688 | |
---|
| 689 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 690 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),true ); |
---|
| 691 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),true ); |
---|
| 692 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK); |
---|
| 693 | TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK); |
---|
| 694 | TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),LOCK); |
---|
| 695 | |
---|
| 696 | CYCLE(1); |
---|
| 697 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 698 | dcache_signals [0][1].REQ_VAL .write(true); |
---|
| 699 | dcache_signals [0][2].REQ_VAL .write(true); |
---|
| 700 | dcache_signals [0][0].REQ_ADDR .write(0x8000000E); |
---|
| 701 | dcache_signals [0][1].REQ_ADDR .write(0x8000000E); |
---|
| 702 | dcache_signals [0][2].REQ_ADDR .write(0x8000000E); |
---|
| 703 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ ); |
---|
| 704 | dcache_signals [0][1].REQ_TYPE .write(DTYPE_WRITE_ACK); |
---|
| 705 | dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ ); |
---|
| 706 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 707 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 708 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 709 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 710 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 711 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 712 | |
---|
| 713 | CYCLE(1); |
---|
| 714 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 715 | dcache_signals [0][1].REQ_VAL .write(false); |
---|
| 716 | dcache_signals [0][2].REQ_VAL .write(false); |
---|
| 717 | |
---|
| 718 | CYCLE(28); |
---|
| 719 | |
---|
| 720 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 721 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),true ); |
---|
| 722 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),true ); |
---|
| 723 | TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK); |
---|
| 724 | TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK); |
---|
| 725 | TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),UNLOCK); |
---|
| 726 | } |
---|
| 727 | |
---|
| 728 | { |
---|
| 729 | CYCLE(50); |
---|
| 730 | cout << " -> Test of SIM2OS" << endl; |
---|
| 731 | |
---|
| 732 | dcache_signals [0][0].RSP_ACK .write(true ); |
---|
| 733 | dcache_signals [0][1].RSP_ACK .write(true ); |
---|
| 734 | dcache_signals [0][2].RSP_ACK .write(true ); |
---|
| 735 | |
---|
| 736 | dcache_signals [0][0].REQ_VAL .write(true); |
---|
| 737 | dcache_signals [0][0].REQ_TRDID .write(1); |
---|
| 738 | dcache_signals [0][0].REQ_PKTID .write(0); |
---|
| 739 | dcache_signals [0][0].REQ_ADDR .write(0x7000000C); |
---|
| 740 | dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE); |
---|
| 741 | dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32); |
---|
| 742 | dcache_signals [0][0].REQ_WDATA .write(0x10000004); |
---|
| 743 | TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true); |
---|
| 744 | |
---|
| 745 | dcache_signals [0][1].REQ_VAL .write(true); |
---|
| 746 | dcache_signals [0][1].REQ_TRDID .write(1); |
---|
| 747 | dcache_signals [0][1].REQ_PKTID .write(0); |
---|
| 748 | dcache_signals [0][1].REQ_ADDR .write(0x70000000); |
---|
| 749 | dcache_signals [0][1].REQ_TYPE .write(DTYPE_WRITE); |
---|
| 750 | dcache_signals [0][1].REQ_ACCESS.write(ACCESS_32); |
---|
| 751 | dcache_signals [0][1].REQ_WDATA .write(SERVICE_TIME); |
---|
| 752 | |
---|
| 753 | TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true); |
---|
| 754 | |
---|
| 755 | dcache_signals [0][2].REQ_VAL .write(true); |
---|
| 756 | dcache_signals [0][2].REQ_TRDID .write(1); |
---|
| 757 | dcache_signals [0][2].REQ_PKTID .write(0); |
---|
| 758 | dcache_signals [0][2].REQ_ADDR .write(0x70000004); |
---|
| 759 | dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ); |
---|
| 760 | dcache_signals [0][2].REQ_ACCESS.write(ACCESS_32); |
---|
| 761 | dcache_signals [0][2].REQ_WDATA .write(SERVICE_TIME); |
---|
| 762 | |
---|
| 763 | TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true); |
---|
| 764 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false); |
---|
| 765 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 766 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 767 | |
---|
| 768 | CYCLE(1); |
---|
| 769 | dcache_signals [0][0].REQ_VAL .write(false); |
---|
| 770 | dcache_signals [0][1].REQ_VAL .write(false); |
---|
| 771 | dcache_signals [0][2].REQ_VAL .write(false); |
---|
| 772 | CYCLE(28); |
---|
| 773 | |
---|
| 774 | TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true ); |
---|
| 775 | TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false); |
---|
| 776 | TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false); |
---|
| 777 | } |
---|
| 778 | //cout << *memory << endl; test_ok(); |
---|
| 779 | // CYCLE(1); |
---|
| 780 | |
---|
| 781 | cout << "Press a key to quit the test" << endl; |
---|
| 782 | getchar(); |
---|
| 783 | delete memory; |
---|
| 784 | test_ok (); |
---|
| 785 | |
---|
| 786 | return 1; |
---|
| 787 | }; |
---|