#include "hierarchy_memory.h" #include #include #define TEXT_BASE 0x00000000 #define TEXT_SIZE 0x00005000 #define DATA_CACHED_BASE 0x10000000 #define DATA_CACHED_SIZE 0x00000100 #define DATA_UNCACHED_BASE 0x40000000 #define DATA_UNCACHED_SIZE 0x00000100 #define STACK_BASE 0x50000000 #define STACK_SIZE 0x00000200 #define TTY1_BASE 0x60000000 #define TTY1_SIZE 0x00000100 #define TTY2_BASE 0x60000100 #define TTY2_SIZE 0x00000200 #define SIM2OS_BASE 0x70000000 #define SIM2OS_SIZE 0x00000100 #define RAMLOCK_BASE 0x80000000 #define RAMLOCK_SIZE 0x00000100 // using namespace hierarchy_memory::data; using namespace std; using namespace hierarchy_memory; //-----[ Routine de test ]--------------------------------------- void test_ko (char * file, uint32_t line) { cerr << "***** Test KO *****" << endl << " - File : " << file << endl << " - Line : " << line << endl; exit (line); }; void test_ok () { cout << "***** Test OK *****" << endl; exit (0); }; template void test(T exp1, T exp2, char * file, uint32_t line) { if (exp1 != exp2) { cerr << "Expression is different : " << endl << " - exp1 : " << exp1 << endl << " - exp2 : " << exp2 << endl; test_ko (file,line); } }; #define TEST(type,exp1,exp2) do { test (exp1,exp2,__FILE__,__LINE__);} while(0) int sc_main(int argc, char* argv[]) { cout << "
Test de \"HIERARCHY_MEMORY\"" << endl; /********************************************************************* * Declarations des constantes *********************************************************************/ const uint32_t nb_context = 6; const uint32_t nb_cluster = 2; const uint32_t nb_iport = 1; const uint32_t nb_dport = 3; const uint32_t size_trdid = 5; const uint32_t size_ipktid = 4; const uint32_t size_iaddr = 32; const uint32_t size_idata = 32; const uint32_t nb_iword = 2; const uint32_t size_dpktid = 2; const uint32_t size_daddr = 32; const uint32_t size_ddata = 32; const uint32_t size_buffer_irsp = 9; const uint32_t size_buffer_drsp = 7; /********************************************************************* * Declarations des signaux *********************************************************************/ cout << " * Declaration of signals" << endl; sc_clock CLK ("clock",1,0.5); sc_signal NRESET; ICACHE_SIGNALS ** icache_signals; DCACHE_SIGNALS ** dcache_signals; icache_signals = new ICACHE_SIGNALS * [nb_cluster]; dcache_signals = new DCACHE_SIGNALS * [nb_cluster]; for (uint32_t x = 0; x < nb_cluster; x ++) { icache_signals[x] = new ICACHE_SIGNALS [nb_iport]; dcache_signals[x] = new DCACHE_SIGNALS [nb_dport]; } /********************************************************************* * Segmentation table *********************************************************************/ cout << " * Segment_table" << endl; SOCLIB_SEGMENT_TABLE segtable; segtable.setMSBNumber (8); segtable.setDefaultTarget(0,0); // Add a segment :name , address of base , size , global index , local index, uncache segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false); segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false); segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true ); segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false); segtable.addSegment("tty1" , TTY1_BASE , TTY1_SIZE , 0 ,0 , true ); segtable.addSegment("tty2" , TTY2_BASE , TTY2_SIZE , 0 ,0 , true ); segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true ); segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true ); const char * sections_text [] = {".text",NULL}; const char * sections_data [] = {".data",".rodata",".sdata",".sbss",".bss", NULL}; const char * sections_stack [] = {".stack",NULL}; const char * filename = "soft.x"; /********************************************************************* * Declaration of component *********************************************************************/ char * name_tty1[nb_context/2] = { "tty_0", "tty_1", "tty_2"}; char * name_tty2[nb_context/2] = { "tty_3", "tty_4", "tty_5"}; // nb_line, size_line, size_word, associativity, hit_latence, miss_penality #define L1_ICACHE "L1_ICACHE", 4, 2, 4, 4, 1, 4 #define L1_DCACHE "L1_DCACHE", 4, 2, 4, 4, 1, 4 #define L2_CACHE "L2_CACHE", 8, 4, 4, 2, 2, 7 #define L3_CACHE "L3_CACHE", 16, 8, 4, 1, 3, 12 param_cache_t param_icache_1 [1] = { param_cache_t (L1_ICACHE) }; param_cache_t param_dcache_1 [1] = { param_cache_t (L1_DCACHE) }; param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) , param_cache_t (L3_CACHE) }; cache::cache_multilevel::param_t param_icache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_icache_dedicated[0]",1, nb_iport, param_icache_1), cache::cache_multilevel::param_t ("param_icache_dedicated[1]",1, nb_iport, param_icache_1), }; cache::cache_multilevel::param_t param_dcache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_dcache_dedicated[0]",1, nb_dport, param_dcache_1), cache::cache_multilevel::param_t ("param_dcache_dedicated[1]",1, nb_dport, param_dcache_1), }; cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",2, nb_cluster*(nb_iport+nb_dport), param_cache_2); cache::param_t param_cache ("cache" , nb_cluster , param_icache_dedicated, param_dcache_dedicated, param_cache_shared ); param_entity_t param_tty [2] = {param_entity_t (TTY1_BASE , TTY1_SIZE , tty::param_t ("tty1" , nb_context/2, name_tty1,true)), param_entity_t (TTY2_BASE , TTY2_SIZE , tty::param_t ("tty2" , nb_context/2, name_tty2,true))}; param_entity_t param_ramlock [1] = {param_entity_t(RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))}; param_entity_t param_sim2os = param_entity_t(SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable)); #define PARAM_MEMORY 2,param_tty,1,param_ramlock,param_sim2os,param_cache #define PARAM "memory", 0,0, &segtable,nb_cluster, nb_context,size_buffer_irsp, size_buffer_drsp, hierarchy_memory::param_t(PARAM_MEMORY) #define TEMPLATE size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword, size_dpktid, size_daddr, size_ddata HIERARCHY_MEMORY