Context Navigation

source: trunk/IPs/systemC/hierarchy_memory/main.cpp @ 19

Last change on this file since 19 was 2, checked in by kane, 18 years ago
Import Morpheo
File size: 34.1 KB

Line
1	#include "hierarchy_memory.h"
2	#include <systemc.h>
3	#include <iostream>
4
5	#define TEXT_BASE 0x00000000
6	#define TEXT_SIZE 0x00005000
7
8	#define DATA_CACHED_BASE 0x10000000
9	#define DATA_CACHED_SIZE 0x00000100
10
11	#define DATA_UNCACHED_BASE 0x40000000
12	#define DATA_UNCACHED_SIZE 0x00000100
13
14	#define STACK_BASE 0x50000000
15	#define STACK_SIZE 0x00000200
16
17	#define TTY1_BASE 0x60000000
18	#define TTY1_SIZE 0x00000100
19
20	#define TTY2_BASE 0x60000100
21	#define TTY2_SIZE 0x00000200
22
23	#define SIM2OS_BASE 0x70000000
24	#define SIM2OS_SIZE 0x00000100
25
26	#define RAMLOCK_BASE 0x80000000
27	#define RAMLOCK_SIZE 0x00000100
28
29	// using namespace hierarchy_memory::data;
30	using namespace std;
31	using namespace hierarchy_memory;
32
33	//-----[ Routine de test ]---------------------------------------
34
35	void test_ko (char * file, uint32_t line)
36	{
37	cerr << "*** Test KO ***" << endl
38	<< " - File : " << file << endl
39	<< " - Line : " << line << endl;
40	exit (line);
41	};
42
43	void test_ok ()
44	{
45	cout << "*** Test OK ***" << endl;
46	exit (0);
47	};
48
49	template <class T>
50	void test(T exp1, T exp2, char * file, uint32_t line)
51	{
52	if (exp1 != exp2)
53	{
54	cerr << "Expression is different : " << endl
55	<< " - exp1 : " << exp1 << endl
56	<< " - exp2 : " << exp2 << endl;
57
58	test_ko (file,line);
59	}
60	};
61
62	#define TEST(type,exp1,exp2) do { test<type> (exp1,exp2,__FILE__,__LINE__);} while(0)
63
64	int sc_main(int argc, char* argv[])
65	{
66	cout << "<main> Test de \"HIERARCHY_MEMORY\"" << endl;
67
68	/*********************************************************************
69	* Declarations des constantes
70	*********************************************************************/
71	const uint32_t nb_context = 6;
72	const uint32_t nb_cluster = 2;
73	const uint32_t nb_iport = 1;
74	const uint32_t nb_dport = 3;
75	const uint32_t size_trdid = 5;
76	const uint32_t size_ipktid = 4;
77	const uint32_t size_iaddr = 32;
78	const uint32_t size_idata = 32;
79	const uint32_t nb_iword = 2;
80	const uint32_t size_dpktid = 2;
81	const uint32_t size_daddr = 32;
82	const uint32_t size_ddata = 32;
83
84	const uint32_t size_buffer_irsp = 9;
85	const uint32_t size_buffer_drsp = 7;
86	/*********************************************************************
87	* Declarations des signaux
88	*********************************************************************/
89	cout << " * Declaration of signals" << endl;
90	sc_clock CLK ("clock",1,0.5);
91	sc_signal<bool> NRESET;
92
93	ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> ** icache_signals;
94	DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> ** dcache_signals;
95
96	icache_signals = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> * [nb_cluster];
97	dcache_signals = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> * [nb_cluster];
98
99	for (uint32_t x = 0; x < nb_cluster; x ++)
100	{
101	icache_signals[x] = new ICACHE_SIGNALS <size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword> [nb_iport];
102	dcache_signals[x] = new DCACHE_SIGNALS <size_trdid, size_dpktid, size_daddr, size_ddata> [nb_dport];
103	}
104
105	/*********************************************************************
106	* Segmentation table
107	*********************************************************************/
108	cout << " * Segment_table" << endl;
109
110	SOCLIB_SEGMENT_TABLE segtable;
111	segtable.setMSBNumber (8);
112	segtable.setDefaultTarget(0,0);
113
114	// Add a segment :name , address of base , size , global index , local index, uncache
115	segtable.addSegment("text" , TEXT_BASE , TEXT_SIZE , 0 ,0 , false);
116	segtable.addSegment("data" , DATA_CACHED_BASE , DATA_CACHED_SIZE , 0 ,0 , false);
117	segtable.addSegment("data_unc" , DATA_UNCACHED_BASE , DATA_UNCACHED_SIZE , 0 ,0 , true );
118	segtable.addSegment("stack" , STACK_BASE , STACK_SIZE , 0 ,0 , false);
119	segtable.addSegment("tty1" , TTY1_BASE , TTY1_SIZE , 0 ,0 , true );
120	segtable.addSegment("tty2" , TTY2_BASE , TTY2_SIZE , 0 ,0 , true );
121	segtable.addSegment("sim2os" , SIM2OS_BASE , SIM2OS_SIZE , 0 ,0 , true );
122	segtable.addSegment("ramlock" , RAMLOCK_BASE , RAMLOCK_SIZE , 0 ,0 , true );
123
124	const char * sections_text [] = {".text",NULL};
125	const char * sections_data [] = {".data",".rodata",".sdata",".sbss",".bss", NULL};
126	const char * sections_stack [] = {".stack",NULL};
127	const char * filename = "soft.x";
128
129	/*********************************************************************
130	* Declaration of component
131	*********************************************************************/
132	char * name_tty1[nb_context/2] = { "tty_0",
133	"tty_1",
134	"tty_2"};
135
136	char * name_tty2[nb_context/2] = { "tty_3",
137	"tty_4",
138	"tty_5"};
139
140	// nb_line, size_line, size_word, associativity, hit_latence, miss_penality
141	#define L1_ICACHE "L1_ICACHE", 4, 2, 4, 4, 1, 4
142	#define L1_DCACHE "L1_DCACHE", 4, 2, 4, 4, 1, 4
143	#define L2_CACHE "L2_CACHE", 8, 4, 4, 2, 2, 7
144	#define L3_CACHE "L3_CACHE", 16, 8, 4, 1, 3, 12
145
146	param_cache_t param_icache_1 [1] = { param_cache_t (L1_ICACHE) };
147	param_cache_t param_dcache_1 [1] = { param_cache_t (L1_DCACHE) };
148	param_cache_t param_cache_2 [2] = { param_cache_t (L2_CACHE) ,
149	param_cache_t (L3_CACHE) };
150
151	cache::cache_multilevel::param_t param_icache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_icache_dedicated[0]",1, nb_iport, param_icache_1),
152	cache::cache_multilevel::param_t ("param_icache_dedicated[1]",1, nb_iport, param_icache_1),
153	};
154
155	cache::cache_multilevel::param_t param_dcache_dedicated [nb_cluster] = {cache::cache_multilevel::param_t ("param_dcache_dedicated[0]",1, nb_dport, param_dcache_1),
156	cache::cache_multilevel::param_t ("param_dcache_dedicated[1]",1, nb_dport, param_dcache_1),
157	};
158
159	cache::cache_multilevel::param_t param_cache_shared ("param_cache_shared",2, nb_cluster*(nb_iport+nb_dport), param_cache_2);
160
161	cache::param_t param_cache ("cache" ,
162	nb_cluster ,
163	param_icache_dedicated,
164	param_dcache_dedicated,
165	param_cache_shared );
166	param_entity_t<tty::param_t> param_tty [2] = {param_entity_t<tty::param_t> (TTY1_BASE , TTY1_SIZE , tty::param_t ("tty1" , nb_context/2, name_tty1,true)),
167	param_entity_t<tty::param_t> (TTY2_BASE , TTY2_SIZE , tty::param_t ("tty2" , nb_context/2, name_tty2,true))};
168	param_entity_t<ramlock::param_t> param_ramlock [1] = {param_entity_t<ramlock::param_t>(RAMLOCK_BASE, RAMLOCK_SIZE, ramlock::param_t("ramlock", RAMLOCK_SIZE))};
169
170
171	param_entity_t<sim2os::param_t> param_sim2os = param_entity_t<sim2os::param_t>(SIM2OS_BASE, SIM2OS_SIZE, sim2os::param_t("sim2os",&segtable));
172
173	#define PARAM_MEMORY 2,param_tty,1,param_ramlock,param_sim2os,param_cache
174	#define PARAM "memory", 0,0, &segtable,nb_cluster, nb_context,size_buffer_irsp, size_buffer_drsp, hierarchy_memory::param_t(PARAM_MEMORY)
175	#define TEMPLATE size_trdid, size_ipktid, size_iaddr, size_idata, nb_iword, size_dpktid, size_daddr, size_ddata
176
177	HIERARCHY_MEMORY <TEMPLATE> * memory = new HIERARCHY_MEMORY <TEMPLATE> (PARAM);
178
179	/*********************************************************************
180	* Instanciation
181	*********************************************************************/
182	memory->CLK (CLK);
183	memory->NRESET (NRESET);
184
185	for (uint32_t x = 0; x < nb_cluster; x ++)
186	{
187	for (uint32_t y = 0; y < nb_iport; y ++)
188	memory->ICACHE[x][y] (icache_signals [x][y]);
189	for (uint32_t y = 0; y < nb_dport; y ++)
190	memory->DCACHE[x][y] (dcache_signals [x][y]);
191	}
192
193	cout << " * Create a HIERARCHY_MEMORY" << endl;
194
195	TEST(bool,memory->init("text" , filename, sections_text) ,true);
196	TEST(bool,memory->init("stack" , filename, sections_stack),true);
197	TEST(bool,memory->init("data" , filename, sections_data) ,true);
198
199	/********************************************************
200	* Simulation - Begin
201	********************************************************/
202
203	cout << " * simulation" << endl;
204	// Initialisation
205	sc_start(0);
206
207	// Init control signal
208	for (uint32_t x = 0; x < nb_cluster; x ++)
209	{
210	for (uint32_t y = 0; y < nb_iport; y ++)
211	{
212	icache_signals [x][y].REQ_VAL.write (false);
213	icache_signals [x][y].RSP_ACK.write (false);
214	}
215	for (uint32_t y = 0; y < nb_dport; y ++)
216	{
217	dcache_signals [x][y].REQ_VAL.write (false);
218	dcache_signals [x][y].RSP_ACK.write (false);
219	}
220	}
221
222	// Reset
223	uint32_t iaddr = 0x2000;
224
225	#define CYCLE(n) do {sc_start(n); cout << "***{ " << setw(5) << (uint32_t) sc_simulation_time() << " }***" << endl;} while(0)
226	#define NEXT_CYCLE() do {CYCLE(1); getchar();} while(0)
227
228	NRESET.write(false);
229	CYCLE(5);
230	NRESET.write(true);
231
232	{
233	cout << " -> Test of Icache" << endl;
234	iaddr = 0x100;
235	icache_signals [0][0].REQ_VAL .write(true);
236	icache_signals [0][0].REQ_TRDID.write(1);
237	icache_signals [0][0].REQ_PKTID.write(0);
238	icache_signals [0][0].REQ_ADDR .write(iaddr);
239	icache_signals [0][0].REQ_TYPE .write(ITYPE_READ);
240
241	icache_signals [0][0].RSP_ACK .write(false);
242
243	CYCLE(1);
244	iaddr = 0x2000;
245	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
246
247	CYCLE(1);
248	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
249
250	CYCLE(1);
251	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
252
253	CYCLE(1);
254	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
255
256	CYCLE(1);
257	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
258
259	CYCLE(1);
260
261	icache_signals [0][0].REQ_VAL .write(false);
262
263	CYCLE(22);
264
265	icache_signals [0][0].RSP_ACK .write(true );
266	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false);
267
268	CYCLE(1);
269	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
270	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x18400000);
271	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa8422000);
272
273	CYCLE(1);
274	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
275	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x182051ff);
276	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xa821fffc);
277
278	CYCLE(1);
279	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
280	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd);
281	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624);
282
283	CYCLE(1);
284	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
285	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003);
286	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050);
287
288	CYCLE(1);
289	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
290	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000);
291	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306);
292
293	CYCLE(1);
294	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
295	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002);
296	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004);
297
298	CYCLE(1);
299	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false);
300
301	iaddr = 0x2008;
302	icache_signals [0][0].REQ_VAL .write(true);
303	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
304
305	CYCLE(1);
306	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
307
308	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
309	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0x9c40fffd);
310	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x04000624);
311
312	CYCLE(1);
313	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
314	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
315	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0211003);
316	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0x18800050);
317
318	CYCLE(1);
319	icache_signals [0][0].REQ_ADDR .write(iaddr); iaddr += nb_iword*(size_idata/8);
320	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
321	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xa8840000);
322	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe08b2306);
323
324	CYCLE(1);
325	icache_signals [0][0].REQ_VAL .write(false);
326	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),true);
327	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[0].read(),0xe0212002);
328	TEST(sc_uint<size_idata>,icache_signals [0][0].RSP_INS[1].read(),0xe0410004);
329
330	CYCLE(1);
331	TEST(bool ,icache_signals [0][0].RSP_VAL .read(),false);
332
333	}
334	{
335	{
336	CYCLE(50);
337
338	cout << " -> Test of Dcache - Read" << endl;
339
340	uint32_t daddr = 0x10000000;
341
342	dcache_signals [0][0].REQ_VAL .write(true);
343	dcache_signals [0][0].REQ_TRDID .write(1);
344	dcache_signals [0][0].REQ_PKTID .write(0);
345	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
346	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
347	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
348	dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
349
350	dcache_signals [0][0].RSP_ACK .write(false);
351	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
352	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
353	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
354
355	CYCLE(1);
356	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
357	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
358	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
359	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
360
361	CYCLE(1);
362	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
363	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
364	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
365	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
366	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
367
368	CYCLE(1);
369	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
370	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
371	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
372	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
373	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
374
375	CYCLE(1);
376	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
377	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
378	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
379	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
380	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
381
382	CYCLE(1);
383	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
384	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
385	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
386	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
387
388	CYCLE(1);
389	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
390	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
391	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
392	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
393
394	CYCLE(1);
395	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
396	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false);
397	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
398	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
399
400	CYCLE(1);
401	dcache_signals [0][0].REQ_ADDR .write(daddr); daddr += (size_ddata/8);
402	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false);
403	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
404	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
405
406	CYCLE(1);
407	dcache_signals [0][0].REQ_VAL .write(false);
408	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false);
409	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
410	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
411
412	CYCLE(19);
413
414	dcache_signals [0][0].RSP_ACK .write(true );
415	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
416	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false);
417	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
418	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
419
420	CYCLE(1);
421
422	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
423	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573);
424	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),false);
425	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
426	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
427
428	CYCLE(1);
429	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
430	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x745f696e);
431	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true );
432	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),false);
433	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
434
435	CYCLE(1);
436	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
437	printf("%.8x\n",(uint32_t)dcache_signals [0][0].RSP_RDATA .read());
438	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74657465);
439	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true );
440	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true );
441	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),false);
442
443	CYCLE(1);
444	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
445	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x69696969);
446	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true );
447	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true );
448	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true );
449
450	CYCLE(1);
451	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
452	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x20546573);
453	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true );
454	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true );
455	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true );
456
457	CYCLE(1);
458	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
459	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x74206973);
460
461	CYCLE(1);
462	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
463	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x204b6f00);
464
465	CYCLE(1);
466	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
467	}
468	{
469	CYCLE(50);
470
471	cout << " -> Test of Dcache - Write" << endl;
472
473	dcache_signals [0][0].REQ_VAL .write(true);
474	dcache_signals [0][0].REQ_TRDID .write(1);
475	dcache_signals [0][0].REQ_PKTID .write(0);
476	dcache_signals [0][0].REQ_ADDR .write(0x10000000);
477	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
478	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
479	dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
480
481	CYCLE(1);
482	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
483	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x3c746573);
484	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE);
485
486	CYCLE(1);
487	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
488	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ );
489
490	CYCLE(1);
491	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
492	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0xdeadbeaf);
493	dcache_signals [0][0].REQ_ADDR .write(0x10000000);
494	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE);
495	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
496	dcache_signals [0][0].REQ_WDATA .write(0x0bad0bad);
497
498	CYCLE(1);
499	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
500	dcache_signals [0][0].REQ_ADDR .write(0x10000000);
501	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
502	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
503
504	CYCLE(1);
505	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
506	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbeaf);
507	dcache_signals [0][0].REQ_ADDR .write(0x10000002);
508	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK);
509	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_16);
510	dcache_signals [0][0].REQ_WDATA .write(0xbebebebe);
511
512	CYCLE(1);
513	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
514	dcache_signals [0][0].REQ_ADDR .write(0x10000000);
515	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
516	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
517
518	CYCLE(1);
519	dcache_signals [0][0].REQ_VAL .write(false);
520	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true);
521	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),0x0badbebe);
522
523	CYCLE(1);
524	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
525
526	CYCLE(1);
527	dcache_signals [0][0].RSP_ACK .write(false);
528	}
529	}
530	{
531	CYCLE(50);
532	cout << " -> Test of TTY" << endl;
533	dcache_signals [0][0].REQ_VAL .write(true);
534	dcache_signals [0][0].REQ_TRDID .write(1);
535	dcache_signals [0][0].REQ_PKTID .write(0);
536	dcache_signals [0][0].REQ_ADDR .write(0x60000000);
537	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE);
538	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
539	dcache_signals [0][0].REQ_WDATA .write(0x30303030);
540	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
541
542	CYCLE(1);
543	dcache_signals [0][0].REQ_ADDR .write(0x60000004);
544
545	CYCLE(1);
546	dcache_signals [0][0].REQ_ADDR .write(0x60000010);
547	dcache_signals [0][0].REQ_WDATA .write(0x31313131);
548
549	CYCLE(1);
550	dcache_signals [0][0].REQ_ADDR .write(0x60000110);
551	dcache_signals [0][0].REQ_WDATA .write(0x32323232);
552
553	CYCLE(1);
554	dcache_signals [0][0].REQ_ADDR .write(0x60000128);
555	dcache_signals [0][0].REQ_WDATA .write(0xdeadbeaf);
556
557	CYCLE(1);
558	dcache_signals [0][0].REQ_VAL .write(false);
559	}
560	{
561	CYCLE(50);
562	cout << " -> Test of RAMLOCK" << endl;
563	dcache_signals [0][0].RSP_ACK .write(true );
564	dcache_signals [0][1].RSP_ACK .write(true );
565	dcache_signals [0][2].RSP_ACK .write(true );
566
567	dcache_signals [0][0].REQ_VAL .write(true);
568	dcache_signals [0][0].REQ_TRDID .write(1);
569	dcache_signals [0][0].REQ_PKTID .write(0);
570	dcache_signals [0][0].REQ_ADDR .write(0x8000000C);
571	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
572	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_8);
573	dcache_signals [0][0].REQ_WDATA .write(0);
574	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
575	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
576	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
577	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
578
579	CYCLE(1);
580	dcache_signals [0][0].REQ_VAL .write(false);
581
582	CYCLE(28);
583
584	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
585	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
586	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
587	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
588
589	CYCLE(1);
590	dcache_signals [0][0].REQ_VAL .write(true);
591	dcache_signals [0][0].REQ_ADDR .write(0x8000000C);
592	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
593	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
594	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
595	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
596	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
597
598	CYCLE(1);
599	dcache_signals [0][0].REQ_VAL .write(false);
600
601	CYCLE(28);
602
603	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
604	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
605	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
606	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
607
608	CYCLE(1);
609	dcache_signals [0][0].REQ_VAL .write(true);
610	dcache_signals [0][0].REQ_ADDR .write(0x8000000C);
611	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK);
612	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
613	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
614	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
615	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
616
617	CYCLE(1);
618	dcache_signals [0][0].REQ_VAL .write(false);
619
620	CYCLE(28);
621
622	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
623	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
624	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
625	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
626
627	CYCLE(1);
628	dcache_signals [0][0].REQ_VAL .write(true);
629	dcache_signals [0][0].REQ_ADDR .write(0x8000000C);
630	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE_ACK);
631	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
632	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
633	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
634	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
635
636	CYCLE(1);
637	dcache_signals [0][0].REQ_VAL .write(false);
638
639	CYCLE(28);
640
641	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
642	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
643	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
644	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
645
646	CYCLE(1);
647	dcache_signals [0][0].REQ_VAL .write(true);
648	dcache_signals [0][0].REQ_ADDR .write(0x8000000C);
649	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ);
650	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
651	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
652	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
653	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
654
655	CYCLE(1);
656	dcache_signals [0][0].REQ_VAL .write(false);
657
658	CYCLE(28);
659
660	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
661	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
662	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
663	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
664
665	CYCLE(1);
666	dcache_signals [0][0].REQ_VAL .write(true);
667	dcache_signals [0][1].REQ_VAL .write(true);
668	dcache_signals [0][2].REQ_VAL .write(true);
669	dcache_signals [0][0].REQ_ADDR .write(0x8000000E);
670	dcache_signals [0][1].REQ_ADDR .write(0x8000000E);
671	dcache_signals [0][2].REQ_ADDR .write(0x8000000E);
672	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ );
673	dcache_signals [0][1].REQ_TYPE .write(DTYPE_READ );
674	dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ );
675	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
676	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
677	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
678	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
679	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
680	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
681
682	CYCLE(1);
683	dcache_signals [0][0].REQ_VAL .write(false);
684	dcache_signals [0][1].REQ_VAL .write(false);
685	dcache_signals [0][2].REQ_VAL .write(false);
686
687	CYCLE(28);
688
689	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
690	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),true );
691	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),true );
692	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),UNLOCK);
693	TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK);
694	TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),LOCK);
695
696	CYCLE(1);
697	dcache_signals [0][0].REQ_VAL .write(true);
698	dcache_signals [0][1].REQ_VAL .write(true);
699	dcache_signals [0][2].REQ_VAL .write(true);
700	dcache_signals [0][0].REQ_ADDR .write(0x8000000E);
701	dcache_signals [0][1].REQ_ADDR .write(0x8000000E);
702	dcache_signals [0][2].REQ_ADDR .write(0x8000000E);
703	dcache_signals [0][0].REQ_TYPE .write(DTYPE_READ );
704	dcache_signals [0][1].REQ_TYPE .write(DTYPE_WRITE_ACK);
705	dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ );
706	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
707	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
708	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
709	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
710	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
711	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
712
713	CYCLE(1);
714	dcache_signals [0][0].REQ_VAL .write(false);
715	dcache_signals [0][1].REQ_VAL .write(false);
716	dcache_signals [0][2].REQ_VAL .write(false);
717
718	CYCLE(28);
719
720	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
721	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),true );
722	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),true );
723	TEST(sc_uint<size_ddata>,dcache_signals [0][0].RSP_RDATA .read(),LOCK);
724	TEST(sc_uint<size_ddata>,dcache_signals [0][1].RSP_RDATA .read(),LOCK);
725	TEST(sc_uint<size_ddata>,dcache_signals [0][2].RSP_RDATA .read(),UNLOCK);
726	}
727
728	{
729	CYCLE(50);
730	cout << " -> Test of SIM2OS" << endl;
731
732	dcache_signals [0][0].RSP_ACK .write(true );
733	dcache_signals [0][1].RSP_ACK .write(true );
734	dcache_signals [0][2].RSP_ACK .write(true );
735
736	dcache_signals [0][0].REQ_VAL .write(true);
737	dcache_signals [0][0].REQ_TRDID .write(1);
738	dcache_signals [0][0].REQ_PKTID .write(0);
739	dcache_signals [0][0].REQ_ADDR .write(0x7000000C);
740	dcache_signals [0][0].REQ_TYPE .write(DTYPE_WRITE);
741	dcache_signals [0][0].REQ_ACCESS.write(ACCESS_32);
742	dcache_signals [0][0].REQ_WDATA .write(0x10000004);
743	TEST(bool ,dcache_signals [0][0].REQ_ACK .read(),true);
744
745	dcache_signals [0][1].REQ_VAL .write(true);
746	dcache_signals [0][1].REQ_TRDID .write(1);
747	dcache_signals [0][1].REQ_PKTID .write(0);
748	dcache_signals [0][1].REQ_ADDR .write(0x70000000);
749	dcache_signals [0][1].REQ_TYPE .write(DTYPE_WRITE);
750	dcache_signals [0][1].REQ_ACCESS.write(ACCESS_32);
751	dcache_signals [0][1].REQ_WDATA .write(SERVICE_TIME);
752
753	TEST(bool ,dcache_signals [0][1].REQ_ACK .read(),true);
754
755	dcache_signals [0][2].REQ_VAL .write(true);
756	dcache_signals [0][2].REQ_TRDID .write(1);
757	dcache_signals [0][2].REQ_PKTID .write(0);
758	dcache_signals [0][2].REQ_ADDR .write(0x70000004);
759	dcache_signals [0][2].REQ_TYPE .write(DTYPE_READ);
760	dcache_signals [0][2].REQ_ACCESS.write(ACCESS_32);
761	dcache_signals [0][2].REQ_WDATA .write(SERVICE_TIME);
762
763	TEST(bool ,dcache_signals [0][2].REQ_ACK .read(),true);
764	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),false);
765	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
766	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
767
768	CYCLE(1);
769	dcache_signals [0][0].REQ_VAL .write(false);
770	dcache_signals [0][1].REQ_VAL .write(false);
771	dcache_signals [0][2].REQ_VAL .write(false);
772	CYCLE(28);
773
774	TEST(bool ,dcache_signals [0][0].RSP_VAL .read(),true );
775	TEST(bool ,dcache_signals [0][1].RSP_VAL .read(),false);
776	TEST(bool ,dcache_signals [0][2].RSP_VAL .read(),false);
777	}
778	//cout << *memory << endl; test_ok();
779	// CYCLE(1);
780
781	cout << "Press a key to quit the test" << endl;
782	getchar();
783	delete memory;
784	test_ok ();
785
786	return 1;
787	};

Note: See TracBrowser for help on using the repository browser.

Download in other formats: