[88] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Dcache_Access_genMealy_req.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Dcache_Access/include/Dcache_Access.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace dcache_access { |
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| 15 | |
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| 16 | |
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| 17 | #undef FUNCTION |
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| 18 | #define FUNCTION "Dcache_Access::genMealy_req" |
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| 19 | void Dcache_Access::genMealy_req (void) |
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| 20 | { |
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| 21 | log_begin(Dcache_Access,FUNCTION); |
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| 22 | |
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| 23 | Tcontrol_t dcache_req_val [_param->_nb_dcache_port]; |
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| 24 | for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) |
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| 25 | { |
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| 26 | dcache_req_val [i] = 0; |
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| 27 | |
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| 28 | #ifdef STATISTICS |
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| 29 | _internal_DCACHE_REQ_NB_ACCESS [i] = 0; |
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| 30 | _internal_DCACHE_REQ_NB_ACCESS_CONFLIT [i] = 0; |
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| 31 | #endif |
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| 32 | } |
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| 33 | |
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| 34 | Tcontrol_t lsq_req_ack [_param->_nb_execute_loop][_param->_max_nb_load_store_unit][_param->_max_nb_cache_access]; |
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| 35 | for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) |
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| 36 | for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) |
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| 37 | for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) |
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| 38 | lsq_req_ack [i][j][k] = 0; |
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| 39 | |
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| 40 | std::list<generic::priority::select_t> * select = _priority ->select(); |
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| 41 | for (std::list<generic::priority::select_t>::iterator it=select ->begin(); |
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| 42 | it!=select->end(); |
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| 43 | ++it) |
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| 44 | { |
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| 45 | uint32_t num_execute_loop = it->grp; |
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| 46 | uint32_t num_load_store_unit = it->elt; |
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| 47 | |
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| 48 | for (uint32_t num_cache_access = 0; num_cache_access<_param->_nb_cache_access [num_execute_loop][num_load_store_unit]; ++num_cache_access) |
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| 49 | { |
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| 50 | if (PORT_READ(in_LSQ_REQ_VAL [num_execute_loop][num_load_store_unit][num_cache_access])) |
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| 51 | { |
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| 52 | uint32_t num_port = _param->_table_routing[num_execute_loop][num_load_store_unit][num_cache_access]; |
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| 53 | Tcontrol_t dcache_req_ack = PORT_READ(in_DCACHE_REQ_ACK [num_port]); |
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| 54 | |
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| 55 | #ifdef STATISTICS |
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| 56 | if (dcache_req_ack) |
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| 57 | { |
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| 58 | _internal_DCACHE_REQ_NB_ACCESS [num_port] ++; |
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| 59 | if (dcache_req_val [num_port]) |
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| 60 | _internal_DCACHE_REQ_NB_ACCESS_CONFLIT [num_port] ++; |
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| 61 | } |
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| 62 | #endif |
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| 63 | if (not dcache_req_val [num_port]) |
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| 64 | { |
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| 65 | dcache_req_val [num_port] = 1; |
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| 66 | lsq_req_ack [num_execute_loop][num_load_store_unit][num_cache_access] = dcache_req_ack; |
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| 67 | |
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| 68 | if (_param->_have_port_dcache_thread_id) |
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| 69 | { |
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| 70 | Tcontext_t num_context = (_param->_have_port_lsq_thread_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_THREAD_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0; |
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| 71 | PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], _param->_translate_load_store_unit_to_thread[num_execute_loop][num_load_store_unit][num_context]); |
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| 72 | } |
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| 73 | // PORT_WRITE(out_DCACHE_REQ_THREAD_ID [num_port], ((num_execute_loop << _param->_shift_num_execute_loop )+ |
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| 74 | // (num_load_store_unit << _param->_shift_num_load_store_unit)+ |
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| 75 | // (num_cache_access << _param->_shift_num_cache_access )+ |
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| 76 | // num_context)); |
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| 77 | if (_param->_have_port_dcache_packet_id) |
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| 78 | { |
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| 79 | Tpacket_t packet_id = (_param->_have_port_lsq_packet_id [num_execute_loop][num_load_store_unit])?PORT_READ(in_LSQ_REQ_PACKET_ID [num_execute_loop][num_load_store_unit][num_cache_access]):0; |
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| 80 | PORT_WRITE(out_DCACHE_REQ_PACKET_ID [num_port], ((num_cache_access << _param->_shift_num_cache_access )+ |
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| 81 | packet_id)); |
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| 82 | } |
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| 83 | PORT_WRITE(out_DCACHE_REQ_ADDRESS [num_port], PORT_READ(in_LSQ_REQ_ADDRESS [num_execute_loop][num_load_store_unit][num_cache_access])); |
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| 84 | PORT_WRITE(out_DCACHE_REQ_WDATA [num_port], PORT_READ(in_LSQ_REQ_WDATA [num_execute_loop][num_load_store_unit][num_cache_access])); |
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| 85 | PORT_WRITE(out_DCACHE_REQ_TYPE [num_port], PORT_READ(in_LSQ_REQ_TYPE [num_execute_loop][num_load_store_unit][num_cache_access])); |
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| 86 | } |
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| 87 | } |
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| 88 | } |
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| 89 | } |
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| 90 | |
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| 91 | for (uint32_t i=0; i<_param->_nb_dcache_port; ++i) |
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| 92 | PORT_WRITE(out_DCACHE_REQ_VAL [i], dcache_req_val [i]); |
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| 93 | |
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| 94 | for (uint32_t i=0; i<_param->_nb_execute_loop; ++i) |
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| 95 | for (uint32_t j=0; j<_param->_nb_load_store_unit[i]; ++j) |
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| 96 | for (uint32_t k=0; k<_param->_nb_cache_access [i][j]; ++k) |
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| 97 | PORT_WRITE(out_LSQ_REQ_ACK [i][j][k], lsq_req_ack [i][j][k]); |
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| 98 | |
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| 99 | log_end(Dcache_Access,FUNCTION); |
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| 100 | }; |
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| 101 | |
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| 102 | }; // end namespace dcache_access |
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| 103 | }; // end namespace core |
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| 104 | |
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| 105 | }; // end namespace behavioural |
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| 106 | }; // end namespace morpheo |
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| 107 | #endif |
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