[116] | 1 | ------------------------------------------------------------------------------- |
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| 2 | -- File : ./Functionnal_unit_0.vhdl |
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| 3 | -- Date : Fri Mar 13 16:20:01 2009 |
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| 4 | -- Version : 0.2.111 - Castor |
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| 5 | -- Comment : it's a autogenerated file, don't modify |
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| 6 | ------------------------------------------------------------------------------- |
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| 7 | |
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| 8 | |
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| 9 | library ieee; |
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| 10 | use ieee.numeric_bit.all; |
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| 11 | use ieee.numeric_std.all; |
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| 12 | use ieee.std_logic_1164.all; |
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| 13 | use ieee.std_logic_arith.all; |
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| 14 | use ieee.std_logic_misc.all; |
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| 15 | --use ieee.std_logic_signed.all; |
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| 16 | use ieee.std_logic_unsigned.all; |
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| 17 | --use ieee.std_logic_textio.all; |
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| 18 | |
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| 19 | |
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| 20 | library work; |
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| 21 | use work.Functionnal_unit_0_Pack.all; |
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| 22 | use work.Functionnal_unit_0_shifter_Pack.all; |
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| 23 | |
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| 24 | Library XilinxCoreLib; |
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| 25 | use XilinxCoreLib.c_compare_v9_0_comp.all; |
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| 26 | |
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| 27 | entity Functionnal_unit_0 is |
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| 28 | port ( |
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| 29 | in_CLOCK : in std_logic; |
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| 30 | in_NRESET : in std_logic; |
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| 31 | in_EXECUTE_IN_VAL : in std_logic; |
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| 32 | out_EXECUTE_IN_ACK : out std_logic; |
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| 33 | in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; |
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| 34 | in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); |
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| 35 | in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); |
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| 36 | in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); |
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| 37 | in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); |
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| 38 | in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; |
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| 39 | in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); |
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| 40 | in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); |
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| 41 | in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); |
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| 42 | in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); |
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| 43 | in_EXECUTE_IN_WRITE_RD : in std_logic; |
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| 44 | in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); |
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| 45 | in_EXECUTE_IN_WRITE_RE : in std_logic; |
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| 46 | in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); |
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| 47 | out_EXECUTE_OUT_VAL : out std_logic; |
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| 48 | in_EXECUTE_OUT_ACK : in std_logic; |
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| 49 | out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; |
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| 50 | out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); |
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| 51 | out_EXECUTE_OUT_WRITE_RD : out std_logic; |
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| 52 | out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); |
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| 53 | out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); |
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| 54 | out_EXECUTE_OUT_WRITE_RE : out std_logic; |
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| 55 | out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); |
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| 56 | out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); |
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| 57 | out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); |
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| 58 | out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; |
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| 59 | out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) |
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| 60 | ); |
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| 61 | end Functionnal_unit_0; |
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| 62 | |
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| 63 | architecture behavioural of Functionnal_unit_0 is |
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| 64 | type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); |
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| 65 | |
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| 66 | signal sig_EXECUTE_IN_ACK : std_logic; |
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| 67 | signal reg_BUSY_IN : std_logic; |
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| 68 | signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; |
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| 69 | signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); |
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| 70 | signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); |
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| 71 | signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); |
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| 72 | signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; |
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| 73 | signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); |
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| 74 | signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); |
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| 75 | signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); |
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| 76 | signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); |
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| 77 | signal reg_EXECUTE_IN_WRITE_RD : std_logic; |
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| 78 | signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 79 | signal reg_EXECUTE_IN_WRITE_RE : std_logic; |
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| 80 | signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 81 | signal sig_B_OPERAND : std_logic_vector(31 downto 0); |
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| 82 | signal sig_IS_ARITH : std_logic; |
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| 83 | signal sig_IS_LOGIC : std_logic; |
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| 84 | signal sig_CIN_ARITH : std_logic; |
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| 85 | signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); |
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| 86 | signal sig_RES_ARITH : std_logic_vector(32 downto 0); |
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| 87 | signal sig_A_AND_B : std_logic_vector(31 downto 0); |
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| 88 | signal sig_A_OR_B : std_logic_vector(31 downto 0); |
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| 89 | signal sig_A_XOR_B : std_logic_vector(31 downto 0); |
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| 90 | signal sig_RES_LOGIC : std_logic_vector(31 downto 0); |
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| 91 | signal sig_RES_ALU : std_logic_vector(31 downto 0); |
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| 92 | signal sig_OVR_ALU : std_logic; |
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| 93 | signal sig_COUT_ALU : std_logic; |
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| 94 | signal sig_RES_MOVE : std_logic_vector(31 downto 0); |
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| 95 | signal sig_CMOV : std_logic_vector(31 downto 0); |
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| 96 | signal sig_MOVHI : std_logic_vector(31 downto 0); |
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| 97 | signal sig_RES_BRANCH : std_logic_vector(31 downto 0); |
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| 98 | signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); |
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| 99 | signal sig_NOSQ_BRANCH : std_logic; |
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| 100 | signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); |
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| 101 | signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); |
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| 102 | signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); |
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| 103 | signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); |
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| 104 | signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); |
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| 105 | signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); |
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| 106 | signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); |
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| 107 | signal sig_EXT_S : std_logic_vector(31 downto 0); |
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| 108 | signal sig_EXT_Z : std_logic_vector(31 downto 0); |
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| 109 | signal sig_RES_EXTEND : std_logic_vector(31 downto 0); |
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| 110 | signal sig_FF1 : std_logic_vector(5 downto 0); |
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| 111 | signal sig_FL1 : std_logic_vector(5 downto 0); |
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| 112 | signal sig_RES_FIND : std_logic_vector(31 downto 0); |
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| 113 | signal sig_SPR_IS_HERE : std_logic; |
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| 114 | signal sig_MFSPR : std_logic_vector(31 downto 0); |
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| 115 | signal sig_MTSPR : std_logic_vector(31 downto 0); |
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| 116 | signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); |
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| 117 | signal sig_EXECUTE_OUT_VAL : std_logic; |
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| 118 | signal sig_EXECUTE_OUT_UPDATE : std_logic; |
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| 119 | signal reg_BUSY_OUT : std_logic; |
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| 120 | signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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| 121 | signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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| 122 | signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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| 123 | signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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| 124 | signal reg_EXECUTE_OUT_WRITE_RD : std_logic; |
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| 125 | signal sig_EXECUTE_OUT_WRITE_RD : std_logic; |
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| 126 | signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 127 | signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 128 | signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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| 129 | signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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| 130 | signal reg_EXECUTE_OUT_WRITE_RE : std_logic; |
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| 131 | signal sig_EXECUTE_OUT_WRITE_RE : std_logic; |
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| 132 | signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 133 | signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 134 | signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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| 135 | signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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| 136 | signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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| 137 | signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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| 138 | signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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| 139 | signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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| 140 | signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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| 141 | signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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| 142 | signal reg_MACLO : Tmac; |
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| 143 | signal reg_MACHI : Tmac; |
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| 144 | |
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| 145 | signal sig_IS_LESS : std_logic; |
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| 146 | signal sig_A_COMPARE : std_logic_vector(31 downto 0); |
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| 147 | signal sig_B_COMPARE : std_logic_vector(31 downto 0); |
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| 148 | signal sig_A_GT_B_S : std_logic; |
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| 149 | signal sig_A_GT_B_U : std_logic; |
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| 150 | signal sig_A_EQ_B : std_logic; |
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| 151 | signal sig_A_GT_B : std_logic; |
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| 152 | signal sig_A_GE_B : std_logic; |
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| 153 | signal sig_A_NE_B : std_logic; |
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| 154 | signal sig_IS_SIGNED : std_logic; |
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| 155 | signal sig_FLAG_F : std_logic; |
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| 156 | signal sig_BUSY : std_logic; |
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| 157 | |
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| 158 | type TFQUEUE is array (7 downto 0) of std_logic_vector(131 downto 0); |
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| 159 | -- OOO_ENGINE_ID(1) + PACKET_ID(8) + OPERATION(7) + TYPE(5) + |
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| 160 | -- HAS_IMMEDIAT(1) + IMMEDIAT(32) + DATA_RA(32) + DATA_RB(32) + DATA_RC(2) + |
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| 161 | -- WRITE_RD(1) + NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) |
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| 162 | -- = 132 BITS |
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| 163 | signal reg_FUNCTIONAL_QUEUE : TFQUEUE; |
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| 164 | |
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| 165 | |
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| 166 | |
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| 167 | alias reg_OOO_ENGINE_ID_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(131); |
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| 168 | alias reg_OOO_ENGINE_ID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(131); |
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| 169 | alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(131); |
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| 170 | alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(131); |
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| 171 | alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(131); |
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| 172 | alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(131); |
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| 173 | alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(131); |
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| 174 | alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(131); |
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| 175 | alias reg_PACKET_ID_7 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(7)(130 downto 123); |
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| 176 | alias reg_PACKET_ID_6 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(6)(130 downto 123); |
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| 177 | alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(130 downto 123); |
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| 178 | alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(130 downto 123); |
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| 179 | alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(130 downto 123); |
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| 180 | alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(130 downto 123); |
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| 181 | alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(130 downto 123); |
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| 182 | alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(130 downto 123); |
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| 183 | alias reg_OPERATION_7 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(7)(122 downto 116); |
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| 184 | alias reg_OPERATION_6 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(6)(122 downto 116); |
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| 185 | alias reg_OPERATION_5 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(5)(122 downto 116); |
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| 186 | alias reg_OPERATION_4 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(4)(122 downto 116); |
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| 187 | alias reg_OPERATION_3 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(3)(122 downto 116); |
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| 188 | alias reg_OPERATION_2 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(2)(122 downto 116); |
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| 189 | alias reg_OPERATION_1 : std_logic_vector(6 downto 0) is reg_FUNCTIONAL_QUEUE(1)(122 downto 116); |
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| 190 | |
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| 191 | alias reg_TYPE_7 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(7)(115 downto 111); |
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| 192 | alias reg_TYPE_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(115 downto 111); |
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| 193 | alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(115 downto 111); |
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| 194 | alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(115 downto 111); |
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| 195 | alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(115 downto 111); |
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| 196 | alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(115 downto 111); |
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| 197 | alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(115 downto 111); |
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| 198 | |
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| 199 | alias reg_HAS_IMMEDIAT_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(110); |
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| 200 | alias reg_HAS_IMMEDIAT_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(110); |
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| 201 | alias reg_HAS_IMMEDIAT_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(110); |
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| 202 | alias reg_HAS_IMMEDIAT_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(110); |
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| 203 | alias reg_HAS_IMMEDIAT_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(110); |
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| 204 | alias reg_HAS_IMMEDIAT_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(110); |
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| 205 | alias reg_HAS_IMMEDIAT_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(110); |
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| 206 | |
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| 207 | alias reg_IMMEDIAT_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(109 downto 78); |
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| 208 | alias reg_IMMEDIAT_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(109 downto 78); |
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| 209 | alias reg_IMMEDIAT_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(109 downto 78); |
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| 210 | alias reg_IMMEDIAT_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(109 downto 78); |
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| 211 | alias reg_IMMEDIAT_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(109 downto 78); |
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| 212 | alias reg_IMMEDIAT_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(109 downto 78); |
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| 213 | alias reg_IMMEDIAT_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(109 downto 78); |
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| 214 | |
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| 215 | alias reg_DATA_RA_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(77 downto 46); |
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| 216 | alias reg_DATA_RA_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(77 downto 46); |
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| 217 | alias reg_DATA_RA_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(77 downto 46); |
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| 218 | alias reg_DATA_RA_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(77 downto 46); |
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| 219 | alias reg_DATA_RA_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(77 downto 46); |
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| 220 | alias reg_DATA_RA_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(77 downto 46); |
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| 221 | alias reg_DATA_RA_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(77 downto 46); |
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| 222 | |
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| 223 | alias reg_DATA_RB_7 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(7)(45 downto 14); |
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| 224 | alias reg_DATA_RB_6 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(6)(45 downto 14); |
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| 225 | alias reg_DATA_RB_5 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(5)(45 downto 14); |
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| 226 | alias reg_DATA_RB_4 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(4)(45 downto 14); |
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| 227 | alias reg_DATA_RB_3 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(3)(45 downto 14); |
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| 228 | alias reg_DATA_RB_2 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(2)(45 downto 14); |
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| 229 | alias reg_DATA_RB_1 : std_logic_vector(31 downto 0) is reg_FUNCTIONAL_QUEUE(1)(45 downto 14); |
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| 230 | |
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| 231 | alias reg_DATA_RC_7 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(7)(13 downto 12); |
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| 232 | alias reg_DATA_RC_6 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(6)(13 downto 12); |
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| 233 | alias reg_DATA_RC_5 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(5)(13 downto 12); |
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| 234 | alias reg_DATA_RC_4 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(4)(13 downto 12); |
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| 235 | alias reg_DATA_RC_3 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(3)(13 downto 12); |
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| 236 | alias reg_DATA_RC_2 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(2)(13 downto 12); |
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| 237 | alias reg_DATA_RC_1 : std_logic_vector(1 downto 0) is reg_FUNCTIONAL_QUEUE(1)(13 downto 12); |
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| 238 | |
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| 239 | alias reg_WRITE_RD_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(11); |
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| 240 | alias reg_WRITE_RD_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(11); |
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| 241 | alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); |
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| 242 | alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); |
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| 243 | alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); |
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| 244 | alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); |
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| 245 | alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); |
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| 246 | alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); |
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| 247 | alias reg_NUM_REG_RD_7 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(7)(10 downto 6); |
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| 248 | alias reg_NUM_REG_RD_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(10 downto 6); |
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| 249 | alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); |
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| 250 | alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); |
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| 251 | alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); |
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| 252 | alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); |
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| 253 | alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); |
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| 254 | alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); |
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| 255 | alias reg_WRITE_RE_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(5); |
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| 256 | alias reg_WRITE_RE_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(5); |
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| 257 | alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); |
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| 258 | alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); |
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| 259 | alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); |
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| 260 | alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); |
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| 261 | alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); |
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| 262 | alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); |
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| 263 | alias reg_NUM_REG_RE_7 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(7)(4 downto 1); |
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| 264 | alias reg_NUM_REG_RE_6 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(6)(4 downto 1); |
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| 265 | alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); |
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| 266 | alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); |
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| 267 | alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); |
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| 268 | alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); |
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| 269 | alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); |
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| 270 | alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); |
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| 271 | alias reg_VALID_7 : std_logic is reg_FUNCTIONAL_QUEUE(7)(0); |
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| 272 | alias reg_VALID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(0); |
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| 273 | alias reg_VALID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); |
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| 274 | alias reg_VALID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); |
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| 275 | alias reg_VALID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); |
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| 276 | alias reg_VALID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); |
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| 277 | alias reg_VALID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); |
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| 278 | alias reg_VALID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); |
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| 279 | |
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| 280 | -- OOO_ENGINE_ID(1) + PACKET_ID(8) + OPERATION(7) + TYPE (5) + |
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| 281 | -- HAS_IMMEDIAT (1) + DATA_RA (32) + DATA_RB (32) + DATA_RC (2) + |
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| 282 | -- WRITE_RD(1) + NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) |
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| 283 | -- = 100 BITS |
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| 284 | |
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| 285 | begin |
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| 286 | |
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| 287 | -- |
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| 288 | -- ----------------------------------- |
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| 289 | -- -- Registers |
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| 290 | -- ----------------------------------- |
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| 291 | -- |
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| 292 | |
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| 293 | process (in_CLOCK) |
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| 294 | begin |
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| 295 | if in_CLOCK'event and in_CLOCK = '1' then |
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| 296 | if (in_NRESET = '0') then |
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| 297 | reg_BUSY_IN <= '0'; |
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| 298 | reg_BUSY_OUT <= '0'; |
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| 299 | else |
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| 300 | -- Input |
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| 301 | if (sig_EXECUTE_IN_ACK = '1') then |
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| 302 | if (in_EXECUTE_IN_OPERATION = "00100") then |
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| 303 | reg_VALID_7 <= in_EXECUTE_IN_VAL; |
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| 304 | reg_NUM_REG_RE_7 <= in_EXECUTE_IN_NUM_REG_RE; |
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| 305 | reg_WRITE_RE_7 <= in_EXECUTE_IN_WRITE_RE; |
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| 306 | reg_NUM_REG_RD_7 <= in_EXECUTE_IN_NUM_REG_RD; |
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| 307 | reg_WRITE_RD_7 <= in_EXECUTE_IN_WRITE_RD; |
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| 308 | reg_DATA_RC_7 <= in_EXECUTE_IN_DATA_RC; |
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| 309 | reg_DATA_RB_7 <= in_EXECUTE_IN_DATA_RB; |
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| 310 | reg_DATA_RA_7 <= in_EXECUTE_IN_DATA_RA; |
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| 311 | reg_IMMEDIAT_7 <= in_EXECUTE_IN_IMMEDIAT; |
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| 312 | reg_HAS_IMMEDIAT_7 <= in_EXECUTE_IN_HAS_IMMEDIAT; |
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| 313 | reg_TYPE_7 <= in_EXECUTE_IN_TYPE; |
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| 314 | reg_OPERATION_7 <= in_EXECUTE_IN_OPERATION; |
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| 315 | reg_PACKET_ID_7 <= in_EXECUTE_IN_PACKET_ID; |
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| 316 | reg_OOO_ENGINE_ID_7 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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| 317 | else |
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| 318 | reg_VALID_1 <= in_EXECUTE_IN_VAL; |
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| 319 | reg_NUM_REG_RE_1 <= in_EXECUTE_IN_NUM_REG_RE; |
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| 320 | reg_WRITE_RE_1 <= in_EXECUTE_IN_WRITE_RE; |
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| 321 | reg_NUM_REG_RD_1 <= in_EXECUTE_IN_NUM_REG_RD; |
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| 322 | reg_WRITE_RD_1 <= in_EXECUTE_IN_WRITE_RD; |
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| 323 | reg_DATA_RC_1 <= in_EXECUTE_IN_DATA_RC; |
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| 324 | reg_DATA_RB_1 <= in_EXECUTE_IN_DATA_RB; |
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| 325 | reg_DATA_RA_1 <= in_EXECUTE_IN_DATA_RA; |
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| 326 | reg_IMMEDIAT_1 <= in_EXECUTE_IN_IMMEDIAT; |
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| 327 | reg_HAS_IMMEDIAT_1 <= in_EXECUTE_IN_HAS_IMMEDIAT; |
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| 328 | reg_TYPE_1 <= in_EXECUTE_IN_TYPE; |
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| 329 | reg_OPERATION_1 <= in_EXECUTE_IN_OPERATION; |
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| 330 | reg_PACKET_ID_1 <= in_EXECUTE_IN_PACKET_ID; |
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| 331 | reg_OOO_ENGINE_ID_1 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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| 332 | |
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| 333 | end if; |
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| 334 | end if; |
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| 335 | if (sig_EXECUTE_OUT_UPDATE = '1') then |
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| 336 | reg_VALID_0 <= reg_VALID_1; |
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| 337 | reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; |
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| 338 | reg_WRITE_RE_0 <= reg_WRITE_RE_1; |
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| 339 | reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; |
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| 340 | reg_WRITE_RD_0 <= reg_WRITE_RD_1; |
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| 341 | reg_DATA_RC_0 <= reg_DATA_RC_1; |
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| 342 | reg_DATA_RB_0 <= reg_DATA_RB_1; |
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| 343 | reg_DATA_RA_0 <= reg_DATA_RA_1; |
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| 344 | reg_IMMEDIAT_0 <= reg_IMMEDIAT_1; |
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| 345 | reg_HAS_IMMEDIAT_0 <= reg_HAS_IMMEDIAT_1; |
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| 346 | reg_TYPE_0 <= reg_TYPE_1; |
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| 347 | reg_OPERATION_0 <= reg_OPERATION_1; |
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| 348 | reg_PACKET_ID_0 <= reg_PACKET_ID_1; |
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| 349 | reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; |
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| 350 | |
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| 351 | reg_VALID_1 <= reg_VALID_2; |
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| 352 | reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; |
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| 353 | reg_WRITE_RE_1 <= reg_WRITE_RE_2; |
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| 354 | reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; |
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| 355 | reg_WRITE_RD_1 <= reg_WRITE_RD_2; |
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| 356 | reg_DATA_RC_1 <= reg_DATA_RC_2; |
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| 357 | reg_DATA_RB_1 <= reg_DATA_RB_2; |
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| 358 | reg_DATA_RA_1 <= reg_DATA_RA_2; |
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| 359 | reg_IMMEDIAT_1 <= reg_IMMEDIAT_2; |
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| 360 | reg_HAS_IMMEDIAT_1 <= reg_HAS_IMMEDIAT_2; |
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| 361 | reg_TYPE_1 <= reg_TYPE_2; |
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| 362 | reg_OPERATION_1 <= reg_OPERATION_2; |
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| 363 | reg_PACKET_ID_1 <= reg_PACKET_ID_2; |
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| 364 | reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; |
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| 365 | |
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| 366 | reg_VALID_2 <= reg_VALID_3; |
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| 367 | reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; |
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| 368 | reg_WRITE_RE_2 <= reg_WRITE_RE_3; |
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| 369 | reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; |
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| 370 | reg_WRITE_RD_2 <= reg_WRITE_RD_3; |
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| 371 | reg_DATA_RC_2 <= reg_DATA_RC_3; |
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| 372 | reg_DATA_RB_2 <= reg_DATA_RB_3; |
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| 373 | reg_DATA_RA_2 <= reg_DATA_RA_3; |
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| 374 | reg_IMMEDIAT_2 <= reg_IMMEDIAT_3; |
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| 375 | reg_HAS_IMMEDIAT_2 <= reg_HAS_IMMEDIAT_3; |
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| 376 | reg_TYPE_2 <= reg_TYPE_3; |
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| 377 | reg_OPERATION_2 <= reg_OPERATION_3; |
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| 378 | reg_PACKET_ID_2 <= reg_PACKET_ID_3; |
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| 379 | reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; |
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| 380 | |
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| 381 | reg_VALID_3 <= reg_VALID_4; |
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| 382 | reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; |
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| 383 | reg_WRITE_RE_3 <= reg_WRITE_RE_4; |
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| 384 | reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; |
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| 385 | reg_WRITE_RD_3 <= reg_WRITE_RD_4; |
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| 386 | reg_DATA_RC_3 <= reg_DATA_RC_4; |
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| 387 | reg_DATA_RB_3 <= reg_DATA_RB_4; |
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| 388 | reg_DATA_RA_3 <= reg_DATA_RA_4; |
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| 389 | reg_IMMEDIAT_3 <= reg_IMMEDIAT_4; |
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| 390 | reg_HAS_IMMEDIAT_3 <= reg_HAS_IMMEDIAT_4; |
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| 391 | reg_TYPE_3 <= reg_TYPE_4; |
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| 392 | reg_OPERATION_3 <= reg_OPERATION_4; |
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| 393 | reg_PACKET_ID_3 <= reg_PACKET_ID_4; |
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| 394 | reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; |
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| 395 | |
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| 396 | reg_VALID_4 <= reg_VALID_5; |
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| 397 | reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; |
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| 398 | reg_WRITE_RE_4 <= reg_WRITE_RE_5; |
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| 399 | reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; |
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| 400 | reg_WRITE_RD_4 <= reg_WRITE_RD_5; |
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| 401 | reg_DATA_RC_4 <= reg_DATA_RC_5; |
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| 402 | reg_DATA_RB_4 <= reg_DATA_RB_5; |
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| 403 | reg_DATA_RA_4 <= reg_DATA_RA_5; |
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| 404 | reg_IMMEDIAT_4 <= reg_IMMEDIAT_5; |
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| 405 | reg_HAS_IMMEDIAT_4 <= reg_HAS_IMMEDIAT_5; |
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| 406 | reg_TYPE_4 <= reg_TYPE_5; |
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| 407 | reg_OPERATION_4 <= reg_OPERATION_5; |
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| 408 | reg_PACKET_ID_4 <= reg_PACKET_ID_5; |
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| 409 | reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; |
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| 410 | |
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| 411 | reg_VALID_5 <= reg_VALID_6; |
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| 412 | reg_NUM_REG_RE_5 <= reg_NUM_REG_RE_6; |
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| 413 | reg_WRITE_RE_5 <= reg_WRITE_RE_6; |
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| 414 | reg_NUM_REG_RD_5 <= reg_NUM_REG_RD_6; |
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| 415 | reg_WRITE_RD_5 <= reg_WRITE_RD_6; |
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| 416 | reg_DATA_RC_5 <= reg_DATA_RC_6; |
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| 417 | reg_DATA_RB_5 <= reg_DATA_RB_6; |
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| 418 | reg_DATA_RA_5 <= reg_DATA_RA_6; |
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| 419 | reg_IMMEDIAT_5 <= reg_IMMEDIAT_6; |
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| 420 | reg_HAS_IMMEDIAT_5 <= reg_HAS_IMMEDIAT_6; |
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| 421 | reg_TYPE_5 <= reg_TYPE_6; |
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| 422 | reg_OPERATION_5 <= reg_OPERATION_6; |
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| 423 | reg_PACKET_ID_5 <= reg_PACKET_ID_6; |
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| 424 | reg_OOO_ENGINE_ID_5 <= reg_OOO_ENGINE_ID_6; |
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| 425 | |
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| 426 | reg_VALID_6 <= reg_VALID_7; |
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| 427 | reg_NUM_REG_RE_6 <= reg_NUM_REG_RE_7; |
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| 428 | reg_WRITE_RE_6 <= reg_WRITE_RE_7; |
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| 429 | reg_NUM_REG_RD_6 <= reg_NUM_REG_RD_7; |
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| 430 | reg_WRITE_RD_6 <= reg_WRITE_RD_7; |
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| 431 | reg_DATA_RC_6 <= reg_DATA_RC_7; |
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| 432 | reg_DATA_RB_6 <= reg_DATA_RB_7; |
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| 433 | reg_DATA_RA_6 <= reg_DATA_RA_7; |
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| 434 | reg_IMMEDIAT_6 <= reg_IMMEDIAT_7; |
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| 435 | reg_HAS_IMMEDIAT_6 <= reg_HAS_IMMEDIAT_7; |
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| 436 | reg_TYPE_6 <= reg_TYPE_7; |
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| 437 | reg_OPERATION_6 <= reg_OPERATION_7; |
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| 438 | reg_PACKET_ID_6 <= reg_PACKET_ID_7; |
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| 439 | reg_OOO_ENGINE_ID_6 <= reg_OOO_ENGINE_ID_7; |
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| 440 | end if; |
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| 441 | end if; |
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| 442 | end if; |
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| 443 | end process; |
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| 444 | |
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| 445 | -- |
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| 446 | -- ----------------------------------- |
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| 447 | -- -- Insides |
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| 448 | -- ----------------------------------- |
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| 449 | -- |
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| 450 | |
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| 451 | sig_B_OPERAND <= reg_IMMEDIAT_1 when (reg_HAS_IMMEDIAT_1 = '1') else |
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| 452 | reg_DATA_RB_1; |
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| 453 | -- |
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| 454 | -- ALU |
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| 455 | -- |
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| 456 | sig_IS_ARITH <= reg_OPERATION_1(0) or reg_OPERATION_1(1) or reg_OPERATION_1(2); |
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| 457 | sig_IS_LOGIC <= reg_OPERATION_1(3) or reg_OPERATION_1(4) or reg_OPERATION_1(5); |
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| 458 | sig_CIN_ARITH <= reg_DATA_RC_1(1) and reg_OPERATION_1(1); |
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| 459 | sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_OPERATION_1(2) = '1') else |
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| 460 | sig_B_OPERAND; |
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| 461 | sig_RES_ARITH <= ('0' & reg_DATA_RA_1) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); |
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| 462 | |
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| 463 | sig_A_AND_B <= reg_DATA_RA_1 and sig_B_OPERAND; |
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| 464 | sig_A_OR_B <= reg_DATA_RA_1 or sig_B_OPERAND; |
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| 465 | sig_A_XOR_B <= reg_DATA_RA_1 xor sig_B_OPERAND; |
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| 466 | |
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| 467 | with reg_OPERATION_1 select |
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| 468 | sig_RES_LOGIC <= |
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| 469 | sig_A_AND_B when "0001000", |
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| 470 | sig_A_OR_B when "0010000", |
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| 471 | sig_A_XOR_B when "0100000", |
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| 472 | "00000000000000000000000000000000" when others; |
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| 473 | sig_RES_ALU <= |
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| 474 | sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else |
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| 475 | sig_RES_LOGIC when (sig_IS_LOGIC = '1') else |
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| 476 | "00000000000000000000000000000000"; |
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| 477 | |
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| 478 | -- In ISA l.sub doesn't change carry flag. |
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| 479 | sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_OPERATION_1(0) or reg_OPERATION_1(1))) or (reg_OPERATION_1(2) and reg_DATA_RC_1(1)); |
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| 480 | sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_DATA_RA_1(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_DATA_RA_1(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; |
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| 481 | |
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| 482 | -- |
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| 483 | -- MOVE |
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| 484 | -- |
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| 485 | sig_MOVHI <= reg_IMMEDIAT_1(15 downto 0) & "0000000000000000"; |
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| 486 | sig_CMOV <= |
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| 487 | reg_DATA_RA_1 when (reg_DATA_RC_1(0) = '1') else |
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| 488 | reg_DATA_RB_1; |
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| 489 | sig_RES_MOVE <= |
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| 490 | sig_MOVHI when (reg_OPERATION_1(0) = '1') else |
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| 491 | sig_CMOV when (reg_OPERATION_1(1) = '1') else |
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| 492 | "00000000000000000000000000000000"; |
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| 493 | |
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| 494 | -- |
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| 495 | -- TEST |
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| 496 | -- |
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| 497 | sig_IS_LESS <= reg_OPERATION_1(3); |
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| 498 | sig_A_COMPARE <= |
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| 499 | sig_B_OPERAND when (sig_IS_LESS = '1') else |
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| 500 | reg_DATA_RA_1; |
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| 501 | |
---|
| 502 | sig_B_COMPARE <= |
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| 503 | reg_DATA_RA_1 when (sig_IS_LESS = '1') else |
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| 504 | sig_B_OPERAND; |
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| 505 | |
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| 506 | a_gt_b_s : c_compare_v9_0 |
---|
| 507 | generic map ( |
---|
| 508 | c_width => 32, |
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| 509 | c_data_type => 0, -- 0 = signed, 1 = unsigned |
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| 510 | c_has_a_eq_b => 0, |
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| 511 | c_has_a_gt_b => 1) |
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| 512 | port map ( |
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| 513 | a => sig_A_COMPARE, |
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| 514 | b => sig_B_COMPARE, |
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| 515 | a_gt_b => sig_A_GT_B_S); |
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| 516 | |
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| 517 | a_gt_b_u : c_compare_v9_0 |
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| 518 | generic map ( |
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| 519 | c_width => 32, |
---|
| 520 | c_data_type => 1, -- 0 = signed, 1 = unsigned |
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| 521 | c_has_a_eq_b => 0, |
---|
| 522 | c_has_a_gt_b => 1) |
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| 523 | port map ( |
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| 524 | a => sig_A_COMPARE, |
---|
| 525 | b => sig_B_COMPARE, |
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| 526 | a_gt_b => sig_A_GT_B_U); |
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| 527 | |
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| 528 | a_eq_b : c_compare_v9_0 |
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| 529 | generic map ( -- sign doesn't matter for |
---|
| 530 | -- equality test |
---|
| 531 | c_width => 32, |
---|
| 532 | c_has_a_eq_b => 1, |
---|
| 533 | c_has_a_gt_b => 0) |
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| 534 | port map ( |
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| 535 | a => sig_A_COMPARE, |
---|
| 536 | b => sig_B_COMPARE, |
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| 537 | a_eq_b => sig_A_EQ_B); |
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| 538 | |
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| 539 | sig_IS_SIGNED <= reg_OPERATION_1(6); |
---|
| 540 | sig_A_GT_B <= |
---|
| 541 | sig_A_GT_B_S when (sig_IS_SIGNED = '1') else |
---|
| 542 | sig_A_GT_B_U; |
---|
| 543 | sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; |
---|
| 544 | sig_A_NE_B <= not sig_A_EQ_B; |
---|
| 545 | |
---|
| 546 | sig_FLAG_F <= |
---|
| 547 | (sig_A_EQ_B and reg_OPERATION_1(4)) or |
---|
| 548 | (sig_A_NE_B and reg_OPERATION_1(5)) or |
---|
| 549 | (sig_A_GE_B and reg_OPERATION_1(0)) or |
---|
| 550 | (sig_A_GT_B and reg_OPERATION_1(1)); |
---|
| 551 | |
---|
| 552 | |
---|
| 553 | -- |
---|
| 554 | -- BRANCH |
---|
| 555 | -- |
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| 556 | sig_NOSQ_BRANCH <= (reg_DATA_RC_1(0) and reg_OPERATION_1(2)) or (not reg_DATA_RC_1(0) and reg_OPERATION_1(1)) or reg_OPERATION_1(3); |
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| 557 | sig_RES_BRANCH <= |
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| 558 | reg_IMMEDIAT_1(29 downto 0) & "00"when (reg_OPERATION_1(3) = '1') else |
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| 559 | "00000000000000000000000000000000"; |
---|
| 560 | sig_ADDR_BRANCH <= |
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| 561 | reg_DATA_RB_1(31 downto 2) when (reg_OPERATION_1(3) = '1') else |
---|
| 562 | reg_IMMEDIAT_1(29 downto 0); |
---|
| 563 | |
---|
| 564 | -- |
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| 565 | -- SHIFTER |
---|
| 566 | -- |
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| 567 | -- Instance shifter |
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| 568 | instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter |
---|
| 569 | port map ( |
---|
| 570 | in_SHIFTER_0_DATA => reg_DATA_RA_1 |
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| 571 | , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) |
---|
| 572 | , in_SHIFTER_0_DIRECTION => reg_OPERATION_1(0) |
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| 573 | , in_SHIFTER_0_TYPE => reg_OPERATION_1(1) |
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| 574 | , in_SHIFTER_0_CARRY => reg_OPERATION_1(2) |
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| 575 | ,out_SHIFTER_0_DATA => sig_RES_SHIFTER |
---|
| 576 | ); |
---|
| 577 | |
---|
| 578 | |
---|
| 579 | -- |
---|
| 580 | -- EXTEND |
---|
| 581 | -- |
---|
| 582 | sig_EXT_BYTE_S <= |
---|
| 583 | "111111111111111111111111" & reg_DATA_RA_1 (7 downto 0) when (reg_DATA_RA_1 (7) = '1') else |
---|
| 584 | "000000000000000000000000" & reg_DATA_RA_1 (7 downto 0); |
---|
| 585 | |
---|
| 586 | sig_EXT_BYTE_Z <= |
---|
| 587 | "000000000000000000000000" & reg_DATA_RA_1 (7 downto 0); |
---|
| 588 | |
---|
| 589 | sig_EXT_HALF_WORD_S <= |
---|
| 590 | "1111111111111111" & reg_DATA_RA_1 (15 downto 0) when (reg_DATA_RA_1 (15) = '1') else |
---|
| 591 | "0000000000000000" & reg_DATA_RA_1 (15 downto 0); |
---|
| 592 | |
---|
| 593 | sig_EXT_HALF_WORD_Z <= |
---|
| 594 | "0000000000000000" & reg_DATA_RA_1 (15 downto 0); |
---|
| 595 | |
---|
| 596 | sig_EXT_WORD_S <= |
---|
| 597 | "" & reg_DATA_RA_1 (31 downto 0) when (reg_DATA_RA_1 (31) = '1') else |
---|
| 598 | "" & reg_DATA_RA_1 (31 downto 0); |
---|
| 599 | |
---|
| 600 | sig_EXT_WORD_Z <= |
---|
| 601 | "" & reg_DATA_RA_1 (31 downto 0); |
---|
| 602 | |
---|
| 603 | sig_EXT_S <= |
---|
| 604 | sig_EXT_BYTE_S when (reg_IMMEDIAT_1 = 8) else |
---|
| 605 | sig_EXT_HALF_WORD_S when (reg_IMMEDIAT_1 = 16) else |
---|
| 606 | sig_EXT_WORD_S; |
---|
| 607 | |
---|
| 608 | sig_EXT_Z <= |
---|
| 609 | sig_EXT_BYTE_Z when (reg_IMMEDIAT_1 = 8) else |
---|
| 610 | sig_EXT_HALF_WORD_Z when (reg_IMMEDIAT_1 = 16) else |
---|
| 611 | sig_EXT_WORD_Z; |
---|
| 612 | |
---|
| 613 | sig_RES_EXTEND <= |
---|
| 614 | sig_EXT_Z when (reg_OPERATION_1(0) = '1') else |
---|
| 615 | sig_EXT_S; |
---|
| 616 | |
---|
| 617 | |
---|
| 618 | -- |
---|
| 619 | -- FIND |
---|
| 620 | -- |
---|
| 621 | sig_FF1 <= |
---|
| 622 | "000001" when (reg_DATA_RA_1 (0) = '1') else |
---|
| 623 | "000010" when (reg_DATA_RA_1 (1) = '1') else |
---|
| 624 | "000011" when (reg_DATA_RA_1 (2) = '1') else |
---|
| 625 | "000100" when (reg_DATA_RA_1 (3) = '1') else |
---|
| 626 | "000101" when (reg_DATA_RA_1 (4) = '1') else |
---|
| 627 | "000110" when (reg_DATA_RA_1 (5) = '1') else |
---|
| 628 | "000111" when (reg_DATA_RA_1 (6) = '1') else |
---|
| 629 | "001000" when (reg_DATA_RA_1 (7) = '1') else |
---|
| 630 | "001001" when (reg_DATA_RA_1 (8) = '1') else |
---|
| 631 | "001010" when (reg_DATA_RA_1 (9) = '1') else |
---|
| 632 | "001011" when (reg_DATA_RA_1 (10) = '1') else |
---|
| 633 | "001100" when (reg_DATA_RA_1 (11) = '1') else |
---|
| 634 | "001101" when (reg_DATA_RA_1 (12) = '1') else |
---|
| 635 | "001110" when (reg_DATA_RA_1 (13) = '1') else |
---|
| 636 | "001111" when (reg_DATA_RA_1 (14) = '1') else |
---|
| 637 | "010000" when (reg_DATA_RA_1 (15) = '1') else |
---|
| 638 | "010001" when (reg_DATA_RA_1 (16) = '1') else |
---|
| 639 | "010010" when (reg_DATA_RA_1 (17) = '1') else |
---|
| 640 | "010011" when (reg_DATA_RA_1 (18) = '1') else |
---|
| 641 | "010100" when (reg_DATA_RA_1 (19) = '1') else |
---|
| 642 | "010101" when (reg_DATA_RA_1 (20) = '1') else |
---|
| 643 | "010110" when (reg_DATA_RA_1 (21) = '1') else |
---|
| 644 | "010111" when (reg_DATA_RA_1 (22) = '1') else |
---|
| 645 | "011000" when (reg_DATA_RA_1 (23) = '1') else |
---|
| 646 | "011001" when (reg_DATA_RA_1 (24) = '1') else |
---|
| 647 | "011010" when (reg_DATA_RA_1 (25) = '1') else |
---|
| 648 | "011011" when (reg_DATA_RA_1 (26) = '1') else |
---|
| 649 | "011100" when (reg_DATA_RA_1 (27) = '1') else |
---|
| 650 | "011101" when (reg_DATA_RA_1 (28) = '1') else |
---|
| 651 | "011110" when (reg_DATA_RA_1 (29) = '1') else |
---|
| 652 | "011111" when (reg_DATA_RA_1 (30) = '1') else |
---|
| 653 | "100000" when (reg_DATA_RA_1 (31) = '1') else |
---|
| 654 | "000000"; |
---|
| 655 | |
---|
| 656 | sig_FL1 <= |
---|
| 657 | "100000" when (reg_DATA_RA_1 (31) = '1') else |
---|
| 658 | "011111" when (reg_DATA_RA_1 (30) = '1') else |
---|
| 659 | "011110" when (reg_DATA_RA_1 (29) = '1') else |
---|
| 660 | "011101" when (reg_DATA_RA_1 (28) = '1') else |
---|
| 661 | "011100" when (reg_DATA_RA_1 (27) = '1') else |
---|
| 662 | "011011" when (reg_DATA_RA_1 (26) = '1') else |
---|
| 663 | "011010" when (reg_DATA_RA_1 (25) = '1') else |
---|
| 664 | "011001" when (reg_DATA_RA_1 (24) = '1') else |
---|
| 665 | "011000" when (reg_DATA_RA_1 (23) = '1') else |
---|
| 666 | "010111" when (reg_DATA_RA_1 (22) = '1') else |
---|
| 667 | "010110" when (reg_DATA_RA_1 (21) = '1') else |
---|
| 668 | "010101" when (reg_DATA_RA_1 (20) = '1') else |
---|
| 669 | "010100" when (reg_DATA_RA_1 (19) = '1') else |
---|
| 670 | "010011" when (reg_DATA_RA_1 (18) = '1') else |
---|
| 671 | "010010" when (reg_DATA_RA_1 (17) = '1') else |
---|
| 672 | "010001" when (reg_DATA_RA_1 (16) = '1') else |
---|
| 673 | "010000" when (reg_DATA_RA_1 (15) = '1') else |
---|
| 674 | "001111" when (reg_DATA_RA_1 (14) = '1') else |
---|
| 675 | "001110" when (reg_DATA_RA_1 (13) = '1') else |
---|
| 676 | "001101" when (reg_DATA_RA_1 (12) = '1') else |
---|
| 677 | "001100" when (reg_DATA_RA_1 (11) = '1') else |
---|
| 678 | "001011" when (reg_DATA_RA_1 (10) = '1') else |
---|
| 679 | "001010" when (reg_DATA_RA_1 (9) = '1') else |
---|
| 680 | "001001" when (reg_DATA_RA_1 (8) = '1') else |
---|
| 681 | "001000" when (reg_DATA_RA_1 (7) = '1') else |
---|
| 682 | "000111" when (reg_DATA_RA_1 (6) = '1') else |
---|
| 683 | "000110" when (reg_DATA_RA_1 (5) = '1') else |
---|
| 684 | "000101" when (reg_DATA_RA_1 (4) = '1') else |
---|
| 685 | "000100" when (reg_DATA_RA_1 (3) = '1') else |
---|
| 686 | "000011" when (reg_DATA_RA_1 (2) = '1') else |
---|
| 687 | "000010" when (reg_DATA_RA_1 (1) = '1') else |
---|
| 688 | "000001" when (reg_DATA_RA_1 (0) = '1') else |
---|
| 689 | "000000"; |
---|
| 690 | |
---|
| 691 | sig_RES_FIND <= |
---|
| 692 | "00000000000000000000000000"&sig_FF1 when (reg_OPERATION_1(0) = '1') else |
---|
| 693 | "00000000000000000000000000"&sig_FL1; |
---|
| 694 | |
---|
| 695 | |
---|
| 696 | -- |
---|
| 697 | -- SPECIAL |
---|
| 698 | -- |
---|
| 699 | sig_SPR_IS_HERE <= |
---|
| 700 | '1' when (sig_A_OR_B(15 downto 0) = "00101") else |
---|
| 701 | '0'; |
---|
| 702 | -- MFSPR |
---|
| 703 | sig_MFSPR <= |
---|
| 704 | reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else |
---|
| 705 | reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else |
---|
| 706 | "00000000000000000000000000000000"; |
---|
| 707 | |
---|
| 708 | |
---|
| 709 | -- MTSPR |
---|
| 710 | process (in_CLOCK) |
---|
| 711 | begin |
---|
| 712 | if in_CLOCK'event and in_CLOCK = '1' then |
---|
| 713 | if (sig_SPR_IS_HERE = '1') then |
---|
| 714 | if (sig_A_OR_B(10 downto 0) = "00000000001") then |
---|
| 715 | reg_MACLO(0) <= reg_DATA_RB_1; |
---|
| 716 | end if; |
---|
| 717 | if (sig_A_OR_B(10 downto 0) = "00000000010") then |
---|
| 718 | reg_MACHI(0) <= reg_DATA_RB_1; |
---|
| 719 | end if; |
---|
| 720 | end if; |
---|
| 721 | end if; |
---|
| 722 | end process; |
---|
| 723 | |
---|
| 724 | sig_RES_SPECIAL <= |
---|
| 725 | sig_MFSPR when (reg_OPERATION_1 = "0000001") else |
---|
| 726 | reg_DATA_RB_1 when (reg_OPERATION_1 = "0000010") else |
---|
| 727 | "00000000000000000000000000000000"; |
---|
| 728 | |
---|
| 729 | -- |
---|
| 730 | -- TRANSACTION |
---|
| 731 | -- |
---|
| 732 | sig_BUSY <= |
---|
| 733 | -- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else |
---|
| 734 | reg_FUNCTIONAL_QUEUE(7)(0) when in_EXECUTE_IN_OPERATION = "" else |
---|
| 735 | reg_FUNCTIONAL_QUEUE(1)(0); |
---|
| 736 | sig_EXECUTE_OUT_VAL <= reg_FUNCTIONAL_QUEUE(0)(0); |
---|
| 737 | sig_EXECUTE_OUT_UPDATE <= not reg_FUNCTIONAL_QUEUE(0)(0) or in_EXECUTE_OUT_ACK; |
---|
| 738 | sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_EXECUTE_OUT_UPDATE; |
---|
| 739 | |
---|
| 740 | -- |
---|
| 741 | -- ----------------------------------- |
---|
| 742 | -- -- |
---|
| 743 | -- ----------------------------------- |
---|
| 744 | -- |
---|
| 745 | |
---|
| 746 | sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_1; |
---|
| 747 | sig_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_IN_PACKET_ID; |
---|
| 748 | sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_1; |
---|
| 749 | sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_1; |
---|
| 750 | with reg_TYPE_1 select |
---|
| 751 | sig_EXECUTE_OUT_DATA_RD <= |
---|
| 752 | sig_RES_ALU when "00000", |
---|
| 753 | sig_RES_MOVE when "00010", |
---|
| 754 | sig_RES_BRANCH when "01010", |
---|
| 755 | sig_RES_SHIFTER when "00001", |
---|
| 756 | sig_RES_EXTEND when "00110", |
---|
| 757 | sig_RES_FIND when "00111", |
---|
| 758 | sig_RES_SPECIAL when "01000", |
---|
| 759 | "00000000000000000000000000000000" when others; |
---|
| 760 | sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_1; |
---|
| 761 | sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_1; |
---|
| 762 | with reg_TYPE_1 select |
---|
| 763 | sig_EXECUTE_OUT_DATA_RE <= |
---|
| 764 | sig_COUT_ALU & sig_OVR_ALU when "00000", |
---|
| 765 | '0' & sig_FLAG_F when "00011", |
---|
| 766 | "00" when others; |
---|
| 767 | sig_EXECUTE_OUT_EXCEPTION <= |
---|
| 768 | "01011" when (reg_TYPE_1 = "00000" and sig_OVR_ALU = '1') else |
---|
| 769 | "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else |
---|
| 770 | "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else |
---|
| 771 | "00000"; |
---|
| 772 | with reg_TYPE_1 select |
---|
| 773 | sig_EXECUTE_OUT_NO_SEQUENCE <= |
---|
| 774 | sig_NOSQ_BRANCH when "01010", |
---|
| 775 | '0'when others; |
---|
| 776 | with reg_TYPE_1 select |
---|
| 777 | sig_EXECUTE_OUT_ADDRESS <= |
---|
| 778 | sig_ADDR_BRANCH when "01010", |
---|
| 779 | sig_A_OR_B(29 downto 0) when "01000", |
---|
| 780 | "000000000000000000000000000000" when others; |
---|
| 781 | |
---|
| 782 | -- |
---|
| 783 | -- ----------------------------------- |
---|
| 784 | -- -- Outputs |
---|
| 785 | -- ----------------------------------- |
---|
| 786 | -- |
---|
| 787 | |
---|
| 788 | out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; |
---|
| 789 | out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; |
---|
| 790 | out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; |
---|
| 791 | out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; |
---|
| 792 | out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; |
---|
| 793 | out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; |
---|
| 794 | out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; |
---|
| 795 | out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; |
---|
| 796 | out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; |
---|
| 797 | out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; |
---|
| 798 | out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; |
---|
| 799 | out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; |
---|
| 800 | out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; |
---|
| 801 | |
---|
| 802 | end behavioural; |
---|
| 803 | |
---|