1 | ------------------------------------------------------------------------------- |
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2 | -- File : ./Functionnal_unit_0.vhdl |
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3 | -- Date : Fri Mar 13 16:20:01 2009 |
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4 | -- Version : 0.2.111 - Castor |
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5 | -- Comment : it's a autogenerated file, don't modify |
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6 | ------------------------------------------------------------------------------- |
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7 | |
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8 | |
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9 | library ieee; |
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10 | use ieee.numeric_bit.all; |
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11 | use ieee.numeric_std.all; |
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12 | use ieee.std_logic_1164.all; |
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13 | use ieee.std_logic_arith.all; |
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14 | use ieee.std_logic_misc.all; |
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15 | --use ieee.std_logic_signed.all; |
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16 | use ieee.std_logic_unsigned.all; |
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17 | --use ieee.std_logic_textio.all; |
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18 | |
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19 | |
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20 | library work; |
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21 | use work.Functionnal_unit_0_Pack.all; |
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22 | use work.Functionnal_unit_0_shifter_Pack.all; |
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23 | |
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24 | Library XilinxCoreLib; |
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25 | use XilinxCoreLib.c_compare_v9_0_comp.all; |
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26 | use XilinxCoreLib.mult_gen_v9_0_comp.all; |
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27 | |
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28 | entity Functionnal_unit_0 is |
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29 | port ( |
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30 | in_CLOCK : in std_logic; |
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31 | in_NRESET : in std_logic; |
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32 | in_EXECUTE_IN_VAL : in std_logic; |
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33 | out_EXECUTE_IN_ACK : out std_logic; |
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34 | in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; |
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35 | in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); |
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36 | in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); |
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37 | in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); |
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38 | in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); |
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39 | in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; |
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40 | in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); |
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41 | in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); |
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42 | in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); |
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43 | in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); |
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44 | in_EXECUTE_IN_WRITE_RD : in std_logic; |
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45 | in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); |
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46 | in_EXECUTE_IN_WRITE_RE : in std_logic; |
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47 | in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); |
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48 | out_EXECUTE_OUT_VAL : out std_logic; |
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49 | in_EXECUTE_OUT_ACK : in std_logic; |
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50 | out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; |
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51 | out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); |
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52 | out_EXECUTE_OUT_WRITE_RD : out std_logic; |
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53 | out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); |
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54 | out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); |
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55 | out_EXECUTE_OUT_WRITE_RE : out std_logic; |
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56 | out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); |
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57 | out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); |
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58 | out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); |
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59 | out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; |
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60 | out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) |
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61 | ); |
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62 | end Functionnal_unit_0; |
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63 | |
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64 | architecture behavioural of Functionnal_unit_0 is |
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65 | type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); |
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66 | |
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67 | signal sig_EXECUTE_IN_ACK : std_logic; |
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68 | signal reg_EXECUTE_IN_VAL : std_logic; |
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69 | signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; |
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70 | signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); |
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71 | signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); |
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72 | signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); |
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73 | signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; |
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74 | signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); |
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75 | signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); |
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76 | signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); |
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77 | signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); |
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78 | signal reg_EXECUTE_IN_WRITE_RD : std_logic; |
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79 | signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); |
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80 | signal reg_EXECUTE_IN_WRITE_RE : std_logic; |
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81 | signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); |
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82 | signal sig_B_OPERAND : std_logic_vector(31 downto 0); |
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83 | signal sig_IS_ARITH : std_logic; |
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84 | signal sig_IS_LOGIC : std_logic; |
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85 | signal sig_CIN_ARITH : std_logic; |
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86 | signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); |
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87 | signal sig_RES_ARITH : std_logic_vector(32 downto 0); |
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88 | signal sig_A_AND_B : std_logic_vector(31 downto 0); |
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89 | signal sig_A_OR_B : std_logic_vector(31 downto 0); |
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90 | signal sig_A_XOR_B : std_logic_vector(31 downto 0); |
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91 | signal sig_RES_LOGIC : std_logic_vector(31 downto 0); |
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92 | signal sig_RES_ALU : std_logic_vector(31 downto 0); |
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93 | signal sig_OVR_ALU : std_logic; |
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94 | signal sig_COUT_ALU : std_logic; |
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95 | signal sig_RES_MOVE : std_logic_vector(31 downto 0); |
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96 | signal sig_CMOV : std_logic_vector(31 downto 0); |
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97 | signal sig_MOVHI : std_logic_vector(31 downto 0); |
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98 | signal sig_RES_BRANCH : std_logic_vector(31 downto 0); |
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99 | signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); |
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100 | signal sig_NOSQ_BRANCH : std_logic; |
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101 | signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); |
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102 | signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); |
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103 | signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); |
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104 | signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); |
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105 | signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); |
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106 | signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); |
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107 | signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); |
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108 | signal sig_EXT_S : std_logic_vector(31 downto 0); |
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109 | signal sig_EXT_Z : std_logic_vector(31 downto 0); |
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110 | signal sig_RES_EXTEND : std_logic_vector(31 downto 0); |
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111 | signal sig_FF1 : std_logic_vector(5 downto 0); |
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112 | signal sig_FL1 : std_logic_vector(5 downto 0); |
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113 | signal sig_RES_FIND : std_logic_vector(31 downto 0); |
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114 | signal sig_SPR_IS_HERE : std_logic; |
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115 | signal sig_MFSPR : std_logic_vector(31 downto 0); |
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116 | signal sig_MTSPR : std_logic_vector(31 downto 0); |
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117 | signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); |
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118 | signal sig_EXECUTE_OUT_VAL : std_logic; |
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119 | signal sig_UPDATE : std_logic; |
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120 | signal reg_EXECUTE_OUT_VAL : std_logic; |
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121 | signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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122 | signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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123 | signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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124 | signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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125 | signal reg_EXECUTE_OUT_WRITE_RD : std_logic; |
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126 | signal sig_EXECUTE_OUT_WRITE_RD : std_logic; |
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127 | signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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128 | signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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129 | signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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130 | signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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131 | signal reg_EXECUTE_OUT_WRITE_RE : std_logic; |
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132 | signal sig_EXECUTE_OUT_WRITE_RE : std_logic; |
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133 | signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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134 | signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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135 | signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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136 | signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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137 | signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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138 | signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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139 | signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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140 | signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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141 | signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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142 | signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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143 | signal reg_MACLO : Tmac; |
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144 | signal reg_MACHI : Tmac; |
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145 | |
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146 | signal sig_VAL_5 : std_logic; |
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147 | signal sig_VAL_0 : std_logic; |
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148 | signal sig_NUM_REG_RE_0 : std_logic_vector(3 downto 0); |
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149 | signal sig_WRITE_RE_0 : std_logic; |
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150 | signal sig_NUM_REG_RD_0 : std_logic_vector(4 downto 0); |
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151 | signal sig_WRITE_RD_0 : std_logic; |
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152 | signal sig_TYPE_0 : std_logic_vector(4 downto 0); |
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153 | signal sig_PACKET_ID_0 : std_logic_vector(7 downto 0); |
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154 | signal sig_OOO_ENGINE_ID_0 : std_logic; |
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155 | |
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156 | signal sig_IS_LESS : std_logic; |
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157 | signal sig_A_COMPARE : std_logic_vector(31 downto 0); |
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158 | signal sig_B_COMPARE : std_logic_vector(31 downto 0); |
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159 | signal sig_A_GT_B_S : std_logic; |
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160 | signal sig_A_GT_B_U : std_logic; |
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161 | signal sig_A_EQ_B : std_logic; |
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162 | signal sig_A_GT_B : std_logic; |
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163 | signal sig_A_GE_B : std_logic; |
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164 | signal sig_A_NE_B : std_logic; |
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165 | signal sig_IS_SIGNED : std_logic; |
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166 | signal sig_FLAG_F : std_logic; |
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167 | signal sig_BUSY : std_logic; |
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168 | |
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169 | signal sig_FULL_RES_MUL : std_logic_vector (63 downto 0); |
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170 | signal sig_FULL_RES_MULU : std_logic_vector (63 downto 0); |
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171 | signal sig_FULL_RES_MULS : std_logic_vector (63 downto 0); |
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172 | signal sig_RES_MUL : std_logic_vector (31 downto 0); |
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173 | signal sig_COUT_MUL : std_logic; |
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174 | signal sig_OVR_MUL : std_logic; |
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175 | |
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176 | |
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177 | type TFQUEUE is array (6 downto 0) of std_logic_vector(25 downto 0); |
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178 | -- OOO_ENGINE_ID(1) + PACKET_ID(8) + TYPE(5) + WRITE_RD(1) + |
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179 | -- NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) = 26 BITS |
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180 | signal reg_FUNCTIONAL_QUEUE : TFQUEUE; |
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181 | |
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182 | |
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183 | alias reg_OOO_ENGINE_ID_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(25); |
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184 | alias reg_PACKET_ID_6 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(6)(24 downto 17); |
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185 | alias reg_TYPE_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(16 downto 12); |
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186 | alias reg_WRITE_RD_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(11); |
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187 | alias reg_NUM_REG_RD_6 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(6)(10 downto 6); |
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188 | alias reg_WRITE_RE_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(5); |
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189 | alias reg_NUM_REG_RE_6 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(6)(4 downto 1); |
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190 | alias reg_VAL_6 : std_logic is reg_FUNCTIONAL_QUEUE(6)(0); |
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191 | |
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192 | alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(25); |
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193 | alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(25); |
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194 | alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(25); |
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195 | alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(25); |
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196 | alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(25); |
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197 | alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(25); |
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198 | alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(24 downto 17); |
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199 | alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(24 downto 17); |
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200 | alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(24 downto 17); |
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201 | alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(24 downto 17); |
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202 | alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(24 downto 17); |
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203 | alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(24 downto 17); |
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204 | alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(16 downto 12); |
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205 | alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(16 downto 12); |
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206 | alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(16 downto 12); |
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207 | alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(16 downto 12); |
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208 | alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(16 downto 12); |
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209 | alias reg_TYPE_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(16 downto 12); |
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210 | alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); |
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211 | alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); |
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212 | alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); |
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213 | alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); |
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214 | alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); |
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215 | alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); |
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216 | alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); |
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217 | alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); |
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218 | alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); |
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219 | alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); |
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220 | alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); |
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221 | alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); |
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222 | alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); |
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223 | alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); |
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224 | alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); |
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225 | alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); |
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226 | alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); |
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227 | alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); |
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228 | alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); |
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229 | alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); |
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230 | alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); |
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231 | alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); |
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232 | alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); |
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233 | alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); |
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234 | alias reg_VAL_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); |
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235 | alias reg_VAL_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); |
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236 | alias reg_VAL_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); |
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237 | alias reg_VAL_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); |
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238 | alias reg_VAL_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); |
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239 | alias reg_VAL_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); |
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240 | |
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241 | begin |
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242 | |
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243 | -- |
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244 | -- ----------------------------------- |
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245 | -- -- Registers |
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246 | -- ----------------------------------- |
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247 | -- |
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248 | |
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249 | process (in_CLOCK) |
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250 | begin |
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251 | if in_CLOCK'event and in_CLOCK = '1' then |
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252 | if (in_NRESET = '0') then |
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253 | reg_EXECUTE_IN_VAL <= '0'; |
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254 | reg_EXECUTE_OUT_VAL <= '0'; |
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255 | reg_FUNCTIONAL_QUEUE(0) <= (others => '0'); |
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256 | reg_FUNCTIONAL_QUEUE(1) <= (others => '0'); |
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257 | reg_FUNCTIONAL_QUEUE(2) <= (others => '0'); |
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258 | reg_FUNCTIONAL_QUEUE(3) <= (others => '0'); |
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259 | reg_FUNCTIONAL_QUEUE(4) <= (others => '0'); |
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260 | reg_FUNCTIONAL_QUEUE(5) <= (others => '0'); |
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261 | reg_FUNCTIONAL_QUEUE(6) <= (others => '0'); |
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262 | else |
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263 | -- Input |
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264 | if (sig_EXECUTE_IN_ACK = '1') then |
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265 | reg_EXECUTE_IN_VAL <= in_EXECUTE_IN_VAL; |
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266 | reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; |
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267 | reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; |
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268 | reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; |
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269 | reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; |
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270 | reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; |
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271 | reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; |
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272 | reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; |
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273 | reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; |
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274 | reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; |
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275 | reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; |
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276 | reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; |
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277 | reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; |
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278 | reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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279 | |
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280 | reg_NUM_REG_RE_6 <= in_EXECUTE_IN_NUM_REG_RE; |
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281 | reg_WRITE_RE_6 <= in_EXECUTE_IN_WRITE_RE; |
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282 | reg_NUM_REG_RD_6 <= in_EXECUTE_IN_NUM_REG_RD; |
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283 | reg_WRITE_RD_6 <= in_EXECUTE_IN_WRITE_RD; |
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284 | reg_TYPE_6 <= in_EXECUTE_IN_TYPE; |
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285 | reg_PACKET_ID_6 <= in_EXECUTE_IN_PACKET_ID; |
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286 | reg_OOO_ENGINE_ID_6 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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287 | |
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288 | -- Pipeline |
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289 | if (in_EXECUTE_IN_TYPE = "00100") then |
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290 | reg_VAL_0 <= reg_VAL_1; |
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291 | reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; |
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292 | reg_WRITE_RE_0 <= reg_WRITE_RE_1; |
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293 | reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; |
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294 | reg_WRITE_RD_0 <= reg_WRITE_RD_1; |
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295 | reg_TYPE_0 <= reg_TYPE_1; |
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296 | reg_PACKET_ID_0 <= reg_PACKET_ID_1; |
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297 | reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; |
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298 | |
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299 | reg_VAL_6 <= in_EXECUTE_IN_VAL; |
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300 | |
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301 | else |
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302 | reg_VAL_0 <= in_EXECUTE_IN_VAL; |
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303 | reg_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE; |
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304 | reg_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE; |
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305 | reg_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD; |
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306 | reg_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD; |
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307 | reg_TYPE_0 <= in_EXECUTE_IN_TYPE; |
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308 | reg_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID; |
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309 | reg_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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310 | |
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311 | reg_VAL_6 <= '0'; |
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312 | |
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313 | end if; |
---|
314 | end if; |
---|
315 | if (sig_UPDATE = '1') then |
---|
316 | |
---|
317 | reg_VAL_1 <= reg_VAL_2; |
---|
318 | reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; |
---|
319 | reg_WRITE_RE_1 <= reg_WRITE_RE_2; |
---|
320 | reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; |
---|
321 | reg_WRITE_RD_1 <= reg_WRITE_RD_2; |
---|
322 | reg_TYPE_1 <= reg_TYPE_2; |
---|
323 | reg_PACKET_ID_1 <= reg_PACKET_ID_2; |
---|
324 | reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; |
---|
325 | |
---|
326 | reg_VAL_2 <= reg_VAL_3; |
---|
327 | reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; |
---|
328 | reg_WRITE_RE_2 <= reg_WRITE_RE_3; |
---|
329 | reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; |
---|
330 | reg_WRITE_RD_2 <= reg_WRITE_RD_3; |
---|
331 | reg_TYPE_2 <= reg_TYPE_3; |
---|
332 | reg_PACKET_ID_2 <= reg_PACKET_ID_3; |
---|
333 | reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; |
---|
334 | |
---|
335 | reg_VAL_3 <= reg_VAL_4; |
---|
336 | reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; |
---|
337 | reg_WRITE_RE_3 <= reg_WRITE_RE_4; |
---|
338 | reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; |
---|
339 | reg_WRITE_RD_3 <= reg_WRITE_RD_4; |
---|
340 | reg_TYPE_3 <= reg_TYPE_4; |
---|
341 | reg_PACKET_ID_3 <= reg_PACKET_ID_4; |
---|
342 | reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; |
---|
343 | |
---|
344 | reg_VAL_4 <= reg_VAL_5; |
---|
345 | reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; |
---|
346 | reg_WRITE_RE_4 <= reg_WRITE_RE_5; |
---|
347 | reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; |
---|
348 | reg_WRITE_RD_4 <= reg_WRITE_RD_5; |
---|
349 | reg_TYPE_4 <= reg_TYPE_5; |
---|
350 | reg_PACKET_ID_4 <= reg_PACKET_ID_5; |
---|
351 | reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; |
---|
352 | |
---|
353 | reg_VAL_5 <= reg_VAL_6; |
---|
354 | reg_NUM_REG_RE_5 <= reg_NUM_REG_RE_6; |
---|
355 | reg_WRITE_RE_5 <= reg_WRITE_RE_6; |
---|
356 | reg_NUM_REG_RD_5 <= reg_NUM_REG_RD_6; |
---|
357 | reg_WRITE_RD_5 <= reg_WRITE_RD_6; |
---|
358 | reg_TYPE_5 <= reg_TYPE_6; |
---|
359 | reg_PACKET_ID_5 <= reg_PACKET_ID_6; |
---|
360 | reg_OOO_ENGINE_ID_5 <= reg_OOO_ENGINE_ID_6; |
---|
361 | |
---|
362 | -- Output |
---|
363 | reg_EXECUTE_OUT_VAL <= reg_VAL_0; |
---|
364 | reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; |
---|
365 | reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; |
---|
366 | reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; |
---|
367 | reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; |
---|
368 | reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; |
---|
369 | reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; |
---|
370 | reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; |
---|
371 | reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; |
---|
372 | reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; |
---|
373 | reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; |
---|
374 | reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; |
---|
375 | end if; |
---|
376 | end if; |
---|
377 | end if; |
---|
378 | end process; |
---|
379 | |
---|
380 | -- |
---|
381 | -- ----------------------------------- |
---|
382 | -- -- Insides |
---|
383 | -- ----------------------------------- |
---|
384 | -- |
---|
385 | |
---|
386 | -- sig_VAL_0 <= in_EXECUTE_IN_VAL when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
387 | -- reg_VAL_1; |
---|
388 | -- sig_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
389 | -- reg_NUM_REG_RE_1; |
---|
390 | -- sig_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
391 | -- reg_WRITE_RE_1; |
---|
392 | -- sig_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
393 | -- reg_NUM_REG_RD_1; |
---|
394 | -- sig_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
395 | -- reg_WRITE_RD_1; |
---|
396 | -- sig_TYPE_0 <= in_EXECUTE_IN_TYPE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
397 | -- reg_TYPE_1; |
---|
398 | -- sig_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
399 | -- reg_PACKET_ID_1; |
---|
400 | -- sig_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
401 | -- reg_OOO_ENGINE_ID_1; |
---|
402 | |
---|
403 | -- sig_VAL_5 <= reg_EXECUTE_IN_VAL when (reg_EXECUTE_IN_TYPE = "00100") else |
---|
404 | -- '0'; |
---|
405 | |
---|
406 | sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else |
---|
407 | reg_EXECUTE_IN_DATA_RB; |
---|
408 | -- |
---|
409 | -- ALU |
---|
410 | -- |
---|
411 | sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); |
---|
412 | sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); |
---|
413 | sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); |
---|
414 | sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else |
---|
415 | sig_B_OPERAND; |
---|
416 | sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); |
---|
417 | |
---|
418 | sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; |
---|
419 | sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; |
---|
420 | sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; |
---|
421 | |
---|
422 | with reg_EXECUTE_IN_OPERATION select |
---|
423 | sig_RES_LOGIC <= |
---|
424 | sig_A_AND_B when "0001000", |
---|
425 | sig_A_OR_B when "0010000", |
---|
426 | sig_A_XOR_B when "0100000", |
---|
427 | "00000000000000000000000000000000" when others; |
---|
428 | sig_RES_ALU <= |
---|
429 | sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else |
---|
430 | sig_RES_LOGIC when (sig_IS_LOGIC = '1') else |
---|
431 | "00000000000000000000000000000000"; |
---|
432 | |
---|
433 | -- In ISA l.sub doesn't change carry flag. |
---|
434 | sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); |
---|
435 | sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; |
---|
436 | |
---|
437 | -- |
---|
438 | -- MOVE |
---|
439 | -- |
---|
440 | sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; |
---|
441 | sig_CMOV <= |
---|
442 | reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else |
---|
443 | reg_EXECUTE_IN_DATA_RB; |
---|
444 | sig_RES_MOVE <= |
---|
445 | sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
446 | sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else |
---|
447 | "00000000000000000000000000000000"; |
---|
448 | |
---|
449 | -- |
---|
450 | -- TEST |
---|
451 | -- |
---|
452 | sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); |
---|
453 | sig_A_COMPARE <= |
---|
454 | sig_B_OPERAND when (sig_IS_LESS = '1') else |
---|
455 | reg_EXECUTE_IN_DATA_RA; |
---|
456 | |
---|
457 | sig_B_COMPARE <= |
---|
458 | reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else |
---|
459 | sig_B_OPERAND; |
---|
460 | |
---|
461 | a_gt_b_s : c_compare_v9_0 |
---|
462 | generic map ( |
---|
463 | c_width => 32, |
---|
464 | c_data_type => 0, -- 0 = signed, 1 = unsigned |
---|
465 | c_has_a_eq_b => 0, |
---|
466 | c_has_a_gt_b => 1) |
---|
467 | port map ( |
---|
468 | a => sig_A_COMPARE, |
---|
469 | b => sig_B_COMPARE, |
---|
470 | a_gt_b => sig_A_GT_B_S); |
---|
471 | |
---|
472 | a_gt_b_u : c_compare_v9_0 |
---|
473 | generic map ( |
---|
474 | c_width => 32, |
---|
475 | c_data_type => 1, -- 0 = signed, 1 = unsigned |
---|
476 | c_has_a_eq_b => 0, |
---|
477 | c_has_a_gt_b => 1) |
---|
478 | port map ( |
---|
479 | a => sig_A_COMPARE, |
---|
480 | b => sig_B_COMPARE, |
---|
481 | a_gt_b => sig_A_GT_B_U); |
---|
482 | |
---|
483 | a_eq_b : c_compare_v9_0 |
---|
484 | generic map ( -- sign doesn't matter for |
---|
485 | -- equality test |
---|
486 | c_width => 32, |
---|
487 | c_has_a_eq_b => 1, |
---|
488 | c_has_a_gt_b => 0) |
---|
489 | port map ( |
---|
490 | a => sig_A_COMPARE, |
---|
491 | b => sig_B_COMPARE, |
---|
492 | a_eq_b => sig_A_EQ_B); |
---|
493 | |
---|
494 | sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); |
---|
495 | sig_A_GT_B <= |
---|
496 | sig_A_GT_B_S when (sig_IS_SIGNED = '1') else |
---|
497 | sig_A_GT_B_U; |
---|
498 | sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; |
---|
499 | sig_A_NE_B <= not sig_A_EQ_B; |
---|
500 | |
---|
501 | sig_FLAG_F <= |
---|
502 | (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or |
---|
503 | (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or |
---|
504 | (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or |
---|
505 | (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); |
---|
506 | |
---|
507 | -- |
---|
508 | -- MULT |
---|
509 | -- |
---|
510 | signed_multiplier : mult_gen_v9_0 |
---|
511 | generic map ( |
---|
512 | c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name |
---|
513 | c_a_width => 32, -- width of A port |
---|
514 | c_a_type => 0, -- datatype of A port |
---|
515 | c_b_width => 32, -- width of B port |
---|
516 | c_b_type => 0, -- datatype of B port |
---|
517 | c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) |
---|
518 | c_mult_type => 1, -- Type of multiplier to implement |
---|
519 | c_opt_goal => 1, -- Optimization of multiplier |
---|
520 | c_has_ce => 1, -- Use clock enable on all registers |
---|
521 | c_pipe_stages => 6 -- Number of register stages required |
---|
522 | ) |
---|
523 | port map ( |
---|
524 | clk => in_CLOCK, |
---|
525 | a => reg_EXECUTE_IN_DATA_RA, |
---|
526 | b => sig_B_OPERAND, |
---|
527 | ce => sig_UPDATE, |
---|
528 | p => sig_FULL_RES_MULS |
---|
529 | ); |
---|
530 | |
---|
531 | unsigned_multiplier : mult_gen_v9_0 |
---|
532 | generic map ( |
---|
533 | c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name |
---|
534 | c_a_width => 32, -- width of A port |
---|
535 | c_a_type => 1, -- datatype of A port |
---|
536 | c_b_width => 32, -- width of B port |
---|
537 | c_b_type => 1, -- datatype of B port |
---|
538 | c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) |
---|
539 | c_mult_type => 1, -- Type of multiplier to implement |
---|
540 | c_opt_goal => 1, -- Optimization of multiplier |
---|
541 | c_has_ce => 1, -- Use clock enable on all registers |
---|
542 | c_pipe_stages => 6 -- Number of register stages required |
---|
543 | ) |
---|
544 | port map ( |
---|
545 | clk => in_CLOCK, |
---|
546 | a => reg_EXECUTE_IN_DATA_RA, |
---|
547 | b => sig_B_OPERAND, |
---|
548 | ce => sig_UPDATE, |
---|
549 | p => sig_FULL_RES_MULU |
---|
550 | ); |
---|
551 | |
---|
552 | sig_FULL_RES_MUL <= |
---|
553 | sig_FULL_RES_MULS when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
554 | sig_FULL_RES_MULU; |
---|
555 | |
---|
556 | sig_RES_MUL <= sig_FULL_RES_MUL (31 downto 0); |
---|
557 | |
---|
558 | sig_COUT_MUL <= sig_FULL_RES_MUL(63) or sig_FULL_RES_MUL(62) or sig_FULL_RES_MUL(61) or sig_FULL_RES_MUL(60) or |
---|
559 | sig_FULL_RES_MUL(59) or sig_FULL_RES_MUL(58) or sig_FULL_RES_MUL(57) or sig_FULL_RES_MUL(56) or |
---|
560 | sig_FULL_RES_MUL(55) or sig_FULL_RES_MUL(54) or sig_FULL_RES_MUL(53) or sig_FULL_RES_MUL(52) or |
---|
561 | sig_FULL_RES_MUL(51) or sig_FULL_RES_MUL(50) or sig_FULL_RES_MUL(49) or sig_FULL_RES_MUL(48) or |
---|
562 | sig_FULL_RES_MUL(47) or sig_FULL_RES_MUL(46) or sig_FULL_RES_MUL(45) or sig_FULL_RES_MUL(44) or |
---|
563 | sig_FULL_RES_MUL(43) or sig_FULL_RES_MUL(42) or sig_FULL_RES_MUL(41) or sig_FULL_RES_MUL(40) or |
---|
564 | sig_FULL_RES_MUL(39) or sig_FULL_RES_MUL(38) or sig_FULL_RES_MUL(37) or sig_FULL_RES_MUL(36) or |
---|
565 | sig_FULL_RES_MUL(35) or sig_FULL_RES_MUL(34) or sig_FULL_RES_MUL(33) or sig_FULL_RES_MUL(32); |
---|
566 | |
---|
567 | sig_OVR_MUL <= sig_COUT_MUL; |
---|
568 | |
---|
569 | -- |
---|
570 | -- BRANCH |
---|
571 | -- |
---|
572 | sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); |
---|
573 | sig_RES_BRANCH <= |
---|
574 | reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else |
---|
575 | "00000000000000000000000000000000"; |
---|
576 | sig_ADDR_BRANCH <= |
---|
577 | reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else |
---|
578 | reg_EXECUTE_IN_IMMEDIAT(29 downto 0); |
---|
579 | |
---|
580 | -- |
---|
581 | -- SHIFTER |
---|
582 | -- |
---|
583 | -- Instance shifter |
---|
584 | instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter |
---|
585 | port map ( |
---|
586 | in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA |
---|
587 | , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) |
---|
588 | , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) |
---|
589 | , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) |
---|
590 | , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) |
---|
591 | ,out_SHIFTER_0_DATA => sig_RES_SHIFTER |
---|
592 | ); |
---|
593 | |
---|
594 | |
---|
595 | -- |
---|
596 | -- EXTEND |
---|
597 | -- |
---|
598 | sig_EXT_BYTE_S <= |
---|
599 | "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
600 | "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); |
---|
601 | |
---|
602 | sig_EXT_BYTE_Z <= |
---|
603 | "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); |
---|
604 | |
---|
605 | sig_EXT_HALF_WORD_S <= |
---|
606 | "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
607 | "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); |
---|
608 | |
---|
609 | sig_EXT_HALF_WORD_Z <= |
---|
610 | "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); |
---|
611 | |
---|
612 | sig_EXT_WORD_S <= |
---|
613 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
614 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); |
---|
615 | |
---|
616 | sig_EXT_WORD_Z <= |
---|
617 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); |
---|
618 | |
---|
619 | sig_EXT_S <= |
---|
620 | sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else |
---|
621 | sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else |
---|
622 | sig_EXT_WORD_S; |
---|
623 | |
---|
624 | sig_EXT_Z <= |
---|
625 | sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else |
---|
626 | sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else |
---|
627 | sig_EXT_WORD_Z; |
---|
628 | |
---|
629 | sig_RES_EXTEND <= |
---|
630 | sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
631 | sig_EXT_S; |
---|
632 | |
---|
633 | |
---|
634 | -- |
---|
635 | -- FIND |
---|
636 | -- |
---|
637 | sig_FF1 <= |
---|
638 | "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else |
---|
639 | "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else |
---|
640 | "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else |
---|
641 | "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else |
---|
642 | "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else |
---|
643 | "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else |
---|
644 | "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else |
---|
645 | "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
646 | "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else |
---|
647 | "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else |
---|
648 | "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else |
---|
649 | "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else |
---|
650 | "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else |
---|
651 | "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else |
---|
652 | "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else |
---|
653 | "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
654 | "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else |
---|
655 | "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else |
---|
656 | "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else |
---|
657 | "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else |
---|
658 | "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else |
---|
659 | "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else |
---|
660 | "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else |
---|
661 | "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else |
---|
662 | "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else |
---|
663 | "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else |
---|
664 | "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else |
---|
665 | "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else |
---|
666 | "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else |
---|
667 | "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else |
---|
668 | "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else |
---|
669 | "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
670 | "000000"; |
---|
671 | |
---|
672 | sig_FL1 <= |
---|
673 | "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
674 | "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else |
---|
675 | "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else |
---|
676 | "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else |
---|
677 | "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else |
---|
678 | "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else |
---|
679 | "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else |
---|
680 | "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else |
---|
681 | "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else |
---|
682 | "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else |
---|
683 | "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else |
---|
684 | "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else |
---|
685 | "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else |
---|
686 | "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else |
---|
687 | "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else |
---|
688 | "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else |
---|
689 | "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
690 | "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else |
---|
691 | "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else |
---|
692 | "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else |
---|
693 | "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else |
---|
694 | "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else |
---|
695 | "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else |
---|
696 | "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else |
---|
697 | "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
698 | "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else |
---|
699 | "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else |
---|
700 | "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else |
---|
701 | "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else |
---|
702 | "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else |
---|
703 | "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else |
---|
704 | "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else |
---|
705 | "000000"; |
---|
706 | |
---|
707 | sig_RES_FIND <= |
---|
708 | "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
709 | "00000000000000000000000000"&sig_FL1; |
---|
710 | |
---|
711 | |
---|
712 | -- |
---|
713 | -- SPECIAL |
---|
714 | -- |
---|
715 | sig_SPR_IS_HERE <= |
---|
716 | '1' when (sig_A_OR_B(15 downto 0) = "00101") else |
---|
717 | '0'; |
---|
718 | -- MFSPR |
---|
719 | sig_MFSPR <= |
---|
720 | reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else |
---|
721 | reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else |
---|
722 | "00000000000000000000000000000000"; |
---|
723 | |
---|
724 | |
---|
725 | -- MTSPR |
---|
726 | process (in_CLOCK) |
---|
727 | begin |
---|
728 | if in_CLOCK'event and in_CLOCK = '1' then |
---|
729 | if (sig_SPR_IS_HERE = '1') then |
---|
730 | if (sig_A_OR_B(10 downto 0) = "00000000001") then |
---|
731 | reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; |
---|
732 | end if; |
---|
733 | if (sig_A_OR_B(10 downto 0) = "00000000010") then |
---|
734 | reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; |
---|
735 | end if; |
---|
736 | end if; |
---|
737 | end if; |
---|
738 | end process; |
---|
739 | |
---|
740 | sig_RES_SPECIAL <= |
---|
741 | sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else |
---|
742 | reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else |
---|
743 | "00000000000000000000000000000000"; |
---|
744 | |
---|
745 | -- |
---|
746 | -- TRANSACTION |
---|
747 | -- |
---|
748 | sig_BUSY <= |
---|
749 | -- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else |
---|
750 | reg_VAL_6 when in_EXECUTE_IN_TYPE = "00100" else |
---|
751 | reg_VAL_0; |
---|
752 | sig_EXECUTE_OUT_VAL <= reg_EXECUTE_OUT_VAL; |
---|
753 | sig_UPDATE <= not reg_EXECUTE_OUT_VAL or in_EXECUTE_OUT_ACK; |
---|
754 | sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_UPDATE; |
---|
755 | |
---|
756 | -- |
---|
757 | -- ----------------------------------- |
---|
758 | -- -- Output Buffer Signals |
---|
759 | -- ----------------------------------- |
---|
760 | -- |
---|
761 | |
---|
762 | sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0; |
---|
763 | sig_EXECUTE_OUT_PACKET_ID <= reg_PACKET_ID_0; |
---|
764 | sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_0; |
---|
765 | sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_0; |
---|
766 | with reg_TYPE_0 select |
---|
767 | sig_EXECUTE_OUT_DATA_RD <= |
---|
768 | sig_RES_ALU when "00000", |
---|
769 | sig_RES_MOVE when "00010", |
---|
770 | sig_RES_BRANCH when "01010", |
---|
771 | sig_RES_SHIFTER when "00001", |
---|
772 | sig_RES_EXTEND when "00110", |
---|
773 | sig_RES_FIND when "00111", |
---|
774 | sig_RES_MUL when "00100", |
---|
775 | sig_RES_SPECIAL when "01000", |
---|
776 | "00000000000000000000000000000000" when others; |
---|
777 | sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_0; |
---|
778 | sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_0; |
---|
779 | with reg_TYPE_0 select |
---|
780 | sig_EXECUTE_OUT_DATA_RE <= |
---|
781 | sig_COUT_ALU & sig_OVR_ALU when "00000", |
---|
782 | sig_COUT_MUL & sig_OVR_MUL when "00100", |
---|
783 | '0' & sig_FLAG_F when "00011", |
---|
784 | "00" when others; |
---|
785 | sig_EXECUTE_OUT_EXCEPTION <= |
---|
786 | "01011" when (reg_TYPE_0 = "00000" and sig_OVR_ALU = '1') else |
---|
787 | "01011" when (reg_TYPE_0 = "00100" and sig_OVR_MUL = '1') else |
---|
788 | -- "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else |
---|
789 | -- "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else |
---|
790 | "00000"; |
---|
791 | with reg_TYPE_0 select |
---|
792 | sig_EXECUTE_OUT_NO_SEQUENCE <= |
---|
793 | sig_NOSQ_BRANCH when "01010", |
---|
794 | '0'when others; |
---|
795 | with reg_TYPE_0 select |
---|
796 | sig_EXECUTE_OUT_ADDRESS <= |
---|
797 | sig_ADDR_BRANCH when "01010", |
---|
798 | sig_A_OR_B(29 downto 0) when "01000", |
---|
799 | "000000000000000000000000000000" when others; |
---|
800 | |
---|
801 | -- |
---|
802 | -- ----------------------------------- |
---|
803 | -- -- Outputs |
---|
804 | -- ----------------------------------- |
---|
805 | -- |
---|
806 | |
---|
807 | out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; |
---|
808 | out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; |
---|
809 | out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; |
---|
810 | out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; |
---|
811 | out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; |
---|
812 | out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; |
---|
813 | out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; |
---|
814 | out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; |
---|
815 | out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; |
---|
816 | out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; |
---|
817 | out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; |
---|
818 | out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; |
---|
819 | out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; |
---|
820 | |
---|
821 | end behavioural; |
---|
822 | |
---|