[116] | 1 | ------------------------------------------------------------------------------- |
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| 2 | -- File : ./Functionnal_unit_0.vhdl |
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| 3 | -- Date : Fri Mar 13 16:20:01 2009 |
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| 4 | -- Version : 0.2.111 - Castor |
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| 5 | -- Comment : it's a autogenerated file, don't modify |
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| 6 | ------------------------------------------------------------------------------- |
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| 7 | |
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| 8 | |
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| 9 | library ieee; |
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| 10 | use ieee.numeric_bit.all; |
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| 11 | use ieee.numeric_std.all; |
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| 12 | use ieee.std_logic_1164.all; |
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| 13 | use ieee.std_logic_arith.all; |
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| 14 | use ieee.std_logic_misc.all; |
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| 15 | --use ieee.std_logic_signed.all; |
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| 16 | use ieee.std_logic_unsigned.all; |
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| 17 | --use ieee.std_logic_textio.all; |
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| 18 | |
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| 19 | |
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| 20 | library work; |
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| 21 | use work.Functionnal_unit_0_Pack.all; |
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| 22 | use work.Functionnal_unit_0_shifter_Pack.all; |
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| 23 | |
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| 24 | Library XilinxCoreLib; |
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| 25 | use XilinxCoreLib.c_compare_v9_0_comp.all; |
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| 26 | use XilinxCoreLib.mult_gen_v9_0_comp.all; |
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| 27 | |
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| 28 | entity Functionnal_unit_0 is |
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| 29 | port ( |
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| 30 | in_CLOCK : in std_logic; |
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| 31 | in_NRESET : in std_logic; |
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| 32 | in_EXECUTE_IN_VAL : in std_logic; |
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| 33 | out_EXECUTE_IN_ACK : out std_logic; |
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| 34 | in_EXECUTE_IN_OOO_ENGINE_ID : in std_logic; |
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| 35 | in_EXECUTE_IN_PACKET_ID : in std_logic_vector(7 downto 0); |
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| 36 | in_EXECUTE_IN_OPERATION : in std_logic_vector(6 downto 0); |
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| 37 | in_EXECUTE_IN_TYPE : in std_logic_vector(4 downto 0); |
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| 38 | in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE : in std_logic_vector(1 downto 0); |
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| 39 | in_EXECUTE_IN_HAS_IMMEDIAT : in std_logic; |
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| 40 | in_EXECUTE_IN_IMMEDIAT : in std_logic_vector(31 downto 0); |
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| 41 | in_EXECUTE_IN_DATA_RA : in std_logic_vector(31 downto 0); |
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| 42 | in_EXECUTE_IN_DATA_RB : in std_logic_vector(31 downto 0); |
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| 43 | in_EXECUTE_IN_DATA_RC : in std_logic_vector(1 downto 0); |
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| 44 | in_EXECUTE_IN_WRITE_RD : in std_logic; |
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| 45 | in_EXECUTE_IN_NUM_REG_RD : in std_logic_vector(4 downto 0); |
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| 46 | in_EXECUTE_IN_WRITE_RE : in std_logic; |
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| 47 | in_EXECUTE_IN_NUM_REG_RE : in std_logic_vector(3 downto 0); |
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| 48 | out_EXECUTE_OUT_VAL : out std_logic; |
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| 49 | in_EXECUTE_OUT_ACK : in std_logic; |
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| 50 | out_EXECUTE_OUT_OOO_ENGINE_ID : out std_logic; |
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| 51 | out_EXECUTE_OUT_PACKET_ID : out std_logic_vector(7 downto 0); |
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| 52 | out_EXECUTE_OUT_WRITE_RD : out std_logic; |
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| 53 | out_EXECUTE_OUT_NUM_REG_RD : out std_logic_vector(4 downto 0); |
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| 54 | out_EXECUTE_OUT_DATA_RD : out std_logic_vector(31 downto 0); |
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| 55 | out_EXECUTE_OUT_WRITE_RE : out std_logic; |
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| 56 | out_EXECUTE_OUT_NUM_REG_RE : out std_logic_vector(3 downto 0); |
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| 57 | out_EXECUTE_OUT_DATA_RE : out std_logic_vector(1 downto 0); |
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| 58 | out_EXECUTE_OUT_EXCEPTION : out std_logic_vector(4 downto 0); |
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| 59 | out_EXECUTE_OUT_NO_SEQUENCE : out std_logic; |
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| 60 | out_EXECUTE_OUT_ADDRESS : out std_logic_vector(29 downto 0) |
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| 61 | ); |
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| 62 | end Functionnal_unit_0; |
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| 63 | |
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| 64 | architecture behavioural of Functionnal_unit_0 is |
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| 65 | type Tmac is array (1 downto 0) of std_logic_vector(31 downto 0); |
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| 66 | |
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| 67 | signal sig_EXECUTE_IN_ACK : std_logic; |
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| 68 | signal reg_EXECUTE_IN_VAL : std_logic; |
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| 69 | signal reg_EXECUTE_IN_OOO_ENGINE_ID : std_logic; |
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| 70 | signal reg_EXECUTE_IN_PACKET_ID : std_logic_vector(7 downto 0); |
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| 71 | signal reg_EXECUTE_IN_OPERATION : std_logic_vector(6 downto 0); |
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| 72 | signal reg_EXECUTE_IN_TYPE : std_logic_vector(4 downto 0); |
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| 73 | signal reg_EXECUTE_IN_HAS_IMMEDIAT : std_logic; |
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| 74 | signal reg_EXECUTE_IN_IMMEDIAT : std_logic_vector(31 downto 0); |
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| 75 | signal reg_EXECUTE_IN_DATA_RA : std_logic_vector(31 downto 0); |
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| 76 | signal reg_EXECUTE_IN_DATA_RB : std_logic_vector(31 downto 0); |
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| 77 | signal reg_EXECUTE_IN_DATA_RC : std_logic_vector(1 downto 0); |
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| 78 | signal reg_EXECUTE_IN_WRITE_RD : std_logic; |
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| 79 | signal reg_EXECUTE_IN_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 80 | signal reg_EXECUTE_IN_WRITE_RE : std_logic; |
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| 81 | signal reg_EXECUTE_IN_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 82 | signal sig_B_OPERAND : std_logic_vector(31 downto 0); |
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| 83 | signal sig_IS_ARITH : std_logic; |
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| 84 | signal sig_IS_LOGIC : std_logic; |
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| 85 | signal sig_CIN_ARITH : std_logic; |
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| 86 | signal sig_ARITH_B_OPERAND : std_logic_vector(31 downto 0); |
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| 87 | signal sig_RES_ARITH : std_logic_vector(32 downto 0); |
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| 88 | signal sig_A_AND_B : std_logic_vector(31 downto 0); |
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| 89 | signal sig_A_OR_B : std_logic_vector(31 downto 0); |
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| 90 | signal sig_A_XOR_B : std_logic_vector(31 downto 0); |
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| 91 | signal sig_RES_LOGIC : std_logic_vector(31 downto 0); |
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| 92 | signal sig_RES_ALU : std_logic_vector(31 downto 0); |
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| 93 | signal sig_OVR_ALU : std_logic; |
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| 94 | signal sig_COUT_ALU : std_logic; |
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| 95 | signal sig_RES_MOVE : std_logic_vector(31 downto 0); |
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| 96 | signal sig_CMOV : std_logic_vector(31 downto 0); |
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| 97 | signal sig_MOVHI : std_logic_vector(31 downto 0); |
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| 98 | signal sig_RES_BRANCH : std_logic_vector(31 downto 0); |
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| 99 | signal sig_ADDR_BRANCH : std_logic_vector(29 downto 0); |
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| 100 | signal sig_NOSQ_BRANCH : std_logic; |
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| 101 | signal sig_RES_SHIFTER : std_logic_vector(31 downto 0); |
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| 102 | signal sig_EXT_BYTE_S : std_logic_vector(31 downto 0); |
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| 103 | signal sig_EXT_BYTE_Z : std_logic_vector(31 downto 0); |
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| 104 | signal sig_EXT_HALF_WORD_S : std_logic_vector(31 downto 0); |
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| 105 | signal sig_EXT_HALF_WORD_Z : std_logic_vector(31 downto 0); |
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| 106 | signal sig_EXT_WORD_S : std_logic_vector(31 downto 0); |
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| 107 | signal sig_EXT_WORD_Z : std_logic_vector(31 downto 0); |
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| 108 | signal sig_EXT_S : std_logic_vector(31 downto 0); |
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| 109 | signal sig_EXT_Z : std_logic_vector(31 downto 0); |
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| 110 | signal sig_RES_EXTEND : std_logic_vector(31 downto 0); |
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| 111 | signal sig_FF1 : std_logic_vector(5 downto 0); |
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| 112 | signal sig_FL1 : std_logic_vector(5 downto 0); |
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| 113 | signal sig_RES_FIND : std_logic_vector(31 downto 0); |
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| 114 | signal sig_SPR_IS_HERE : std_logic; |
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| 115 | signal sig_MFSPR : std_logic_vector(31 downto 0); |
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| 116 | signal sig_MTSPR : std_logic_vector(31 downto 0); |
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| 117 | signal sig_RES_SPECIAL : std_logic_vector(31 downto 0); |
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| 118 | signal sig_EXECUTE_OUT_VAL : std_logic; |
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| 119 | signal sig_UPDATE : std_logic; |
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| 120 | signal reg_EXECUTE_OUT_VAL : std_logic; |
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| 121 | signal reg_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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| 122 | signal sig_EXECUTE_OUT_OOO_ENGINE_ID : std_logic; |
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| 123 | signal reg_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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| 124 | signal sig_EXECUTE_OUT_PACKET_ID : std_logic_vector(7 downto 0); |
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| 125 | signal reg_EXECUTE_OUT_WRITE_RD : std_logic; |
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| 126 | signal sig_EXECUTE_OUT_WRITE_RD : std_logic; |
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| 127 | signal reg_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 128 | signal sig_EXECUTE_OUT_NUM_REG_RD : std_logic_vector(4 downto 0); |
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| 129 | signal reg_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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| 130 | signal sig_EXECUTE_OUT_DATA_RD : std_logic_vector(31 downto 0); |
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| 131 | signal reg_EXECUTE_OUT_WRITE_RE : std_logic; |
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| 132 | signal sig_EXECUTE_OUT_WRITE_RE : std_logic; |
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| 133 | signal reg_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 134 | signal sig_EXECUTE_OUT_NUM_REG_RE : std_logic_vector(3 downto 0); |
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| 135 | signal reg_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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| 136 | signal sig_EXECUTE_OUT_DATA_RE : std_logic_vector(1 downto 0); |
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| 137 | signal reg_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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| 138 | signal sig_EXECUTE_OUT_EXCEPTION : std_logic_vector(4 downto 0); |
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| 139 | signal reg_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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| 140 | signal sig_EXECUTE_OUT_NO_SEQUENCE : std_logic; |
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| 141 | signal reg_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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| 142 | signal sig_EXECUTE_OUT_ADDRESS : std_logic_vector(29 downto 0); |
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| 143 | signal reg_MACLO : Tmac; |
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| 144 | signal reg_MACHI : Tmac; |
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| 145 | |
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| 146 | signal sig_VAL_5 : std_logic; |
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| 147 | signal sig_VAL_0 : std_logic; |
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| 148 | signal sig_NUM_REG_RE_0 : std_logic_vector(3 downto 0); |
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| 149 | signal sig_WRITE_RE_0 : std_logic; |
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| 150 | signal sig_NUM_REG_RD_0 : std_logic_vector(4 downto 0); |
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| 151 | signal sig_WRITE_RD_0 : std_logic; |
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| 152 | signal sig_TYPE_0 : std_logic_vector(4 downto 0); |
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| 153 | signal sig_PACKET_ID_0 : std_logic_vector(7 downto 0); |
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| 154 | signal sig_OOO_ENGINE_ID_0 : std_logic; |
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| 155 | |
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| 156 | signal sig_IS_LESS : std_logic; |
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| 157 | signal sig_A_COMPARE : std_logic_vector(31 downto 0); |
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| 158 | signal sig_B_COMPARE : std_logic_vector(31 downto 0); |
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| 159 | signal sig_A_GT_B_S : std_logic; |
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| 160 | signal sig_A_GT_B_U : std_logic; |
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| 161 | signal sig_A_EQ_B : std_logic; |
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| 162 | signal sig_A_GT_B : std_logic; |
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| 163 | signal sig_A_GE_B : std_logic; |
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| 164 | signal sig_A_NE_B : std_logic; |
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| 165 | signal sig_IS_SIGNED : std_logic; |
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| 166 | signal sig_FLAG_F : std_logic; |
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| 167 | signal sig_BUSY : std_logic; |
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| 168 | |
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| 169 | signal sig_FULL_RES_MUL : std_logic_vector (63 downto 0); |
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| 170 | signal sig_FULL_RES_MULU : std_logic_vector (63 downto 0); |
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| 171 | signal sig_FULL_RES_MULS : std_logic_vector (63 downto 0); |
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| 172 | signal sig_RES_MUL : std_logic_vector (31 downto 0); |
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| 173 | signal sig_COUT_MUL : std_logic; |
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| 174 | signal sig_OVR_MUL : std_logic; |
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| 175 | |
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| 176 | |
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| 177 | type TFQUEUE is array (5 downto 0) of std_logic_vector(25 downto 0); |
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| 178 | -- OOO_ENGINE_ID(1) + PACKET_ID(8) + TYPE(5) + WRITE_RD(1) + |
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| 179 | -- NUM_REG_RD(5) + WRITE_RE(1) + NUM_REG_RE(4) + VALID(1) = 26 BITS |
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| 180 | signal reg_FUNCTIONAL_QUEUE : TFQUEUE; |
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| 181 | |
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| 182 | |
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| 183 | |
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| 184 | alias reg_OOO_ENGINE_ID_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(25); |
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| 185 | alias reg_OOO_ENGINE_ID_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(25); |
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| 186 | alias reg_OOO_ENGINE_ID_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(25); |
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| 187 | alias reg_OOO_ENGINE_ID_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(25); |
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| 188 | alias reg_OOO_ENGINE_ID_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(25); |
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| 189 | alias reg_OOO_ENGINE_ID_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(25); |
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| 190 | alias reg_PACKET_ID_5 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(5)(24 downto 17); |
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| 191 | alias reg_PACKET_ID_4 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(4)(24 downto 17); |
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| 192 | alias reg_PACKET_ID_3 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(3)(24 downto 17); |
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| 193 | alias reg_PACKET_ID_2 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(2)(24 downto 17); |
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| 194 | alias reg_PACKET_ID_1 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(1)(24 downto 17); |
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| 195 | alias reg_PACKET_ID_0 : std_logic_vector(7 downto 0) is reg_FUNCTIONAL_QUEUE(0)(24 downto 17); |
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| 196 | alias reg_TYPE_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(16 downto 12); |
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| 197 | alias reg_TYPE_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(16 downto 12); |
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| 198 | alias reg_TYPE_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(16 downto 12); |
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| 199 | alias reg_TYPE_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(16 downto 12); |
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| 200 | alias reg_TYPE_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(16 downto 12); |
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| 201 | alias reg_TYPE_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(16 downto 12); |
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| 202 | alias reg_WRITE_RD_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(11); |
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| 203 | alias reg_WRITE_RD_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(11); |
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| 204 | alias reg_WRITE_RD_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(11); |
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| 205 | alias reg_WRITE_RD_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(11); |
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| 206 | alias reg_WRITE_RD_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(11); |
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| 207 | alias reg_WRITE_RD_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(11); |
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| 208 | alias reg_NUM_REG_RD_5 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(5)(10 downto 6); |
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| 209 | alias reg_NUM_REG_RD_4 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(4)(10 downto 6); |
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| 210 | alias reg_NUM_REG_RD_3 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(3)(10 downto 6); |
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| 211 | alias reg_NUM_REG_RD_2 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(2)(10 downto 6); |
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| 212 | alias reg_NUM_REG_RD_1 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(1)(10 downto 6); |
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| 213 | alias reg_NUM_REG_RD_0 : std_logic_vector(4 downto 0) is reg_FUNCTIONAL_QUEUE(0)(10 downto 6); |
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| 214 | alias reg_WRITE_RE_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(5); |
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| 215 | alias reg_WRITE_RE_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(5); |
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| 216 | alias reg_WRITE_RE_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(5); |
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| 217 | alias reg_WRITE_RE_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(5); |
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| 218 | alias reg_WRITE_RE_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(5); |
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| 219 | alias reg_WRITE_RE_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(5); |
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| 220 | alias reg_NUM_REG_RE_5 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(5)(4 downto 1); |
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| 221 | alias reg_NUM_REG_RE_4 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(4)(4 downto 1); |
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| 222 | alias reg_NUM_REG_RE_3 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(3)(4 downto 1); |
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| 223 | alias reg_NUM_REG_RE_2 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(2)(4 downto 1); |
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| 224 | alias reg_NUM_REG_RE_1 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(1)(4 downto 1); |
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| 225 | alias reg_NUM_REG_RE_0 : std_logic_vector(3 downto 0) is reg_FUNCTIONAL_QUEUE(0)(4 downto 1); |
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| 226 | alias reg_VAL_5 : std_logic is reg_FUNCTIONAL_QUEUE(5)(0); |
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| 227 | alias reg_VAL_4 : std_logic is reg_FUNCTIONAL_QUEUE(4)(0); |
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| 228 | alias reg_VAL_3 : std_logic is reg_FUNCTIONAL_QUEUE(3)(0); |
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| 229 | alias reg_VAL_2 : std_logic is reg_FUNCTIONAL_QUEUE(2)(0); |
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| 230 | alias reg_VAL_1 : std_logic is reg_FUNCTIONAL_QUEUE(1)(0); |
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| 231 | alias reg_VAL_0 : std_logic is reg_FUNCTIONAL_QUEUE(0)(0); |
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| 232 | |
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| 233 | begin |
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| 234 | |
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| 235 | -- |
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| 236 | -- ----------------------------------- |
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| 237 | -- -- Registers |
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| 238 | -- ----------------------------------- |
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| 239 | -- |
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| 240 | |
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| 241 | process (in_CLOCK) |
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| 242 | begin |
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| 243 | if in_CLOCK'event and in_CLOCK = '1' then |
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| 244 | if (in_NRESET = '0') then |
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| 245 | reg_EXECUTE_IN_VAL <= '0'; |
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| 246 | reg_EXECUTE_OUT_VAL <= '0'; |
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| 247 | reg_FUNCTIONAL_QUEUE(0) <= (others => '0'); |
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| 248 | reg_FUNCTIONAL_QUEUE(1) <= (others => '0'); |
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| 249 | reg_FUNCTIONAL_QUEUE(2) <= (others => '0'); |
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| 250 | reg_FUNCTIONAL_QUEUE(3) <= (others => '0'); |
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| 251 | reg_FUNCTIONAL_QUEUE(4) <= (others => '0'); |
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| 252 | reg_FUNCTIONAL_QUEUE(5) <= (others => '0'); |
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| 253 | else |
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| 254 | -- Input |
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| 255 | if (sig_EXECUTE_IN_ACK = '1') then |
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| 256 | reg_EXECUTE_IN_VAL <= in_EXECUTE_IN_VAL; |
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| 257 | reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE; |
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| 258 | reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE; |
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| 259 | reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD; |
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| 260 | reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD; |
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| 261 | reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC; |
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| 262 | reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB; |
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| 263 | reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA; |
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| 264 | reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT; |
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| 265 | reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT; |
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| 266 | reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE; |
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| 267 | reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION; |
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| 268 | reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID; |
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| 269 | reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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| 270 | |
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| 271 | -- Pipeline |
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| 272 | if (in_EXECUTE_IN_TYPE = "00100") then |
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| 273 | reg_VAL_5 <= in_EXECUTE_IN_VAL; |
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| 274 | reg_NUM_REG_RE_5 <= in_EXECUTE_IN_NUM_REG_RE; |
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| 275 | reg_WRITE_RE_5 <= in_EXECUTE_IN_WRITE_RE; |
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| 276 | reg_NUM_REG_RD_5 <= in_EXECUTE_IN_NUM_REG_RD; |
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| 277 | reg_WRITE_RD_5 <= in_EXECUTE_IN_WRITE_RD; |
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| 278 | reg_TYPE_5 <= in_EXECUTE_IN_TYPE; |
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| 279 | reg_PACKET_ID_5 <= in_EXECUTE_IN_PACKET_ID; |
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| 280 | reg_OOO_ENGINE_ID_5 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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| 281 | |
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| 282 | reg_VAL_0 <= reg_VAL_1; |
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| 283 | reg_NUM_REG_RE_0 <= reg_NUM_REG_RE_1; |
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| 284 | reg_WRITE_RE_0 <= reg_WRITE_RE_1; |
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| 285 | reg_NUM_REG_RD_0 <= reg_NUM_REG_RD_1; |
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| 286 | reg_WRITE_RD_0 <= reg_WRITE_RD_1; |
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| 287 | reg_TYPE_0 <= reg_TYPE_1; |
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| 288 | reg_PACKET_ID_0 <= reg_PACKET_ID_1; |
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| 289 | reg_OOO_ENGINE_ID_0 <= reg_OOO_ENGINE_ID_1; |
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| 290 | |
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| 291 | else |
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| 292 | reg_VAL_0 <= in_EXECUTE_IN_VAL; |
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| 293 | reg_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE; |
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| 294 | reg_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE; |
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| 295 | reg_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD; |
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| 296 | reg_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD; |
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| 297 | reg_TYPE_0 <= in_EXECUTE_IN_TYPE; |
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| 298 | reg_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID; |
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| 299 | reg_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID; |
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| 300 | end if; |
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| 301 | end if; |
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| 302 | if (sig_UPDATE = '1') then |
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| 303 | |
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| 304 | reg_VAL_1 <= reg_VAL_2; |
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| 305 | reg_NUM_REG_RE_1 <= reg_NUM_REG_RE_2; |
---|
| 306 | reg_WRITE_RE_1 <= reg_WRITE_RE_2; |
---|
| 307 | reg_NUM_REG_RD_1 <= reg_NUM_REG_RD_2; |
---|
| 308 | reg_WRITE_RD_1 <= reg_WRITE_RD_2; |
---|
| 309 | reg_TYPE_1 <= reg_TYPE_2; |
---|
| 310 | reg_PACKET_ID_1 <= reg_PACKET_ID_2; |
---|
| 311 | reg_OOO_ENGINE_ID_1 <= reg_OOO_ENGINE_ID_2; |
---|
| 312 | |
---|
| 313 | reg_VAL_2 <= reg_VAL_3; |
---|
| 314 | reg_NUM_REG_RE_2 <= reg_NUM_REG_RE_3; |
---|
| 315 | reg_WRITE_RE_2 <= reg_WRITE_RE_3; |
---|
| 316 | reg_NUM_REG_RD_2 <= reg_NUM_REG_RD_3; |
---|
| 317 | reg_WRITE_RD_2 <= reg_WRITE_RD_3; |
---|
| 318 | reg_TYPE_2 <= reg_TYPE_3; |
---|
| 319 | reg_PACKET_ID_2 <= reg_PACKET_ID_3; |
---|
| 320 | reg_OOO_ENGINE_ID_2 <= reg_OOO_ENGINE_ID_3; |
---|
| 321 | |
---|
| 322 | reg_VAL_3 <= reg_VAL_4; |
---|
| 323 | reg_NUM_REG_RE_3 <= reg_NUM_REG_RE_4; |
---|
| 324 | reg_WRITE_RE_3 <= reg_WRITE_RE_4; |
---|
| 325 | reg_NUM_REG_RD_3 <= reg_NUM_REG_RD_4; |
---|
| 326 | reg_WRITE_RD_3 <= reg_WRITE_RD_4; |
---|
| 327 | reg_TYPE_3 <= reg_TYPE_4; |
---|
| 328 | reg_PACKET_ID_3 <= reg_PACKET_ID_4; |
---|
| 329 | reg_OOO_ENGINE_ID_3 <= reg_OOO_ENGINE_ID_4; |
---|
| 330 | |
---|
| 331 | reg_VAL_4 <= reg_VAL_5; |
---|
| 332 | reg_NUM_REG_RE_4 <= reg_NUM_REG_RE_5; |
---|
| 333 | reg_WRITE_RE_4 <= reg_WRITE_RE_5; |
---|
| 334 | reg_NUM_REG_RD_4 <= reg_NUM_REG_RD_5; |
---|
| 335 | reg_WRITE_RD_4 <= reg_WRITE_RD_5; |
---|
| 336 | reg_TYPE_4 <= reg_TYPE_5; |
---|
| 337 | reg_PACKET_ID_4 <= reg_PACKET_ID_5; |
---|
| 338 | reg_OOO_ENGINE_ID_4 <= reg_OOO_ENGINE_ID_5; |
---|
| 339 | |
---|
| 340 | -- Output |
---|
| 341 | reg_EXECUTE_OUT_VAL <= reg_VAL_0; |
---|
| 342 | reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID; |
---|
| 343 | reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID; |
---|
| 344 | reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD; |
---|
| 345 | reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD; |
---|
| 346 | reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD; |
---|
| 347 | reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE; |
---|
| 348 | reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE; |
---|
| 349 | reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE; |
---|
| 350 | reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION; |
---|
| 351 | reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE; |
---|
| 352 | reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS; |
---|
| 353 | end if; |
---|
| 354 | end if; |
---|
| 355 | end if; |
---|
| 356 | end process; |
---|
| 357 | |
---|
| 358 | -- |
---|
| 359 | -- ----------------------------------- |
---|
| 360 | -- -- Insides |
---|
| 361 | -- ----------------------------------- |
---|
| 362 | -- |
---|
| 363 | |
---|
| 364 | -- sig_VAL_0 <= in_EXECUTE_IN_VAL when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 365 | -- reg_VAL_1; |
---|
| 366 | -- sig_NUM_REG_RE_0 <= in_EXECUTE_IN_NUM_REG_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 367 | -- reg_NUM_REG_RE_1; |
---|
| 368 | -- sig_WRITE_RE_0 <= in_EXECUTE_IN_WRITE_RE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 369 | -- reg_WRITE_RE_1; |
---|
| 370 | -- sig_NUM_REG_RD_0 <= in_EXECUTE_IN_NUM_REG_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 371 | -- reg_NUM_REG_RD_1; |
---|
| 372 | -- sig_WRITE_RD_0 <= in_EXECUTE_IN_WRITE_RD when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 373 | -- reg_WRITE_RD_1; |
---|
| 374 | -- sig_TYPE_0 <= in_EXECUTE_IN_TYPE when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 375 | -- reg_TYPE_1; |
---|
| 376 | -- sig_PACKET_ID_0 <= in_EXECUTE_IN_PACKET_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 377 | -- reg_PACKET_ID_1; |
---|
| 378 | -- sig_OOO_ENGINE_ID_0 <= in_EXECUTE_IN_OOO_ENGINE_ID when (sig_EXECUTE_IN_ACK = '1' and in_EXECUTE_IN_TYPE /= "00100") else |
---|
| 379 | -- reg_OOO_ENGINE_ID_1; |
---|
| 380 | |
---|
| 381 | -- sig_VAL_5 <= reg_EXECUTE_IN_VAL when (reg_EXECUTE_IN_TYPE = "00100") else |
---|
| 382 | -- '0'; |
---|
| 383 | |
---|
| 384 | sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else |
---|
| 385 | reg_EXECUTE_IN_DATA_RB; |
---|
| 386 | -- |
---|
| 387 | -- ALU |
---|
| 388 | -- |
---|
| 389 | sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1) or reg_EXECUTE_IN_OPERATION(2); |
---|
| 390 | sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION(3) or reg_EXECUTE_IN_OPERATION(4) or reg_EXECUTE_IN_OPERATION(5); |
---|
| 391 | sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC(1) and reg_EXECUTE_IN_OPERATION(1); |
---|
| 392 | sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION(2) = '1') else |
---|
| 393 | sig_B_OPERAND; |
---|
| 394 | sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("000000000000000000000000000000" & sig_CIN_ARITH); |
---|
| 395 | |
---|
| 396 | sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND; |
---|
| 397 | sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND; |
---|
| 398 | sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND; |
---|
| 399 | |
---|
| 400 | with reg_EXECUTE_IN_OPERATION select |
---|
| 401 | sig_RES_LOGIC <= |
---|
| 402 | sig_A_AND_B when "0001000", |
---|
| 403 | sig_A_OR_B when "0010000", |
---|
| 404 | sig_A_XOR_B when "0100000", |
---|
| 405 | "00000000000000000000000000000000" when others; |
---|
| 406 | sig_RES_ALU <= |
---|
| 407 | sig_RES_ARITH (31 downto 0) when (sig_IS_ARITH = '1') else |
---|
| 408 | sig_RES_LOGIC when (sig_IS_LOGIC = '1') else |
---|
| 409 | "00000000000000000000000000000000"; |
---|
| 410 | |
---|
| 411 | -- In ISA l.sub doesn't change carry flag. |
---|
| 412 | sig_COUT_ALU <= (sig_RES_ARITH(32) and (reg_EXECUTE_IN_OPERATION(0) or reg_EXECUTE_IN_OPERATION(1))) or (reg_EXECUTE_IN_OPERATION(2) and reg_EXECUTE_IN_DATA_RC(1)); |
---|
| 413 | sig_OVR_ALU <= ((sig_ARITH_B_OPERAND(31) and reg_EXECUTE_IN_DATA_RA(31) and not sig_RES_ARITH(31)) or (not sig_ARITH_B_OPERAND(31) and not reg_EXECUTE_IN_DATA_RA(31) and sig_RES_ARITH(31))) and sig_IS_ARITH; |
---|
| 414 | |
---|
| 415 | -- |
---|
| 416 | -- MOVE |
---|
| 417 | -- |
---|
| 418 | sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT(15 downto 0) & "0000000000000000"; |
---|
| 419 | sig_CMOV <= |
---|
| 420 | reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC(0) = '1') else |
---|
| 421 | reg_EXECUTE_IN_DATA_RB; |
---|
| 422 | sig_RES_MOVE <= |
---|
| 423 | sig_MOVHI when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
| 424 | sig_CMOV when (reg_EXECUTE_IN_OPERATION(1) = '1') else |
---|
| 425 | "00000000000000000000000000000000"; |
---|
| 426 | |
---|
| 427 | -- |
---|
| 428 | -- TEST |
---|
| 429 | -- |
---|
| 430 | sig_IS_LESS <= reg_EXECUTE_IN_OPERATION(3); |
---|
| 431 | sig_A_COMPARE <= |
---|
| 432 | sig_B_OPERAND when (sig_IS_LESS = '1') else |
---|
| 433 | reg_EXECUTE_IN_DATA_RA; |
---|
| 434 | |
---|
| 435 | sig_B_COMPARE <= |
---|
| 436 | reg_EXECUTE_IN_DATA_RA when (sig_IS_LESS = '1') else |
---|
| 437 | sig_B_OPERAND; |
---|
| 438 | |
---|
| 439 | a_gt_b_s : c_compare_v9_0 |
---|
| 440 | generic map ( |
---|
| 441 | c_width => 32, |
---|
| 442 | c_data_type => 0, -- 0 = signed, 1 = unsigned |
---|
| 443 | c_has_a_eq_b => 0, |
---|
| 444 | c_has_a_gt_b => 1) |
---|
| 445 | port map ( |
---|
| 446 | a => sig_A_COMPARE, |
---|
| 447 | b => sig_B_COMPARE, |
---|
| 448 | a_gt_b => sig_A_GT_B_S); |
---|
| 449 | |
---|
| 450 | a_gt_b_u : c_compare_v9_0 |
---|
| 451 | generic map ( |
---|
| 452 | c_width => 32, |
---|
| 453 | c_data_type => 1, -- 0 = signed, 1 = unsigned |
---|
| 454 | c_has_a_eq_b => 0, |
---|
| 455 | c_has_a_gt_b => 1) |
---|
| 456 | port map ( |
---|
| 457 | a => sig_A_COMPARE, |
---|
| 458 | b => sig_B_COMPARE, |
---|
| 459 | a_gt_b => sig_A_GT_B_U); |
---|
| 460 | |
---|
| 461 | a_eq_b : c_compare_v9_0 |
---|
| 462 | generic map ( -- sign doesn't matter for |
---|
| 463 | -- equality test |
---|
| 464 | c_width => 32, |
---|
| 465 | c_has_a_eq_b => 1, |
---|
| 466 | c_has_a_gt_b => 0) |
---|
| 467 | port map ( |
---|
| 468 | a => sig_A_COMPARE, |
---|
| 469 | b => sig_B_COMPARE, |
---|
| 470 | a_eq_b => sig_A_EQ_B); |
---|
| 471 | |
---|
| 472 | sig_IS_SIGNED <= reg_EXECUTE_IN_OPERATION(6); |
---|
| 473 | sig_A_GT_B <= |
---|
| 474 | sig_A_GT_B_S when (sig_IS_SIGNED = '1') else |
---|
| 475 | sig_A_GT_B_U; |
---|
| 476 | sig_A_GE_B <= sig_A_GT_B or sig_A_EQ_B; |
---|
| 477 | sig_A_NE_B <= not sig_A_EQ_B; |
---|
| 478 | |
---|
| 479 | sig_FLAG_F <= |
---|
| 480 | (sig_A_EQ_B and reg_EXECUTE_IN_OPERATION(4)) or |
---|
| 481 | (sig_A_NE_B and reg_EXECUTE_IN_OPERATION(5)) or |
---|
| 482 | (sig_A_GE_B and reg_EXECUTE_IN_OPERATION(0)) or |
---|
| 483 | (sig_A_GT_B and reg_EXECUTE_IN_OPERATION(1)); |
---|
| 484 | |
---|
| 485 | -- |
---|
| 486 | -- MULT |
---|
| 487 | -- |
---|
| 488 | signed_multiplier : mult_gen_v9_0 |
---|
| 489 | generic map ( |
---|
| 490 | c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name |
---|
| 491 | c_a_width => 32, -- width of A port |
---|
| 492 | c_a_type => 0, -- datatype of A port |
---|
| 493 | c_b_width => 32, -- width of B port |
---|
| 494 | c_b_type => 0, -- datatype of B port |
---|
| 495 | c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) |
---|
| 496 | c_mult_type => 1, -- Type of multiplier to implement |
---|
| 497 | c_opt_goal => 1, -- Optimization of multiplier |
---|
| 498 | c_has_ce => 1, -- Use clock enable on all registers |
---|
| 499 | c_pipe_stages => 6 -- Number of register stages required |
---|
| 500 | ) |
---|
| 501 | port map ( |
---|
| 502 | clk => in_CLOCK, |
---|
| 503 | a => reg_EXECUTE_IN_DATA_RA, |
---|
| 504 | b => sig_B_OPERAND, |
---|
| 505 | ce => sig_UPDATE, |
---|
| 506 | p => sig_FULL_RES_MULS |
---|
| 507 | ); |
---|
| 508 | |
---|
| 509 | unsigned_multiplier : mult_gen_v9_0 |
---|
| 510 | generic map ( |
---|
| 511 | c_xdevicefamily => "virtex4", -- specifies target Xilinx FPGA name |
---|
| 512 | c_a_width => 32, -- width of A port |
---|
| 513 | c_a_type => 1, -- datatype of A port |
---|
| 514 | c_b_width => 32, -- width of B port |
---|
| 515 | c_b_type => 1, -- datatype of B port |
---|
| 516 | c_out_high => 63, -- MSB of P output port (N-1 downto 0 convention) |
---|
| 517 | c_mult_type => 1, -- Type of multiplier to implement |
---|
| 518 | c_opt_goal => 1, -- Optimization of multiplier |
---|
| 519 | c_has_ce => 1, -- Use clock enable on all registers |
---|
| 520 | c_pipe_stages => 6 -- Number of register stages required |
---|
| 521 | ) |
---|
| 522 | port map ( |
---|
| 523 | clk => in_CLOCK, |
---|
| 524 | a => reg_EXECUTE_IN_DATA_RA, |
---|
| 525 | b => sig_B_OPERAND, |
---|
| 526 | ce => sig_UPDATE, |
---|
| 527 | p => sig_FULL_RES_MULU |
---|
| 528 | ); |
---|
| 529 | |
---|
| 530 | sig_FULL_RES_MUL <= |
---|
| 531 | sig_FULL_RES_MULS when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
| 532 | sig_FULL_RES_MULU; |
---|
| 533 | |
---|
| 534 | sig_RES_MUL <= sig_FULL_RES_MUL (31 downto 0); |
---|
| 535 | |
---|
| 536 | sig_COUT_MUL <= sig_FULL_RES_MUL(63) or sig_FULL_RES_MUL(62) or sig_FULL_RES_MUL(61) or sig_FULL_RES_MUL(60) or |
---|
| 537 | sig_FULL_RES_MUL(59) or sig_FULL_RES_MUL(58) or sig_FULL_RES_MUL(57) or sig_FULL_RES_MUL(56) or |
---|
| 538 | sig_FULL_RES_MUL(55) or sig_FULL_RES_MUL(54) or sig_FULL_RES_MUL(53) or sig_FULL_RES_MUL(52) or |
---|
| 539 | sig_FULL_RES_MUL(51) or sig_FULL_RES_MUL(50) or sig_FULL_RES_MUL(49) or sig_FULL_RES_MUL(48) or |
---|
| 540 | sig_FULL_RES_MUL(47) or sig_FULL_RES_MUL(46) or sig_FULL_RES_MUL(45) or sig_FULL_RES_MUL(44) or |
---|
| 541 | sig_FULL_RES_MUL(43) or sig_FULL_RES_MUL(42) or sig_FULL_RES_MUL(41) or sig_FULL_RES_MUL(40) or |
---|
| 542 | sig_FULL_RES_MUL(39) or sig_FULL_RES_MUL(38) or sig_FULL_RES_MUL(37) or sig_FULL_RES_MUL(36) or |
---|
| 543 | sig_FULL_RES_MUL(35) or sig_FULL_RES_MUL(34) or sig_FULL_RES_MUL(33) or sig_FULL_RES_MUL(32); |
---|
| 544 | |
---|
| 545 | sig_OVR_MUL <= sig_COUT_MUL; |
---|
| 546 | |
---|
| 547 | -- |
---|
| 548 | -- BRANCH |
---|
| 549 | -- |
---|
| 550 | sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(2)) or (not reg_EXECUTE_IN_DATA_RC(0) and reg_EXECUTE_IN_OPERATION(1)) or reg_EXECUTE_IN_OPERATION(3); |
---|
| 551 | sig_RES_BRANCH <= |
---|
| 552 | reg_EXECUTE_IN_IMMEDIAT(29 downto 0) & "00"when (reg_EXECUTE_IN_OPERATION(3) = '1') else |
---|
| 553 | "00000000000000000000000000000000"; |
---|
| 554 | sig_ADDR_BRANCH <= |
---|
| 555 | reg_EXECUTE_IN_DATA_RB(31 downto 2) when (reg_EXECUTE_IN_OPERATION(3) = '1') else |
---|
| 556 | reg_EXECUTE_IN_IMMEDIAT(29 downto 0); |
---|
| 557 | |
---|
| 558 | -- |
---|
| 559 | -- SHIFTER |
---|
| 560 | -- |
---|
| 561 | -- Instance shifter |
---|
| 562 | instance_Functionnal_unit_0_shifter : Functionnal_unit_0_shifter |
---|
| 563 | port map ( |
---|
| 564 | in_SHIFTER_0_DATA => reg_EXECUTE_IN_DATA_RA |
---|
| 565 | , in_SHIFTER_0_SHIFT => sig_B_OPERAND(4 downto 0) |
---|
| 566 | , in_SHIFTER_0_DIRECTION => reg_EXECUTE_IN_OPERATION(0) |
---|
| 567 | , in_SHIFTER_0_TYPE => reg_EXECUTE_IN_OPERATION(1) |
---|
| 568 | , in_SHIFTER_0_CARRY => reg_EXECUTE_IN_OPERATION(2) |
---|
| 569 | ,out_SHIFTER_0_DATA => sig_RES_SHIFTER |
---|
| 570 | ); |
---|
| 571 | |
---|
| 572 | |
---|
| 573 | -- |
---|
| 574 | -- EXTEND |
---|
| 575 | -- |
---|
| 576 | sig_EXT_BYTE_S <= |
---|
| 577 | "111111111111111111111111" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
| 578 | "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); |
---|
| 579 | |
---|
| 580 | sig_EXT_BYTE_Z <= |
---|
| 581 | "000000000000000000000000" & reg_EXECUTE_IN_DATA_RA (7 downto 0); |
---|
| 582 | |
---|
| 583 | sig_EXT_HALF_WORD_S <= |
---|
| 584 | "1111111111111111" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
| 585 | "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); |
---|
| 586 | |
---|
| 587 | sig_EXT_HALF_WORD_Z <= |
---|
| 588 | "0000000000000000" & reg_EXECUTE_IN_DATA_RA (15 downto 0); |
---|
| 589 | |
---|
| 590 | sig_EXT_WORD_S <= |
---|
| 591 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
| 592 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); |
---|
| 593 | |
---|
| 594 | sig_EXT_WORD_Z <= |
---|
| 595 | "" & reg_EXECUTE_IN_DATA_RA (31 downto 0); |
---|
| 596 | |
---|
| 597 | sig_EXT_S <= |
---|
| 598 | sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else |
---|
| 599 | sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else |
---|
| 600 | sig_EXT_WORD_S; |
---|
| 601 | |
---|
| 602 | sig_EXT_Z <= |
---|
| 603 | sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else |
---|
| 604 | sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else |
---|
| 605 | sig_EXT_WORD_Z; |
---|
| 606 | |
---|
| 607 | sig_RES_EXTEND <= |
---|
| 608 | sig_EXT_Z when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
| 609 | sig_EXT_S; |
---|
| 610 | |
---|
| 611 | |
---|
| 612 | -- |
---|
| 613 | -- FIND |
---|
| 614 | -- |
---|
| 615 | sig_FF1 <= |
---|
| 616 | "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else |
---|
| 617 | "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else |
---|
| 618 | "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else |
---|
| 619 | "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else |
---|
| 620 | "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else |
---|
| 621 | "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else |
---|
| 622 | "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else |
---|
| 623 | "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
| 624 | "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else |
---|
| 625 | "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else |
---|
| 626 | "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else |
---|
| 627 | "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else |
---|
| 628 | "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else |
---|
| 629 | "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else |
---|
| 630 | "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else |
---|
| 631 | "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
| 632 | "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else |
---|
| 633 | "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else |
---|
| 634 | "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else |
---|
| 635 | "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else |
---|
| 636 | "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else |
---|
| 637 | "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else |
---|
| 638 | "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else |
---|
| 639 | "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else |
---|
| 640 | "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else |
---|
| 641 | "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else |
---|
| 642 | "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else |
---|
| 643 | "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else |
---|
| 644 | "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else |
---|
| 645 | "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else |
---|
| 646 | "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else |
---|
| 647 | "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
| 648 | "000000"; |
---|
| 649 | |
---|
| 650 | sig_FL1 <= |
---|
| 651 | "100000" when (reg_EXECUTE_IN_DATA_RA (31) = '1') else |
---|
| 652 | "011111" when (reg_EXECUTE_IN_DATA_RA (30) = '1') else |
---|
| 653 | "011110" when (reg_EXECUTE_IN_DATA_RA (29) = '1') else |
---|
| 654 | "011101" when (reg_EXECUTE_IN_DATA_RA (28) = '1') else |
---|
| 655 | "011100" when (reg_EXECUTE_IN_DATA_RA (27) = '1') else |
---|
| 656 | "011011" when (reg_EXECUTE_IN_DATA_RA (26) = '1') else |
---|
| 657 | "011010" when (reg_EXECUTE_IN_DATA_RA (25) = '1') else |
---|
| 658 | "011001" when (reg_EXECUTE_IN_DATA_RA (24) = '1') else |
---|
| 659 | "011000" when (reg_EXECUTE_IN_DATA_RA (23) = '1') else |
---|
| 660 | "010111" when (reg_EXECUTE_IN_DATA_RA (22) = '1') else |
---|
| 661 | "010110" when (reg_EXECUTE_IN_DATA_RA (21) = '1') else |
---|
| 662 | "010101" when (reg_EXECUTE_IN_DATA_RA (20) = '1') else |
---|
| 663 | "010100" when (reg_EXECUTE_IN_DATA_RA (19) = '1') else |
---|
| 664 | "010011" when (reg_EXECUTE_IN_DATA_RA (18) = '1') else |
---|
| 665 | "010010" when (reg_EXECUTE_IN_DATA_RA (17) = '1') else |
---|
| 666 | "010001" when (reg_EXECUTE_IN_DATA_RA (16) = '1') else |
---|
| 667 | "010000" when (reg_EXECUTE_IN_DATA_RA (15) = '1') else |
---|
| 668 | "001111" when (reg_EXECUTE_IN_DATA_RA (14) = '1') else |
---|
| 669 | "001110" when (reg_EXECUTE_IN_DATA_RA (13) = '1') else |
---|
| 670 | "001101" when (reg_EXECUTE_IN_DATA_RA (12) = '1') else |
---|
| 671 | "001100" when (reg_EXECUTE_IN_DATA_RA (11) = '1') else |
---|
| 672 | "001011" when (reg_EXECUTE_IN_DATA_RA (10) = '1') else |
---|
| 673 | "001010" when (reg_EXECUTE_IN_DATA_RA (9) = '1') else |
---|
| 674 | "001001" when (reg_EXECUTE_IN_DATA_RA (8) = '1') else |
---|
| 675 | "001000" when (reg_EXECUTE_IN_DATA_RA (7) = '1') else |
---|
| 676 | "000111" when (reg_EXECUTE_IN_DATA_RA (6) = '1') else |
---|
| 677 | "000110" when (reg_EXECUTE_IN_DATA_RA (5) = '1') else |
---|
| 678 | "000101" when (reg_EXECUTE_IN_DATA_RA (4) = '1') else |
---|
| 679 | "000100" when (reg_EXECUTE_IN_DATA_RA (3) = '1') else |
---|
| 680 | "000011" when (reg_EXECUTE_IN_DATA_RA (2) = '1') else |
---|
| 681 | "000010" when (reg_EXECUTE_IN_DATA_RA (1) = '1') else |
---|
| 682 | "000001" when (reg_EXECUTE_IN_DATA_RA (0) = '1') else |
---|
| 683 | "000000"; |
---|
| 684 | |
---|
| 685 | sig_RES_FIND <= |
---|
| 686 | "00000000000000000000000000"&sig_FF1 when (reg_EXECUTE_IN_OPERATION(0) = '1') else |
---|
| 687 | "00000000000000000000000000"&sig_FL1; |
---|
| 688 | |
---|
| 689 | |
---|
| 690 | -- |
---|
| 691 | -- SPECIAL |
---|
| 692 | -- |
---|
| 693 | sig_SPR_IS_HERE <= |
---|
| 694 | '1' when (sig_A_OR_B(15 downto 0) = "00101") else |
---|
| 695 | '0'; |
---|
| 696 | -- MFSPR |
---|
| 697 | sig_MFSPR <= |
---|
| 698 | reg_MACLO(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000001") else |
---|
| 699 | reg_MACHI(0) when (sig_SPR_IS_HERE = '1' and sig_A_OR_B(10 downto 0) = "00000000010") else |
---|
| 700 | "00000000000000000000000000000000"; |
---|
| 701 | |
---|
| 702 | |
---|
| 703 | -- MTSPR |
---|
| 704 | process (in_CLOCK) |
---|
| 705 | begin |
---|
| 706 | if in_CLOCK'event and in_CLOCK = '1' then |
---|
| 707 | if (sig_SPR_IS_HERE = '1') then |
---|
| 708 | if (sig_A_OR_B(10 downto 0) = "00000000001") then |
---|
| 709 | reg_MACLO(0) <= reg_EXECUTE_IN_DATA_RB; |
---|
| 710 | end if; |
---|
| 711 | if (sig_A_OR_B(10 downto 0) = "00000000010") then |
---|
| 712 | reg_MACHI(0) <= reg_EXECUTE_IN_DATA_RB; |
---|
| 713 | end if; |
---|
| 714 | end if; |
---|
| 715 | end if; |
---|
| 716 | end process; |
---|
| 717 | |
---|
| 718 | sig_RES_SPECIAL <= |
---|
| 719 | sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "0000001") else |
---|
| 720 | reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "0000010") else |
---|
| 721 | "00000000000000000000000000000000"; |
---|
| 722 | |
---|
| 723 | -- |
---|
| 724 | -- TRANSACTION |
---|
| 725 | -- |
---|
| 726 | sig_BUSY <= |
---|
| 727 | -- reg_FUNCTIONAL_QUEUE(34)(0) when in_EXECUTE_IN_OPERATION = "" else |
---|
| 728 | reg_VAL_5 when in_EXECUTE_IN_TYPE = "00100" else |
---|
| 729 | reg_VAL_0; |
---|
| 730 | sig_EXECUTE_OUT_VAL <= reg_EXECUTE_OUT_VAL; |
---|
| 731 | sig_UPDATE <= not reg_EXECUTE_OUT_VAL or in_EXECUTE_OUT_ACK; |
---|
| 732 | sig_EXECUTE_IN_ACK <= not sig_BUSY or sig_UPDATE; |
---|
| 733 | |
---|
| 734 | -- |
---|
| 735 | -- ----------------------------------- |
---|
| 736 | -- -- Output Buffer Signals |
---|
| 737 | -- ----------------------------------- |
---|
| 738 | -- |
---|
| 739 | |
---|
| 740 | sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_OOO_ENGINE_ID_0; |
---|
| 741 | sig_EXECUTE_OUT_PACKET_ID <= reg_PACKET_ID_0; |
---|
| 742 | sig_EXECUTE_OUT_WRITE_RD <= reg_WRITE_RD_0; |
---|
| 743 | sig_EXECUTE_OUT_NUM_REG_RD <= reg_NUM_REG_RD_0; |
---|
| 744 | with reg_TYPE_0 select |
---|
| 745 | sig_EXECUTE_OUT_DATA_RD <= |
---|
| 746 | sig_RES_ALU when "00000", |
---|
| 747 | sig_RES_MOVE when "00010", |
---|
| 748 | sig_RES_BRANCH when "01010", |
---|
| 749 | sig_RES_SHIFTER when "00001", |
---|
| 750 | sig_RES_EXTEND when "00110", |
---|
| 751 | sig_RES_FIND when "00111", |
---|
| 752 | sig_RES_MUL when "00100", |
---|
| 753 | sig_RES_SPECIAL when "01000", |
---|
| 754 | "00000000000000000000000000000000" when others; |
---|
| 755 | sig_EXECUTE_OUT_WRITE_RE <= reg_WRITE_RE_0; |
---|
| 756 | sig_EXECUTE_OUT_NUM_REG_RE <= reg_NUM_REG_RE_0; |
---|
| 757 | with reg_TYPE_0 select |
---|
| 758 | sig_EXECUTE_OUT_DATA_RE <= |
---|
| 759 | sig_COUT_ALU & sig_OVR_ALU when "00000", |
---|
| 760 | sig_COUT_MUL & sig_OVR_MUL when "00100", |
---|
| 761 | '0' & sig_FLAG_F when "00011", |
---|
| 762 | "00" when others; |
---|
| 763 | sig_EXECUTE_OUT_EXCEPTION <= |
---|
| 764 | "01011" when (reg_TYPE_0 = "00000" and sig_OVR_ALU = '1') else |
---|
| 765 | "01011" when (reg_TYPE_0 = "00100" and sig_OVR_MUL = '1') else |
---|
| 766 | -- "10011" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000001" and sig_SPR_IS_HERE = '0') else |
---|
| 767 | -- "10100" when (reg_TYPE_1 = "01000" and reg_OPERATION_1 = "0000010" and sig_SPR_IS_HERE = '0') else |
---|
| 768 | "00000"; |
---|
| 769 | with reg_TYPE_0 select |
---|
| 770 | sig_EXECUTE_OUT_NO_SEQUENCE <= |
---|
| 771 | sig_NOSQ_BRANCH when "01010", |
---|
| 772 | '0'when others; |
---|
| 773 | with reg_TYPE_0 select |
---|
| 774 | sig_EXECUTE_OUT_ADDRESS <= |
---|
| 775 | sig_ADDR_BRANCH when "01010", |
---|
| 776 | sig_A_OR_B(29 downto 0) when "01000", |
---|
| 777 | "000000000000000000000000000000" when others; |
---|
| 778 | |
---|
| 779 | -- |
---|
| 780 | -- ----------------------------------- |
---|
| 781 | -- -- Outputs |
---|
| 782 | -- ----------------------------------- |
---|
| 783 | -- |
---|
| 784 | |
---|
| 785 | out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID; |
---|
| 786 | out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID; |
---|
| 787 | out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD; |
---|
| 788 | out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD; |
---|
| 789 | out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD; |
---|
| 790 | out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE; |
---|
| 791 | out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE; |
---|
| 792 | out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE; |
---|
| 793 | out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION; |
---|
| 794 | out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE; |
---|
| 795 | out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS; |
---|
| 796 | out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL; |
---|
| 797 | out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK; |
---|
| 798 | |
---|
| 799 | end behavioural; |
---|
| 800 | |
---|