[72] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Functionnal_unit_vhdl_body.cpp 116 2009-04-30 13:51:41Z moulu $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Functionnal_unit/include/Functionnal_unit.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_execute_unit { |
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| 17 | namespace execute_unit { |
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| 18 | namespace functionnal_unit { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Functionnal_unit::vhdl_body" |
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| 23 | void Functionnal_unit::vhdl_body (Vhdl * & vhdl) |
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| 24 | { |
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| 25 | log_printf(FUNC,Functionnal_unit,FUNCTION,"Begin"); |
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| 26 | vhdl->set_body (""); |
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[116] | 27 | vhdl->set_comment(0,""); |
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| 28 | vhdl->set_comment(0,"-----------------------------------"); |
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| 29 | vhdl->set_comment(0,"-- Registers "); |
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| 30 | vhdl->set_comment(0,"-----------------------------------"); |
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| 31 | vhdl->set_comment(0,""); |
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| 32 | vhdl->set_body (""); |
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| 33 | vhdl->set_body (0,"process (in_CLOCK)"); |
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| 34 | vhdl->set_body (0,"begin"); |
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| 35 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 36 | |
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| 37 | vhdl->set_body (2,"if (in_NRESET = '0') then"); |
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| 38 | vhdl->set_body (3,"reg_BUSY_IN <= '0';"); |
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| 39 | vhdl->set_body (3,"reg_BUSY_OUT <= '0';"); |
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| 40 | vhdl->set_body (2,"else"); |
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| 41 | |
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| 42 | vhdl->set_comment (3,"Input Buffer"); |
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| 43 | vhdl->set_body (3,"if (sig_EXECUTE_IN_ACK = '1') then"); |
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| 44 | vhdl->set_body (4,"reg_BUSY_IN <= in_EXECUTE_IN_VAL;"); |
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| 45 | if(_param->_have_port_context_id) |
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| 46 | vhdl->set_body (4,"reg_EXECUTE_IN_CONTEXT_ID <= in_EXECUTE_IN_CONTEXT_ID;"); |
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| 47 | if(_param->_have_port_front_end_id) |
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| 48 | vhdl->set_body (4,"reg_EXECUTE_IN_FRONT_END_ID <= in_EXECUTE_IN_FRONT_END_ID;"); |
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| 49 | if(_param->_have_port_ooo_engine_id) |
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| 50 | vhdl->set_body (4,"reg_EXECUTE_IN_OOO_ENGINE_ID <= in_EXECUTE_IN_OOO_ENGINE_ID;"); |
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| 51 | if(_param->_have_port_rob_ptr) |
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| 52 | vhdl->set_body (4,"reg_EXECUTE_IN_PACKET_ID <= in_EXECUTE_IN_PACKET_ID;"); |
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| 53 | vhdl->set_body (4,"reg_EXECUTE_IN_OPERATION <= in_EXECUTE_IN_OPERATION;"); |
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| 54 | vhdl->set_body (4,"reg_EXECUTE_IN_TYPE <= in_EXECUTE_IN_TYPE;"); |
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| 55 | vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RA <= in_EXECUTE_IN_DATA_RA;"); |
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| 56 | vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RB <= in_EXECUTE_IN_DATA_RB;"); |
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| 57 | vhdl->set_body (4,"reg_EXECUTE_IN_DATA_RC <= in_EXECUTE_IN_DATA_RC;"); |
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| 58 | vhdl->set_body (4,"reg_EXECUTE_IN_HAS_IMMEDIAT <= in_EXECUTE_IN_HAS_IMMEDIAT;"); |
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| 59 | vhdl->set_body (4,"reg_EXECUTE_IN_IMMEDIAT <= in_EXECUTE_IN_IMMEDIAT;"); |
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| 60 | vhdl->set_body (4,"reg_EXECUTE_IN_WRITE_RD <= in_EXECUTE_IN_WRITE_RD;"); |
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| 61 | vhdl->set_body (4,"reg_EXECUTE_IN_NUM_REG_RD <= in_EXECUTE_IN_NUM_REG_RD;"); |
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| 62 | vhdl->set_body (4,"reg_EXECUTE_IN_WRITE_RE <= in_EXECUTE_IN_WRITE_RE;"); |
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| 63 | vhdl->set_body (4,"reg_EXECUTE_IN_NUM_REG_RE <= in_EXECUTE_IN_NUM_REG_RE;"); |
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| 64 | vhdl->set_body (3,"end if;"); |
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| 65 | |
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| 66 | vhdl->set_comment (3,"Output Buffer"); |
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| 67 | vhdl->set_body (3,"if (sig_EXECUTE_OUT_UPDATE = '1') then"); |
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| 68 | vhdl->set_body (4,"reg_BUSY_OUT <= reg_BUSY_IN;"); |
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| 69 | if(_param->_have_port_context_id) |
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| 70 | vhdl->set_body (4,"reg_EXECUTE_OUT_CONTEXT_ID <= sig_EXECUTE_OUT_CONTEXT_ID;"); |
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| 71 | if(_param->_have_port_front_end_id) |
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| 72 | vhdl->set_body (4,"reg_EXECUTE_OUT_FRONT_END_ID <= sig_EXECUTE_OUT_FRONT_END_ID;"); |
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| 73 | if(_param->_have_port_ooo_engine_id) |
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| 74 | vhdl->set_body (4,"reg_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID;"); |
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| 75 | if(_param->_have_port_rob_ptr) |
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| 76 | vhdl->set_body (4,"reg_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID;"); |
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| 77 | vhdl->set_body (4,"reg_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD;"); |
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| 78 | vhdl->set_body (4,"reg_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD;"); |
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| 79 | vhdl->set_body (4,"reg_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD;"); |
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| 80 | vhdl->set_body (4,"reg_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE;"); |
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| 81 | vhdl->set_body (4,"reg_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE;"); |
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| 82 | vhdl->set_body (4,"reg_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE;"); |
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| 83 | vhdl->set_body (4,"reg_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION;"); |
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| 84 | vhdl->set_body (4,"reg_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE;"); |
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| 85 | vhdl->set_body (4,"reg_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS;"); |
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| 86 | vhdl->set_body (3,"end if;"); |
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| 87 | vhdl->set_body (2,"end if;"); |
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| 88 | vhdl->set_body (1,"end if;"); |
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| 89 | vhdl->set_body (0,"end process;"); |
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| 90 | |
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| 91 | vhdl->set_body (""); |
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| 92 | vhdl->set_comment(0,""); |
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| 93 | vhdl->set_comment(0,"-----------------------------------"); |
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| 94 | vhdl->set_comment(0,"-- Insides "); |
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| 95 | vhdl->set_comment(0,"-----------------------------------"); |
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| 96 | vhdl->set_comment(0,""); |
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| 97 | |
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| 98 | vhdl->set_body (0,""); |
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| 99 | vhdl->set_body (0,"sig_B_OPERAND <= reg_EXECUTE_IN_IMMEDIAT when (reg_EXECUTE_IN_HAS_IMMEDIAT = '1') else"); |
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| 100 | vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB;"); |
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| 101 | |
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| 102 | vhdl->set_comment(0,""); |
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| 103 | vhdl->set_comment(0,"ALU"); |
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| 104 | vhdl->set_comment(0,""); |
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| 105 | |
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| 106 | vhdl->set_body (0,"sig_IS_ARITH <= reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADD))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+");"); |
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| 107 | |
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| 108 | vhdl->set_body (0,"sig_IS_LOGIC <= reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_AND))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_OR))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_XOR))+");"); |
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| 109 | |
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| 110 | vhdl->set_body (0,"sig_CIN_ARITH <= reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+");"); |
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| 111 | // vhdl->set_body (0,"sig_CIN_ARITH <= (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+")) or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+");"); |
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| 112 | |
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| 113 | // vhdl->set_body (0,"sig_ARITH_B_OPERAND <= not (sig_B_OPERAND) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") = '1') else"); |
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| 114 | vhdl->set_body (0,"sig_ARITH_B_OPERAND <= ((not sig_B_OPERAND) + 1) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") = '1') else"); |
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| 115 | vhdl->set_body (1,"sig_B_OPERAND;"); |
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| 116 | |
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| 117 | vhdl->set_body (0,"sig_RES_ARITH <= ('0' & reg_EXECUTE_IN_DATA_RA) + ('0' & sig_ARITH_B_OPERAND) + ("+std_logic_cst(_param->_size_general_data-2,0)+" & sig_CIN_ARITH);"); |
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| 118 | |
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| 119 | vhdl->set_body (0,""); |
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| 120 | vhdl->set_body (0,"sig_A_AND_B <= reg_EXECUTE_IN_DATA_RA and sig_B_OPERAND;"); |
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| 121 | vhdl->set_body (0,"sig_A_OR_B <= reg_EXECUTE_IN_DATA_RA or sig_B_OPERAND;"); |
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| 122 | vhdl->set_body (0,"sig_A_XOR_B <= reg_EXECUTE_IN_DATA_RA xor sig_B_OPERAND;"); |
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| 123 | |
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| 124 | vhdl->set_body (0,""); |
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| 125 | vhdl->set_body (0,"with reg_EXECUTE_IN_OPERATION select"); |
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| 126 | vhdl->set_body (0,"sig_RES_LOGIC <="); |
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| 127 | vhdl->set_body (1,"sig_A_AND_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_AND)+","); |
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| 128 | vhdl->set_body (1,"sig_A_OR_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_OR)+","); |
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| 129 | vhdl->set_body (1,"sig_A_XOR_B when "+std_logic_cst(_param->_size_operation,OPERATION_ALU_L_XOR)+","); |
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| 130 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+" when others;"); |
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| 131 | |
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| 132 | vhdl->set_body (0,"sig_RES_ALU <="); |
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| 133 | vhdl->set_body (1,"sig_RES_ARITH ("+toString(_param->_size_general_data-1)+" downto 0) when (sig_IS_ARITH = '1') else"); |
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| 134 | vhdl->set_body (1,"sig_RES_LOGIC when (sig_IS_LOGIC = '1') else"); |
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| 135 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); |
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| 136 | |
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| 137 | vhdl->set_body (0,""); |
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| 138 | vhdl->set_comment(0,"In ISA l.sub doesn't change carry flag."); |
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| 139 | vhdl->set_body (0,"sig_COUT_ALU <= (sig_RES_ARITH("+toString(_param->_size_general_data)+") and (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADD))+") or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_ADDC))+"))) or (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_ALU_L_SUB))+") and reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_CY)+"));"); |
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| 140 | vhdl->set_body (0,"sig_OVR_ALU <= ((sig_ARITH_B_OPERAND("+toString(_param->_size_general_data-1)+") and reg_EXECUTE_IN_DATA_RA("+toString(_param->_size_general_data-1)+") and not sig_RES_ARITH("+toString(_param->_size_general_data-1)+")) or (not sig_ARITH_B_OPERAND("+toString(_param->_size_general_data-1)+") and not reg_EXECUTE_IN_DATA_RA("+toString(_param->_size_general_data-1)+") and sig_RES_ARITH("+toString(_param->_size_general_data-1)+"))) and sig_IS_ARITH;"); |
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| 141 | |
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| 142 | vhdl->set_body (0,""); |
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| 143 | vhdl->set_comment(0,""); |
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| 144 | vhdl->set_comment(0,"MOVE"); |
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| 145 | vhdl->set_comment(0,""); |
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| 146 | vhdl->set_body (0,"sig_MOVHI <= reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-17)+" downto 0) & "+std_logic_cst(16,0)+";"); |
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| 147 | |
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| 148 | vhdl->set_body (0,"sig_CMOV <="); |
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| 149 | vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RA when (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") = '1') else"); |
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| 150 | vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB;"); |
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| 151 | |
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| 152 | vhdl->set_body (0,"sig_RES_MOVE <="); |
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| 153 | vhdl->set_body (1,"sig_MOVHI when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_MOVE_L_MOVHI))+") = '1') else"); |
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| 154 | vhdl->set_body (1,"sig_CMOV when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_MOVE_L_CMOV))+") = '1') else"); |
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| 155 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); |
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| 156 | |
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| 157 | vhdl->set_body (0,""); |
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| 158 | vhdl->set_comment(0,""); |
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| 159 | vhdl->set_comment(0,"BRANCH"); |
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| 160 | vhdl->set_comment(0,""); |
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| 161 | vhdl->set_body (0,"sig_NOSQ_BRANCH <= (reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_TEST_F))+")) or (not reg_EXECUTE_IN_DATA_RC("+toString(FLAG_POSITION_F)+") and reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_TEST_NF))+")) or reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+");"); |
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| 162 | |
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| 163 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 164 | vhdl->set_body (0,"sig_RES_BRANCH <="); |
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| 165 | vhdl->set_body (1,"reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-3)+" downto 0) & "+std_logic_cst(2,0)+"when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+") = '1') else"); |
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| 166 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); |
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| 167 | #else |
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| 168 | vhdl->set_body (0,"sig_RES_BRANCH <= reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_general_data-3)+" downto 0) & "+std_logic_cst(2,0)+";"); |
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| 169 | #endif |
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| 170 | |
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| 171 | vhdl->set_body (0,"sig_ADDR_BRANCH <="); |
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| 172 | vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB("+toString(_param->_size_instruction_address+1)+" downto 2) when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_BRANCH_L_JALR))+") = '1') else"); |
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| 173 | vhdl->set_body (1,"reg_EXECUTE_IN_IMMEDIAT("+toString(_param->_size_instruction_address-1)+" downto 0);"); |
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| 174 | |
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| 175 | vhdl->set_body (""); |
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| 176 | vhdl->set_comment(0,""); |
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| 177 | vhdl->set_comment(0,"SHIFTER"); |
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| 178 | vhdl->set_comment(0,""); |
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| 179 | |
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| 180 | vhdl->set_comment(0,"Instance shifter"); |
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| 181 | vhdl->set_body (0,"instance_"+_name+"_shifter : "+_name+"_shifter"); |
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| 182 | vhdl->set_body (0,"port map ("); |
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| 183 | vhdl->set_body (1," in_SHIFTER_0_DATA \t=>\treg_EXECUTE_IN_DATA_RA"); |
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| 184 | vhdl->set_body (1,", in_SHIFTER_0_SHIFT \t=>\tsig_B_OPERAND("+toString((log2(_param->_size_general_data))-1)+" downto 0)"); |
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| 185 | vhdl->set_body (1,", in_SHIFTER_0_DIRECTION \t=>\treg_EXECUTE_IN_OPERATION(0)"); |
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| 186 | vhdl->set_body (1,", in_SHIFTER_0_TYPE \t=>\treg_EXECUTE_IN_OPERATION(1)"); |
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| 187 | vhdl->set_body (1,", in_SHIFTER_0_CARRY \t=>\treg_EXECUTE_IN_OPERATION(2)"); |
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| 188 | vhdl->set_body (1,",out_SHIFTER_0_DATA \t=>\tsig_RES_SHIFTER"); |
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| 189 | vhdl->set_body (0,");"); |
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| 190 | vhdl->set_body (0,""); |
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| 191 | |
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| 192 | vhdl->set_body (""); |
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| 193 | vhdl->set_comment(0,""); |
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| 194 | vhdl->set_comment(0,"EXTEND"); |
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| 195 | vhdl->set_comment(0,""); |
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| 196 | |
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| 197 | vhdl->set_body (0,"sig_EXT_BYTE_S <="); |
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| 198 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,(1<<_param->_size_general_data-8)-1)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0) when (reg_EXECUTE_IN_DATA_RA (7) = '1') else"); |
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| 199 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,0)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0);"); |
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| 200 | vhdl->set_body (0,""); |
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| 201 | |
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| 202 | vhdl->set_body (0,"sig_EXT_BYTE_Z <="); |
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| 203 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-8,0)+" & reg_EXECUTE_IN_DATA_RA (7 downto 0);"); |
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| 204 | vhdl->set_body (0,""); |
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| 205 | |
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| 206 | vhdl->set_body (0,"sig_EXT_HALF_WORD_S <="); |
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| 207 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,(1<<_param->_size_general_data-16)-1)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0) when (reg_EXECUTE_IN_DATA_RA (15) = '1') else"); |
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| 208 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,0)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0);"); |
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| 209 | vhdl->set_body (0,""); |
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| 210 | |
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| 211 | vhdl->set_body (0,"sig_EXT_HALF_WORD_Z <="); |
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| 212 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-16,0)+" & reg_EXECUTE_IN_DATA_RA (15 downto 0);"); |
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| 213 | vhdl->set_body (0,""); |
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| 214 | |
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| 215 | vhdl->set_body (0,"sig_EXT_WORD_S <="); |
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| 216 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,(1<<_param->_size_general_data-32)-1)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0) when (reg_EXECUTE_IN_DATA_RA (31) = '1') else"); |
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| 217 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,0)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0);"); |
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| 218 | vhdl->set_body (0,""); |
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| 219 | |
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| 220 | vhdl->set_body (0,"sig_EXT_WORD_Z <="); |
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| 221 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-32,0)+" & reg_EXECUTE_IN_DATA_RA (31 downto 0);"); |
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| 222 | vhdl->set_body (0,""); |
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| 223 | |
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| 224 | vhdl->set_body (0,"sig_EXT_S <="); |
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| 225 | vhdl->set_body (1,"sig_EXT_BYTE_S when (reg_EXECUTE_IN_IMMEDIAT = 8) else"); |
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| 226 | vhdl->set_body (1,"sig_EXT_HALF_WORD_S when (reg_EXECUTE_IN_IMMEDIAT = 16) else"); |
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| 227 | vhdl->set_body (1,"sig_EXT_WORD_S;"); |
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| 228 | vhdl->set_body (0,""); |
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| 229 | |
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| 230 | vhdl->set_body (0,"sig_EXT_Z <="); |
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| 231 | vhdl->set_body (1,"sig_EXT_BYTE_Z when (reg_EXECUTE_IN_IMMEDIAT = 8) else"); |
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| 232 | vhdl->set_body (1,"sig_EXT_HALF_WORD_Z when (reg_EXECUTE_IN_IMMEDIAT = 16) else"); |
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| 233 | vhdl->set_body (1,"sig_EXT_WORD_Z;"); |
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| 234 | vhdl->set_body (0,""); |
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| 235 | |
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| 236 | vhdl->set_body (0,"sig_RES_EXTEND <="); |
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| 237 | vhdl->set_body (1,"sig_EXT_Z when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_EXTEND_L_EXTEND_Z))+") = '1') else"); |
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| 238 | vhdl->set_body (1,"sig_EXT_S;"); |
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| 239 | vhdl->set_body (0,""); |
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| 240 | |
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| 241 | vhdl->set_body (0,""); |
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| 242 | vhdl->set_comment(0,""); |
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| 243 | vhdl->set_comment(0,"FIND"); |
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| 244 | vhdl->set_comment(0,""); |
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| 245 | |
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| 246 | vhdl->set_body (0,"sig_FF1 <="); |
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| 247 | for (uint32_t i=0; i<_param->_size_general_data; i++) |
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| 248 | vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,i+1)+" \twhen (reg_EXECUTE_IN_DATA_RA ("+toString(i)+") = '1') \telse"); |
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| 249 | vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,0)+";"); |
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| 250 | vhdl->set_body (0,""); |
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| 251 | |
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| 252 | vhdl->set_body (0,"sig_FL1 <="); |
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| 253 | for (uint32_t i=_param->_size_general_data; i>0; i--) |
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| 254 | vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,i)+" \twhen (reg_EXECUTE_IN_DATA_RA ("+toString(i-1)+") = '1') \telse"); |
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| 255 | vhdl->set_body (1,std_logic_cst(log2(_param->_size_general_data)+1,0)+";"); |
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| 256 | vhdl->set_body (0,""); |
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| 257 | |
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| 258 | vhdl->set_body (0,"sig_RES_FIND <="); |
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| 259 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-log2(_param->_size_general_data)-1,0)+"&"+"sig_FF1 when (reg_EXECUTE_IN_OPERATION("+toString(log2(OPERATION_FIND_L_FF1))+") = '1') else"); |
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| 260 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data-log2(_param->_size_general_data)-1,0)+"&"+"sig_FL1;"); |
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| 261 | vhdl->set_body (0,""); |
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| 262 | |
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| 263 | vhdl->set_body (0,""); |
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| 264 | vhdl->set_comment(0,""); |
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| 265 | vhdl->set_comment(0,"SPECIAL"); |
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| 266 | vhdl->set_comment(0,""); |
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| 267 | |
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| 268 | vhdl->set_body (0,"sig_SPR_IS_HERE <="); |
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| 269 | // vhdl->set_body (1,"'1' when (sig_A_OR_B("+toString(_param->_size_special_address_group+_param->_size_special_address_register-1)+" downto "+toString(_param->_size_special_address_register)+") = "+std_logic_cst(_param->_size_special_address_group,GROUP_MAC)+") else"); |
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| 270 | vhdl->set_body (1,"'1' when (sig_A_OR_B(15 downto 0) = "+std_logic_cst(_param->_size_special_address_group,GROUP_MAC)+") else"); |
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| 271 | vhdl->set_body (1,"'0';"); |
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| 272 | |
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| 273 | vhdl->set_comment(0,"MFSPR"); |
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| 274 | vhdl->set_body (0,"sig_MFSPR <="); |
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| 275 | vhdl->set_body (1,"reg_MACLO"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" when (sig_SPR_IS_HERE = '1' and sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACLO)+") else"); |
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| 276 | vhdl->set_body (1,"reg_MACHI"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" when (sig_SPR_IS_HERE = '1' and sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACHI)+") else"); |
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| 277 | vhdl->set_body (1,std_logic_cst(_param->_size_spr,0)+";"); |
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| 278 | vhdl->set_body (0,""); |
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| 279 | |
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| 280 | vhdl->set_body (0,""); |
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| 281 | |
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| 282 | vhdl->set_comment(0,"MTSPR"); |
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| 283 | vhdl->set_body (0,"process (in_CLOCK)"); |
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| 284 | vhdl->set_body (0,"begin"); |
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| 285 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 286 | vhdl->set_body (2,"if (sig_SPR_IS_HERE = '1') then"); |
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| 287 | vhdl->set_body (3,"if (sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACLO)+") then"); |
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| 288 | vhdl->set_body (4,"reg_MACLO"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" <= reg_EXECUTE_IN_DATA_RB;"); |
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| 289 | vhdl->set_body (3,"end if;"); |
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| 290 | vhdl->set_body (3,"if (sig_A_OR_B("+toString(_param->_size_special_address_register-1)+" downto 0) = "+std_logic_cst(_param->_size_special_address_register,SPR_MACHI)+") then"); |
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| 291 | vhdl->set_body (4,"reg_MACHI"+toString((_param->_have_port_context_id == 1) ? "(reg_EXECUTE_IN_CONTEXT_ID)" : "(0)")+" <= reg_EXECUTE_IN_DATA_RB;"); |
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| 292 | vhdl->set_body (3,"end if;"); |
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| 293 | vhdl->set_body (2,"end if;"); |
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| 294 | vhdl->set_body (1,"end if;"); |
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| 295 | vhdl->set_body (0,"end process;"); |
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| 296 | vhdl->set_body (0,""); |
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| 297 | |
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| 298 | vhdl->set_body (0,"sig_RES_SPECIAL <="); |
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| 299 | vhdl->set_body (1,"sig_MFSPR when (reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MFSPR)+") else"); |
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| 300 | vhdl->set_body (1,"reg_EXECUTE_IN_DATA_RB when (reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MTSPR)+") else"); |
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| 301 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+";"); |
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| 302 | vhdl->set_body (0,""); |
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| 303 | |
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| 304 | vhdl->set_body (0,""); |
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| 305 | vhdl->set_comment(0,""); |
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| 306 | vhdl->set_comment(0,"TRANSACTION"); |
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| 307 | vhdl->set_comment(0,""); |
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| 308 | // vhdl->set_body (0,"sig_EXECUTE_OUT_VAL <= reg_BUSY_IN;"); |
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| 309 | // vhdl->set_body (0,"sig_EXECUTE_IN_ACK <= not reg_BUSY_IN or (reg_BUSY_IN and in_EXECUTE_OUT_ACK);"); |
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| 310 | |
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| 311 | vhdl->set_body (0,"sig_EXECUTE_OUT_VAL <= reg_BUSY_OUT;"); |
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| 312 | vhdl->set_body (0,"sig_EXECUTE_OUT_UPDATE <= not reg_BUSY_OUT or (reg_BUSY_OUT and in_EXECUTE_OUT_ACK);"); |
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| 313 | vhdl->set_body (0,"sig_EXECUTE_IN_ACK <= not reg_BUSY_IN or (reg_BUSY_IN and sig_EXECUTE_OUT_UPDATE);"); |
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| 314 | |
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| 315 | vhdl->set_body (""); |
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| 316 | vhdl->set_comment(0,""); |
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| 317 | vhdl->set_comment(0,"-----------------------------------"); |
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| 318 | vhdl->set_comment(0,"-- "); |
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| 319 | vhdl->set_comment(0,"-----------------------------------"); |
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| 320 | vhdl->set_comment(0,""); |
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| 321 | vhdl->set_body (""); |
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| 322 | if(_param->_have_port_context_id) |
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| 323 | vhdl->set_body (0,"sig_EXECUTE_OUT_CONTEXT_ID <= reg_EXECUTE_IN_CONTEXT_ID;"); |
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| 324 | |
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| 325 | if(_param->_have_port_front_end_id) |
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| 326 | vhdl->set_body (0,"sig_EXECUTE_OUT_FRONT_END_ID <= reg_EXECUTE_IN_FRONT_END_ID;"); |
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| 327 | |
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| 328 | if(_param->_have_port_ooo_engine_id) |
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| 329 | vhdl->set_body (0,"sig_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_IN_OOO_ENGINE_ID;"); |
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| 330 | |
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| 331 | if(_param->_have_port_rob_ptr) |
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| 332 | vhdl->set_body (0,"sig_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_IN_PACKET_ID;"); |
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| 333 | |
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| 334 | vhdl->set_body (0,"sig_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_IN_WRITE_RD;"); |
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| 335 | |
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| 336 | vhdl->set_body (0,"sig_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_IN_NUM_REG_RD;"); |
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| 337 | |
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| 338 | vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); |
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| 339 | vhdl->set_body (0,"sig_EXECUTE_OUT_DATA_RD <="); |
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| 340 | vhdl->set_body (1,"sig_RES_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); |
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| 341 | vhdl->set_body (1,"sig_RES_MOVE when "+std_logic_cst(_param->_size_type,TYPE_MOVE)+","); |
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| 342 | vhdl->set_body (1,"sig_RES_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); |
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| 343 | vhdl->set_body (1,"sig_RES_SHIFTER when "+std_logic_cst(_param->_size_type,TYPE_SHIFT)+","); |
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| 344 | vhdl->set_body (1,"sig_RES_EXTEND when "+std_logic_cst(_param->_size_type,TYPE_EXTEND)+","); |
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| 345 | vhdl->set_body (1,"sig_RES_FIND when "+std_logic_cst(_param->_size_type,TYPE_FIND)+","); |
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| 346 | vhdl->set_body (1,"sig_RES_SPECIAL when "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+","); |
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| 347 | vhdl->set_body (1,std_logic_cst(_param->_size_general_data,0)+" when others;"); |
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| 348 | |
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| 349 | vhdl->set_body (0,"sig_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_IN_WRITE_RE;"); |
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| 350 | |
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| 351 | vhdl->set_body (0,"sig_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_IN_NUM_REG_RE;"); |
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| 352 | |
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| 353 | vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); |
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| 354 | vhdl->set_body (0,"sig_EXECUTE_OUT_DATA_RE <="); |
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| 355 | if(FLAG_POSITION_CY > FLAG_POSITION_OV) |
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| 356 | vhdl->set_body (1,"sig_COUT_ALU & sig_OVR_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); |
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| 357 | else |
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| 358 | vhdl->set_body (1,"sig_OVR_ALU & sig_COUT_ALU when "+std_logic_cst(_param->_size_type,TYPE_ALU)+","); |
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| 359 | vhdl->set_body (1,std_logic_cst(_param->_size_special_data,0)+" when others;"); |
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| 360 | |
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| 361 | vhdl->set_body (0,"sig_EXECUTE_OUT_EXCEPTION <="); |
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| 362 | vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_RANGE)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_ALU)+" and sig_OVR_ALU = '1') else"); |
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| 363 | vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_SPR_ACCESS_MUST_READ)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+" and reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MFSPR)+" and sig_SPR_IS_HERE = '0') else"); |
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| 364 | vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE)+" when (reg_EXECUTE_IN_TYPE = "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+" and reg_EXECUTE_IN_OPERATION = "+std_logic_cst(_param->_size_operation,OPERATION_SPECIAL_L_MTSPR)+" and sig_SPR_IS_HERE = '0') else"); |
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| 365 | vhdl->set_body (1,std_logic_cst(_param->_size_exception,EXCEPTION_NONE)+";"); |
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| 366 | |
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| 367 | vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); |
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| 368 | vhdl->set_body (0,"sig_EXECUTE_OUT_NO_SEQUENCE <="); |
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| 369 | vhdl->set_body (1,"sig_NOSQ_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); |
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| 370 | vhdl->set_body (1,std_logic_cst(1,0)+"when others;"); |
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| 371 | |
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| 372 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 373 | vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); |
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| 374 | vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <="); |
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| 375 | vhdl->set_body (1,"sig_ADDR_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); |
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| 376 | vhdl->set_body (1,"sig_A_OR_B("+toString(_param->_size_instruction_address-1)+" downto 0) when "+std_logic_cst(_param->_size_type,TYPE_SPECIAL)+","); |
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| 377 | vhdl->set_body (1,std_logic_cst(_param->_size_instruction_address,0)+" when others;"); |
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| 378 | #else |
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| 379 | vhdl->set_body (0,"with reg_EXECUTE_IN_TYPE select"); |
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| 380 | vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <="); |
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| 381 | vhdl->set_body (1,"sig_ADDR_BRANCH when "+std_logic_cst(_param->_size_type,TYPE_BRANCH)+","); |
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| 382 | vhdl->set_body (1,"sig_A_OR_B when others;"); |
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| 383 | // vhdl->set_body (0,"sig_EXECUTE_OUT_ADDRESS <= sig_ADDR_BRANCH;"); |
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| 384 | #endif |
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| 385 | |
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| 386 | vhdl->set_body (""); |
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| 387 | vhdl->set_comment(0,""); |
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| 388 | vhdl->set_comment(0,"-----------------------------------"); |
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| 389 | vhdl->set_comment(0,"-- Outputs "); |
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| 390 | vhdl->set_comment(0,"-----------------------------------"); |
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| 391 | vhdl->set_comment(0,""); |
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| 392 | vhdl->set_body (""); |
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| 393 | // if(_param->_have_port_context_id) |
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| 394 | // vhdl->set_body (0,"out_EXECUTE_OUT_CONTEXT_ID <= sig_EXECUTE_OUT_CONTEXT_ID;"); |
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| 395 | // if(_param->_have_port_front_end_id) |
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| 396 | // vhdl->set_body (0,"out_EXECUTE_OUT_FRONT_END_ID <= sig_EXECUTE_OUT_FRONT_END_ID;"); |
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| 397 | // if(_param->_have_port_ooo_engine_id) |
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| 398 | // vhdl->set_body (0,"out_EXECUTE_OUT_OOO_ENGINE_ID <= sig_EXECUTE_OUT_OOO_ENGINE_ID;"); |
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| 399 | // if(_param->_have_port_rob_ptr) |
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| 400 | // vhdl->set_body (0,"out_EXECUTE_OUT_PACKET_ID <= sig_EXECUTE_OUT_PACKET_ID;"); |
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| 401 | // vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RD <= sig_EXECUTE_OUT_WRITE_RD;"); |
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| 402 | // vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RD <= sig_EXECUTE_OUT_NUM_REG_RD;"); |
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| 403 | // vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RD <= sig_EXECUTE_OUT_DATA_RD;"); |
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| 404 | // vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RE <= sig_EXECUTE_OUT_WRITE_RE;"); |
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| 405 | // vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RE <= sig_EXECUTE_OUT_NUM_REG_RE;"); |
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| 406 | // vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RE <= sig_EXECUTE_OUT_DATA_RE;"); |
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| 407 | // vhdl->set_body (0,"out_EXECUTE_OUT_EXCEPTION <= sig_EXECUTE_OUT_EXCEPTION;"); |
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| 408 | // vhdl->set_body (0,"out_EXECUTE_OUT_NO_SEQUENCE <= sig_EXECUTE_OUT_NO_SEQUENCE;"); |
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| 409 | // vhdl->set_body (0,"out_EXECUTE_OUT_ADDRESS <= sig_EXECUTE_OUT_ADDRESS;"); |
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| 410 | // vhdl->set_body (0,"out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL;"); |
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| 411 | // vhdl->set_body (0,"out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK;"); |
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| 412 | |
---|
| 413 | if(_param->_have_port_context_id) |
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| 414 | vhdl->set_body (0,"out_EXECUTE_OUT_CONTEXT_ID <= reg_EXECUTE_OUT_CONTEXT_ID;"); |
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| 415 | if(_param->_have_port_front_end_id) |
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| 416 | vhdl->set_body (0,"out_EXECUTE_OUT_FRONT_END_ID <= reg_EXECUTE_OUT_FRONT_END_ID;"); |
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| 417 | if(_param->_have_port_ooo_engine_id) |
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| 418 | vhdl->set_body (0,"out_EXECUTE_OUT_OOO_ENGINE_ID <= reg_EXECUTE_OUT_OOO_ENGINE_ID;"); |
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| 419 | if(_param->_have_port_rob_ptr) |
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| 420 | vhdl->set_body (0,"out_EXECUTE_OUT_PACKET_ID <= reg_EXECUTE_OUT_PACKET_ID;"); |
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| 421 | vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RD <= reg_EXECUTE_OUT_WRITE_RD;"); |
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| 422 | vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RD <= reg_EXECUTE_OUT_NUM_REG_RD;"); |
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| 423 | vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RD <= reg_EXECUTE_OUT_DATA_RD;"); |
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| 424 | vhdl->set_body (0,"out_EXECUTE_OUT_WRITE_RE <= reg_EXECUTE_OUT_WRITE_RE;"); |
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| 425 | vhdl->set_body (0,"out_EXECUTE_OUT_NUM_REG_RE <= reg_EXECUTE_OUT_NUM_REG_RE;"); |
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| 426 | vhdl->set_body (0,"out_EXECUTE_OUT_DATA_RE <= reg_EXECUTE_OUT_DATA_RE;"); |
---|
| 427 | vhdl->set_body (0,"out_EXECUTE_OUT_EXCEPTION <= reg_EXECUTE_OUT_EXCEPTION;"); |
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| 428 | vhdl->set_body (0,"out_EXECUTE_OUT_NO_SEQUENCE <= reg_EXECUTE_OUT_NO_SEQUENCE;"); |
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| 429 | vhdl->set_body (0,"out_EXECUTE_OUT_ADDRESS <= reg_EXECUTE_OUT_ADDRESS;"); |
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| 430 | vhdl->set_body (0,"out_EXECUTE_OUT_VAL <= sig_EXECUTE_OUT_VAL;"); |
---|
| 431 | vhdl->set_body (0,"out_EXECUTE_IN_ACK <= sig_EXECUTE_IN_ACK;"); |
---|
| 432 | |
---|
[72] | 433 | log_printf(FUNC,Functionnal_unit,FUNCTION,"End"); |
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| 434 | }; |
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| 435 | |
---|
| 436 | }; // end namespace functionnal_unit |
---|
| 437 | }; // end namespace execute_unit |
---|
| 438 | }; // end namespace multi_execute_unit |
---|
| 439 | }; // end namespace execute_loop |
---|
| 440 | }; // end namespace multi_execute_loop |
---|
| 441 | }; // end namespace core |
---|
| 442 | |
---|
| 443 | }; // end namespace behavioural |
---|
| 444 | }; // end namespace morpheo |
---|
| 445 | #endif |
---|