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test.cpp @ 62

Last change on this file since 62 was 62, checked in by rosiere, 17 years ago
Modification en profondeur de Component-port_map. Compilation ok pour Register_unit ... a tester (systemC et vhdl)
File size: 33.1 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11	#include "Common/include/Test.h"
12	#include "Common/include/BitManipulation.h"
13
14	#define NB_ITERATION 1
15	#define CYCLE_MAX (128*NB_ITERATION)
16
17	#define LABEL(str) \
18	{ \
19	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \
20	} while(0)
21
22	static uint32_t cycle = 0;
23
24	#define SC_START(cycle_offset) \
25	do \
26	{ \
27	/cout << "SC_START (begin)" << endl;/ \
28	\
29	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
30	if (cycle_current != cycle) \
31	{ \
32	cycle = cycle_current; \
33	cout << "##########[ cycle "<< cycle << " ]" << endl; \
34	} \
35	\
36	if (cycle_current > CYCLE_MAX) \
37	{ \
38	TEST_KO("Maximal cycles Reached"); \
39	} \
40	sc_start(cycle_offset); \
41	/cout << "SC_START (end )" << endl;/ \
42	} while(0)
43
44
45
46	//========================================================={MemoryRequest_t}
47	class MemoryRequest_t
48	{
49	public : double _cycle ;
50	public : Tcontext_t _context_id ;
51	public : Tpacket_t _packet_id ;
52	public : Toperation_t _operation ;
53	public : Ttype_t _type ;
54	public : Tlsq_ptr_t _store_queue_ptr_write;
55	public : Tlsq_ptr_t _load_queue_ptr_write ;
56	public : Tgeneral_data_t _immediat ;
57	public : Tgeneral_data_t _data_ra ;
58	public : Tgeneral_data_t _data_rb ;
59	public : Tcontrol_t _write_rd ;
60	public : Tgeneral_address_t _num_reg_rd ;
61	public : bool _write_spec_ko ;
62
63	MemoryRequest_t (void)
64	{
65	_cycle = 0;
66	_context_id = 0;
67	_packet_id = 0;
68	_operation = 0;
69	_type = 0;
70	_store_queue_ptr_write = 0;
71	_load_queue_ptr_write = 0;
72	_immediat = 0;
73	_data_ra = 0;
74	_data_rb = 0;
75	_write_rd = 0;
76	_num_reg_rd = 0;
77	_write_spec_ko = 0;
78	};
79
80	MemoryRequest_t (double cycle ,
81	Tcontext_t context_id ,
82	Tpacket_t packet_id ,
83	Toperation_t operation ,
84	Ttype_t type ,
85	Tlsq_ptr_t store_queue_ptr_write,
86	Tlsq_ptr_t load_queue_ptr_write ,
87	Tgeneral_data_t immediat ,
88	Tgeneral_data_t data_ra ,
89	Tgeneral_data_t data_rb ,
90	Tcontrol_t write_rd ,
91	Tgeneral_address_t num_reg_rd ,
92	bool write_spec_ko )
93	{
94	_cycle = cycle ;
95	_context_id = context_id ;
96	_packet_id = packet_id ;
97	_operation = operation ;
98	_type = type ;
99	_store_queue_ptr_write = store_queue_ptr_write;
100	_load_queue_ptr_write = load_queue_ptr_write ;
101	_immediat = immediat ;
102	_data_ra = data_ra ;
103	_data_rb = data_rb ;
104	_write_rd = write_rd ;
105	_num_reg_rd = num_reg_rd ;
106	_write_spec_ko = write_spec_ko ;
107	}
108
109	void modif (double cycle ,
110	Tcontext_t context_id ,
111	Tpacket_t packet_id ,
112	Toperation_t operation ,
113	Ttype_t type ,
114	Tlsq_ptr_t store_queue_ptr_write,
115	Tlsq_ptr_t load_queue_ptr_write ,
116	Tgeneral_data_t immediat ,
117	Tgeneral_data_t data_ra ,
118	Tgeneral_data_t data_rb ,
119	Tcontrol_t write_rd ,
120	Tgeneral_address_t num_reg_rd ,
121	bool write_spec_ko )
122	{
123	_cycle = cycle ;
124	_context_id = context_id ;
125	_packet_id = packet_id ;
126	_operation = operation ;
127	_type = type ;
128	_store_queue_ptr_write = store_queue_ptr_write;
129	_load_queue_ptr_write = load_queue_ptr_write ;
130	_immediat = immediat ;
131	_data_ra = data_ra ;
132	_data_rb = data_rb ;
133	_write_rd = write_rd ;
134	_num_reg_rd = num_reg_rd ;
135	_write_spec_ko = write_spec_ko ;
136	}
137
138	bool operator< (const MemoryRequest_t & right) const
139	{
140	return _cycle > right._cycle;
141	}
142
143	friend ostream& operator<<(ostream &, const MemoryRequest_t &);
144	};
145
146	ostream & operator << (ostream& os, const MemoryRequest_t & x)
147	{
148	return os << "<" << toString(x._cycle) << "> : "
149	<< "{" << toString(static_cast<uint32_t>(x._packet_id)) << "}" << endl
150	<< "\t * context_id : " << toString(static_cast<uint32_t>(x._context_id)) << endl
151	<< "\t * operation / type / write_spec_ko : " << toString(static_cast<uint32_t>(x._operation)) << " " << toString(static_cast<uint32_t>(x._type)) << " " << toString(static_cast<uint32_t>(x._write_spec_ko)) << endl
152	<< "\t * ptr_write store/load : " << toString(static_cast<uint32_t>(x._store_queue_ptr_write)) << " " << toString(static_cast<uint32_t>(x._load_queue_ptr_write)) << endl
153	<< "\t * immediat / data_ra / data_rb : " << toString(static_cast<uint32_t>(x._immediat)) << " - " << toString(static_cast<uint32_t>(x._data_ra)) << " - " << toString(static_cast<uint32_t>(x._data_rb)) << endl
154	<< "\t * write_rd / num_reg_rd : " << toString(static_cast<uint32_t>(x._write_rd)) << " " << toString(static_cast<uint32_t>(x._num_reg_rd)) << endl;
155	}
156
157	//================================================================{Memory_t}
158	class Memory_t
159	{
160	private : const uint32_t _nb_context;
161	private : const uint32_t _nb_word ;
162	private : const uint32_t _size_data ;
163	private : const Tdcache_address_t _mask_addr ;
164	private : Tdcache_data_t ** _data;
165
166	public : Memory_t (uint32_t nb_context,
167	uint32_t nb_word,
168	uint32_t size_data):
169	_nb_context (nb_context),
170	_nb_word (nb_word ),
171	_size_data (size_data ),
172	_mask_addr (gen_mask<Tdcache_address_t>(static_cast<uint32_t>(log2(ceil(static_cast<double>(size_data))))))
173	{
174	_data = new Tdcache_data_t * [nb_context];
175
176	for (uint32_t i=0; i<nb_context; i++)
177	{
178	_data [i] = new Tdcache_data_t [nb_word];
179
180	for (uint32_t j=0; j<nb_word; j++)
181	_data [i][j] = rand()%(size_data);
182	}
183	}
184
185	public : ~Memory_t (void)
186	{
187	delete [] _data;
188	}
189
190	public : Tdcache_data_t access (uint32_t context,
191	Tdcache_address_t address,
192	Tdcache_type_t type,
193	Tdcache_data_t data)
194	{
195	return 0;
196	}
197
198	public : Tdcache_data_t read (uint32_t context,
199	Tdcache_address_t address,
200	Tdcache_type_t type)
201	{
202	// Address's Read must be aligned
203
204	if ((address & _mask_addr) != 0)
205	TEST_KO("<Memory_t::read> Address is not aligned");
206
207	if (context>_nb_context)
208	TEST_KO("<Memory_t::read> nb context is too high");
209
210	if (address>_nb_word)
211	TEST_KO("<Memory_t::read> address is too high");
212
213	return _data [context][address];
214	}
215
216	public : void write (uint32_t context,
217	Tdcache_address_t address,
218	Tdcache_type_t type,
219	Tdcache_data_t data)
220	{
221	if (context>_nb_context)
222	TEST_KO("<Memory_t::read> nb context is too high");
223
224	if (address>_nb_word)
225	TEST_KO("<Memory_t::read> address is too high");
226
227	Tdcache_address_t LSB = address & _mask;
228	Tdcache_address_t MSB = address & ~_mask;
229
230	Tdcache_data_t write_data = data;
231	Tdcache_data_t read_data = _data [context][MSB];
232
233	// exemple to size_data = 32b
234	// LSB index_min
235	// 0 0
236	// 1 8
237	// 2 16
238	// 3 24
239	uint32_t index_min = LSB<<3;
240	uint32_t index_max = index_min;
241	// index max, dependant of access's size
242
243	switch (type)
244	{
245
246
247	}
248	}
249	};
250
251	//===================================================================={test}
252	void test (string name,
253	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param)
254	{
255	cout << "<" << name << "> : Simulation SystemC" << endl;
256
257	#ifdef STATISTICS
258	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
259	#endif
260
261	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
262	#ifdef STATISTICS
263	_parameters_statistics,
264	#endif
265	_param);
266
267	#ifdef SYSTEMC
268	/*********************************************************************
269	* Déclarations des signaux
270	*********************************************************************/
271	string rename = "";
272
273	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
274	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
275
276	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
277	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
278	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
279	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
280	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
281	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
282	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
283	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
284	//sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
285	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
286	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
287	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
288	//sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
289	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
290	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
291	//sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
292	//sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
293
294	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
295	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
296	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
297	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
298	sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
299	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
300	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
301	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
302	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
303	//sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
304	//sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
305	//sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
306	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
307
308	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
309	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
310	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
311	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
312	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
313	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
314	sc_signal<Tcontrol_t > * out_DCACHE_REQ_UNCACHED = new sc_signal<Tcontrol_t >(rename.c_str());
315	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
316
317	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
318	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
319	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
320	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
321	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
322	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
323
324	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_size_load_queue];
325	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_size_load_queue];
326	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_size_load_queue];
327	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_size_load_queue];
328
329	for (uint32_t i=0; i<_param->_size_load_queue; i++)
330	{
331	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >;
332	out_BYPASS_MEMORY_CONTEXT_ID [i] = new sc_signal<Tcontext_t >;
333	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>;
334	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >;
335	}
336
337	/********************************************************
338	* Instanciation
339	********************************************************/
340
341	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
342
343	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
344	((_Load_store_unit->in_NRESET)) ((in_NRESET));
345
346	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
347	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
348	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
349	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
350	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
351	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
352	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
353	//((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
354	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
355	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
356	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
357	//((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
358	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
359	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
360	//((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
361	//((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
362
363	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
364	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
365	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
366	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
367	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
368	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
369	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
370	//((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
371	//((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
372	//((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
373	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
374
375	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
376	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
377	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
378	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
379	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
380	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
381	((_Load_store_unit->out_DCACHE_REQ_UNCACHED ))((out_DCACHE_REQ_UNCACHED ));
382	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
383
384	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
385	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
386	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
387	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
388	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
389	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
390
391	if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS)
392	{
393	for (uint32_t i=0; i<_param->_size_load_queue; i++)
394	{
395	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
396	((_Load_store_unit->out_BYPASS_MEMORY_CONTEXT_ID [i]))((out_BYPASS_MEMORY_CONTEXT_ID [i]));
397	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
398	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
399	}
400	}
401	cout << "<" << name << "> Start Simulation ............" << endl;
402	Time * _time = new Time();
403
404	/********************************************************
405	* Simulation - Begin
406	********************************************************/
407
408	// Initialisation
409
410	const uint32_t seed = 0;
411	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
412
413	srand(seed);
414
415	const uint32_t nb_request = _param->_nb_packet;
416	const uint32_t nb_word = nb_request;
417
418	//const int32_t percent_transaction_memory_in = 100;
419	const int32_t percent_transaction_memory_out = 100;
420	const int32_t percent_transaction_dcache = 100;
421
422	const int32_t percent_exception = 5;
423	const int32_t percent_type_load = 0;
424	const int32_t percent_type_store = 100;
425	const int32_t percent_miss_spec = 0;
426
427	if ((percent_type_load +
428	percent_type_store ) > 100)
429	TEST_KO("sum of percent_type > 100");
430
431	const int32_t seuil_type_load = percent_type_load;
432	const int32_t seuil_type_store = percent_type_store+percent_type_load;
433
434	uint32_t nb_request_memory_in ;
435	uint32_t nb_request_memory_out;
436	uint32_t nb_request_dcache ;
437
438	MemoryRequest_t tab_request [nb_request];
439	priority_queue<MemoryRequest_t> fifo_request;
440
441	// emulation of cache
442	Tdcache_data_t cache_data [_param->_nb_context][nb_word];
443
444	SC_START(0);
445
446	LABEL("Initialisation");
447
448	// emulate a memory
449	for (uint32_t i=0; i<_param->_nb_context; i++)
450	for (uint32_t j=0; j<nb_word; j++)
451	cache_data [i][j] = rand()%(1<<_param->_size_general_data);
452
453	in_MEMORY_IN_VAL ->write(0);
454	in_MEMORY_OUT_ACK->write(0);
455	in_DCACHE_REQ_ACK->write(0);
456	in_DCACHE_RSP_VAL->write(0);
457
458	in_NRESET ->write(0);
459	SC_START(5);
460	in_NRESET ->write(5);
461
462	LABEL("Loop of Test");
463
464	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
465	{
466	LABEL("Iteration "+toString(iteration));
467
468	LABEL("Structure's initialisation");
469
470	nb_request_memory_in = 0;
471	nb_request_memory_out = 0;
472	nb_request_dcache = 0;
473
474	// Fill the request_queue
475
476	Tlsq_ptr_t store_queue_ptr_write = 0;
477	Tlsq_ptr_t load_queue_ptr_write = 0;
478
479	bool store_queue_use [_param->_size_store_queue];
480	bool load_queue_use [_param->_size_load_queue ];
481
482	for (uint32_t i=0; i<_param->_size_store_queue; i++)
483	store_queue_use [i] = false;
484	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
485	load_queue_use [i] = false;
486
487	double current_cycle = sc_simulation_time();
488	double cycle_min = current_cycle;
489
490	LABEL("Fifo request initialisation");
491	// Init fifo_request
492	for (uint32_t i=0; i<nb_request; i++)
493	{
494	double cycle;
495	Tcontext_t context_id = rand () % _param->_nb_context;
496	Tpacket_t packet_id = i;
497	Tlsq_ptr_t store_queue_ptr_write_old = store_queue_ptr_write;
498	Tlsq_ptr_t load_queue_ptr_write_old = load_queue_ptr_write ;
499	Toperation_t operation;
500
501	int32_t percent = rand()%100;
502
503	uint32_t size_queue;
504
505	if (percent <= seuil_type_load)
506	{
507	// LABEL(" * LOAD");
508	operation = OPERATION_MEMORY_LOAD_16_S;
509	size_queue = _param->_size_load_queue;
510	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
511	}
512	else
513	{
514	if (percent <= seuil_type_store)
515	{
516	// LABEL(" * STORE");
517	operation = OPERATION_MEMORY_STORE_16;
518	size_queue = _param->_size_store_queue;
519	store_queue_ptr_write = (store_queue_ptr_write+1) % (size_queue);
520	}
521	else
522	{
523	// LABEL(" * OTHERS");
524	operation = OPERATION_MEMORY_PREFETCH;
525	size_queue = _param->_size_load_queue;
526	load_queue_ptr_write = (load_queue_ptr_write+1) % (size_queue);
527	}
528	}
529
530	cycle = cycle_min;
531	cycle_min ++;
532
533	Ttype_t type = TYPE_MEMORY;
534	Tgeneral_data_t address = rand()%(nb_word);
535	Tgeneral_data_t offset = rand()%(nb_word);
536
537	percent = rand()%100;
538	if (percent > percent_exception)
539	address = address & (not mask_memory_access(operation));
540
541	if (offset > address) // max
542	offset = address;
543
544	Tgeneral_data_t immediat = offset;
545	Tgeneral_data_t data_ra = address - offset;
546	Tgeneral_data_t data_rb = rand()%(1<<_param->_size_general_data);
547	Tcontrol_t write_rd = 0;
548	Tgeneral_address_t num_reg_rd = 0;
549	bool write_spec_ko = ((rand()%100)<percent_miss_spec);
550
551	tab_request [i].modif(cycle ,
552	context_id ,
553	packet_id ,
554	operation ,
555	type ,
556	store_queue_ptr_write_old,
557	load_queue_ptr_write_old ,
558	immediat ,
559	data_ra ,
560	data_rb ,
561	write_rd ,
562	num_reg_rd ,
563	write_spec_ko
564	);
565
566	cout << tab_request [i] << endl;
567
568	fifo_request.push(tab_request [i]);
569
570	double cycle_head = 0;
571
572	if (is_operation_memory_store(operation))
573	{
574	cycle_head = cycle_min;
575	cycle_min ++;
576
577	cout << " * Write head : " << toString(cycle_head)
578	<< endl
579	<< endl;
580
581	fifo_request.push(MemoryRequest_t(cycle_head,
582	context_id,
583	packet_id,
584	(write_spec_ko==true)?OPERATION_MEMORY_STORE_HEAD_KO:OPERATION_MEMORY_STORE_HEAD_OK,
585	type,
586	store_queue_ptr_write_old,
587	0,
588	0,
589	0,
590	0,
591	0,
592	0,
593	write_spec_ko));
594	}
595	}
596
597	LABEL("Simulation of this iteration ...");
598
599	while (nb_request_memory_out < nb_request)
600	{
601	// *** MEMORY_IN ***
602
603	// memory_in_val depends of three factors :
604	// 1) request's fifo is not empty ?
605	// 2) the slot destination is free ?
606	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
607
608	bool can_execute = false;
609
610	if (is_operation_memory_store(fifo_request.top()._operation))
611	can_execute = (not store_queue_use [fifo_request.top()._store_queue_ptr_write]) or is_operation_memory_store_head(fifo_request.top()._operation);
612	else
613	can_execute = not load_queue_use [fifo_request.top()._load_queue_ptr_write];
614
615	in_MEMORY_IN_VAL ->write((not fifo_request.empty()) and
616	can_execute and
617	(sc_simulation_time() >= fifo_request.top()._cycle));
618
619	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
620	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
621	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
622	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
623	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
624	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
625	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
626	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
627	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
628	in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
629	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
630
631	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
632
633	// *** DCACHE_REQ ***
634	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
635
636	SC_START(0);
637
638	SC_START(1);
639
640	LABEL("MEMORY_IN : "+toString(in_MEMORY_IN_VAL ->read())+" - "+toString(out_MEMORY_IN_ACK ->read()));
641	LABEL(" * fifo_request.empty : "+toString(fifo_request.empty()));
642	LABEL(" * fifo_request.top.cycle : "+toString(fifo_request.top()._cycle));
643	LABEL(" * fifo_request.top.store_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._store_queue_ptr_write)));
644	LABEL(" * fifo_request.top.load_queue_ptr_write : "+toString(static_cast<uint32_t>(fifo_request.top()._load_queue_ptr_write)));
645	LABEL(" * fifo_request.top.operation : "+toString(static_cast<uint32_t>(fifo_request.top()._operation )));
646	LABEL(" * can_execute : "+toString(can_execute));
647
648	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
649	{
650	LABEL(" * Accepted MEMORY_IN : " + toString(nb_request_memory_in));
651	cout << fifo_request.top();
652
653	if (is_operation_memory_store(fifo_request.top()._operation))
654	{
655	if (not is_operation_memory_store_head(fifo_request.top()._operation))
656	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
657	}
658	else
659	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
660
661	fifo_request.pop();
662
663	nb_request_memory_in ++;
664	}
665
666	LABEL("MEMORY_OUT : "+toString(out_MEMORY_OUT_VAL->read())+" - "+toString(in_MEMORY_OUT_ACK ->read()));
667	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
668	{
669	LABEL(" * Accepted MEMORY_OUT : " + toString(static_cast<uint32_t>(out_MEMORY_OUT_PACKET_ID->read())));
670
671	if (is_operation_memory_store(tab_request[out_MEMORY_OUT_PACKET_ID->read()]._operation))
672	store_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._store_queue_ptr_write] = false;
673	else
674	load_queue_use [tab_request[out_MEMORY_OUT_PACKET_ID->read()]._load_queue_ptr_write] = false;
675
676	nb_request_memory_out ++;
677	}
678
679	LABEL("DCACHE_REQ : "+toString(out_DCACHE_REQ_VAL->read())+" - "+toString(in_DCACHE_REQ_ACK ->read()));
680	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
681	{
682	LABEL(" * Accepted DCACHE_REQ : " + toString(static_cast<uint32_t>(out_DCACHE_REQ_PACKET_ID->read())));
683
684	// test type : send or not a respons !
685	}
686
687	}
688	}
689
690	/********************************************************
691	* Simulation - End
692	********************************************************/
693
694	TEST_OK ("End of Simulation");
695	delete _time;
696	cout << "<" << name << "> ............ Stop Simulation" << endl;
697
698	delete in_CLOCK;
699	delete in_NRESET;
700
701	delete in_MEMORY_IN_VAL ;
702	delete out_MEMORY_IN_ACK ;
703	delete in_MEMORY_IN_CONTEXT_ID ;
704	delete in_MEMORY_IN_PACKET_ID ;
705	delete in_MEMORY_IN_OPERATION ;
706	delete in_MEMORY_IN_TYPE ;
707	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
708	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
709	//delete in_MEMORY_IN_HAS_IMMEDIAT ;
710	delete in_MEMORY_IN_IMMEDIAT ;
711	delete in_MEMORY_IN_DATA_RA ;
712	delete in_MEMORY_IN_DATA_RB ;
713	//delete in_MEMORY_IN_DATA_RC ;
714	delete in_MEMORY_IN_WRITE_RD ;
715	delete in_MEMORY_IN_NUM_REG_RD ;
716	//delete in_MEMORY_IN_WRITE_RE ;
717	//delete in_MEMORY_IN_NUM_REG_RE ;
718
719	delete out_MEMORY_OUT_VAL ;
720	delete in_MEMORY_OUT_ACK ;
721	delete out_MEMORY_OUT_CONTEXT_ID;
722	delete out_MEMORY_OUT_PACKET_ID ;
723	delete out_MEMORY_OUT_OPERATION ;
724	delete out_MEMORY_OUT_TYPE ;
725	delete out_MEMORY_OUT_WRITE_RD ;
726	delete out_MEMORY_OUT_NUM_REG_RD;
727	delete out_MEMORY_OUT_DATA_RD ;
728	//delete out_MEMORY_OUT_WRITE_RE ;
729	//delete out_MEMORY_OUT_NUM_REG_RE;
730	//delete out_MEMORY_OUT_DATA_RE ;
731	delete out_MEMORY_OUT_EXCEPTION ;
732
733	delete out_DCACHE_REQ_VAL ;
734	delete in_DCACHE_REQ_ACK ;
735	delete out_DCACHE_REQ_CONTEXT_ID;
736	delete out_DCACHE_REQ_PACKET_ID ;
737	delete out_DCACHE_REQ_ADDRESS ;
738	delete out_DCACHE_REQ_TYPE ;
739	delete out_DCACHE_REQ_UNCACHED ;
740	delete out_DCACHE_REQ_WDATA ;
741
742	delete in_DCACHE_RSP_VAL ;
743	delete out_DCACHE_RSP_ACK ;
744	delete in_DCACHE_RSP_CONTEXT_ID;
745	delete in_DCACHE_RSP_PACKET_ID ;
746	delete in_DCACHE_RSP_RDATA ;
747	delete in_DCACHE_RSP_ERROR ;
748
749	delete [] out_BYPASS_MEMORY_VAL ;
750	delete [] out_BYPASS_MEMORY_CONTEXT_ID;
751	delete [] out_BYPASS_MEMORY_NUM_REG ;
752	delete [] out_BYPASS_MEMORY_DATA ;
753
754	#endif
755
756	delete _Load_store_unit;
757	#ifdef STATISTICS
758	delete _parameters_statistics;
759	#endif
760	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test.cpp @ 62

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