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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/src/test2.cpp @ 82

Last change on this file since 82 was 82, checked in by rosiere, 16 years ago
support locale (now must "just" translate) update all component with new test format update all component with usage New component : decod queue and prediction_unit
Property svn:keywords set to `Id`
File size: 40.3 KB

Line
1	/*
2	* $Id: test2.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include <queue>
10	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/SelfTest/include/test.h"
11
12	//===================================================================={test}
13	void test2 (void)
14	{
15	std::string name = "Test_Load_store_queue_manual";
16
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19
20	morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters * _param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Parameters
21	(
22	4, //_size_store_queue
23	4, //_size_load_queue
24	2, //_size_speculative_access_queue
25	2, //_nb_port_check
26	SPECULATIVE_LOAD_COMMIT, //_speculative_load
27	0, //_nb_bypass_memory
28	1, //_nb_context
29	1, //_nb_front_end
30	2, //_nb_ooo_engine
31	128,//_nb_packet
32	32, //_size_general_data
33	2 , //_size_special_data
34	64, //_nb_general_register
35	16 //_nb_special_register
36	);
37
38	#ifdef STATISTICS
39	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
40	#endif
41
42	Load_store_unit * _Load_store_unit = new Load_store_unit (name.c_str(),
43	#ifdef STATISTICS
44	_parameters_statistics,
45	#endif
46	_param,
47	USE_ALL);
48
49	#ifdef SYSTEMC
50	/*********************************************************************
51	* Déclarations des signaux
52	*********************************************************************/
53	string rename = "";
54
55	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
56	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
57
58	sc_signal<Tcontrol_t > * in_MEMORY_IN_VAL = new sc_signal<Tcontrol_t > (rename.c_str());
59	sc_signal<Tcontrol_t > * out_MEMORY_IN_ACK = new sc_signal<Tcontrol_t > (rename.c_str());
60	sc_signal<Tcontext_t > * in_MEMORY_IN_CONTEXT_ID = new sc_signal<Tcontext_t > (rename.c_str());
61	sc_signal<Tcontext_t > * in_MEMORY_IN_FRONT_END_ID = new sc_signal<Tcontext_t > (rename.c_str());
62	sc_signal<Tcontext_t > * in_MEMORY_IN_OOO_ENGINE_ID = new sc_signal<Tcontext_t > (rename.c_str());
63	sc_signal<Tpacket_t > * in_MEMORY_IN_PACKET_ID = new sc_signal<Tpacket_t > (rename.c_str());
64	sc_signal<Toperation_t > * in_MEMORY_IN_OPERATION = new sc_signal<Toperation_t > (rename.c_str());
65	sc_signal<Ttype_t > * in_MEMORY_IN_TYPE = new sc_signal<Ttype_t > (rename.c_str());
66	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
67	sc_signal<Tlsq_ptr_t > * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t > (rename.c_str());
68	sc_signal<Tcontrol_t > * in_MEMORY_IN_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > (rename.c_str());
69	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_IMMEDIAT = new sc_signal<Tgeneral_data_t > (rename.c_str());
70	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RA = new sc_signal<Tgeneral_data_t > (rename.c_str());
71	sc_signal<Tgeneral_data_t > * in_MEMORY_IN_DATA_RB = new sc_signal<Tgeneral_data_t > (rename.c_str());
72	sc_signal<Tspecial_data_t > * in_MEMORY_IN_DATA_RC = new sc_signal<Tspecial_data_t > (rename.c_str());
73	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RD = new sc_signal<Tcontrol_t > (rename.c_str());
74	sc_signal<Tgeneral_address_t> * in_MEMORY_IN_NUM_REG_RD = new sc_signal<Tgeneral_address_t> (rename.c_str());
75	sc_signal<Tcontrol_t > * in_MEMORY_IN_WRITE_RE = new sc_signal<Tcontrol_t > (rename.c_str());
76	sc_signal<Tspecial_address_t> * in_MEMORY_IN_NUM_REG_RE = new sc_signal<Tspecial_address_t> (rename.c_str());
77
78	sc_signal<Tcontrol_t > * out_MEMORY_OUT_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
79	sc_signal<Tcontrol_t > * in_MEMORY_OUT_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
80	sc_signal<Tcontext_t > * out_MEMORY_OUT_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
81	sc_signal<Tcontext_t > * out_MEMORY_OUT_FRONT_END_ID = new sc_signal<Tcontext_t >(rename.c_str());
82	sc_signal<Tcontext_t > * out_MEMORY_OUT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >(rename.c_str());
83	sc_signal<Tpacket_t > * out_MEMORY_OUT_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
84	// sc_signal<Toperation_t > * out_MEMORY_OUT_OPERATION = new sc_signal<Toperation_t >(rename.c_str());
85	sc_signal<Ttype_t > * out_MEMORY_OUT_TYPE = new sc_signal<Ttype_t >(rename.c_str());
86	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RD = new sc_signal<Tcontrol_t >(rename.c_str());
87	sc_signal<Tgeneral_address_t> * out_MEMORY_OUT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>(rename.c_str());
88	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_DATA_RD = new sc_signal<Tgeneral_data_t >(rename.c_str());
89	sc_signal<Tcontrol_t > * out_MEMORY_OUT_WRITE_RE = new sc_signal<Tcontrol_t >(rename.c_str());
90	sc_signal<Tspecial_address_t> * out_MEMORY_OUT_NUM_REG_RE = new sc_signal<Tspecial_address_t>(rename.c_str());
91	sc_signal<Tspecial_data_t > * out_MEMORY_OUT_DATA_RE = new sc_signal<Tspecial_data_t >(rename.c_str());
92	sc_signal<Texception_t > * out_MEMORY_OUT_EXCEPTION = new sc_signal<Texception_t >(rename.c_str());
93	sc_signal<Tcontrol_t > * out_MEMORY_OUT_NO_SEQUENCE = new sc_signal<Tcontrol_t >(rename.c_str());
94	sc_signal<Tgeneral_data_t > * out_MEMORY_OUT_ADDRESS = new sc_signal<Tgeneral_data_t >(rename.c_str());
95
96	sc_signal<Tcontrol_t > * out_DCACHE_REQ_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
97	sc_signal<Tcontrol_t > * in_DCACHE_REQ_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
98	sc_signal<Tcontext_t > * out_DCACHE_REQ_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
99	sc_signal<Tpacket_t > * out_DCACHE_REQ_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
100	sc_signal<Tdcache_address_t > * out_DCACHE_REQ_ADDRESS = new sc_signal<Tdcache_address_t >(rename.c_str());
101	sc_signal<Tdcache_type_t > * out_DCACHE_REQ_TYPE = new sc_signal<Tdcache_type_t >(rename.c_str());
102	sc_signal<Tdcache_data_t > * out_DCACHE_REQ_WDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
103
104	sc_signal<Tcontrol_t > * in_DCACHE_RSP_VAL = new sc_signal<Tcontrol_t >(rename.c_str());
105	sc_signal<Tcontrol_t > * out_DCACHE_RSP_ACK = new sc_signal<Tcontrol_t >(rename.c_str());
106	sc_signal<Tcontext_t > * in_DCACHE_RSP_CONTEXT_ID = new sc_signal<Tcontext_t >(rename.c_str());
107	sc_signal<Tpacket_t > * in_DCACHE_RSP_PACKET_ID = new sc_signal<Tpacket_t >(rename.c_str());
108	sc_signal<Tdcache_data_t > * in_DCACHE_RSP_RDATA = new sc_signal<Tdcache_data_t >(rename.c_str());
109	sc_signal<Tdcache_error_t > * in_DCACHE_RSP_ERROR = new sc_signal<Tdcache_error_t >(rename.c_str());
110
111	sc_signal<Tcontrol_t > ** out_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory];
112	sc_signal<Tcontext_t > ** out_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory];
113	sc_signal<Tgeneral_address_t> ** out_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory];
114	sc_signal<Tgeneral_data_t > ** out_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory];
115
116	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
117	{
118	out_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t >(rename.c_str());
119	out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t >(rename.c_str());
120	out_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t>(rename.c_str());
121	out_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t >(rename.c_str());
122	}
123
124	/********************************************************
125	* Instanciation
126	********************************************************/
127
128	cout << "<" << name << "> Instanciation of _Load_store_unit" << endl;
129
130	((_Load_store_unit->in_CLOCK)) ((in_CLOCK));
131	((_Load_store_unit->in_NRESET)) ((in_NRESET));
132
133	((_Load_store_unit-> in_MEMORY_IN_VAL ))(( in_MEMORY_IN_VAL ));
134	((_Load_store_unit->out_MEMORY_IN_ACK ))((out_MEMORY_IN_ACK ));
135	if (_param->_have_port_context_id)
136	((_Load_store_unit-> in_MEMORY_IN_CONTEXT_ID ))(( in_MEMORY_IN_CONTEXT_ID ));
137	if (_param->_have_port_front_end_id)
138	((_Load_store_unit-> in_MEMORY_IN_FRONT_END_ID ))(( in_MEMORY_IN_FRONT_END_ID ));
139	if (_param->_have_port_ooo_engine_id)
140	((_Load_store_unit-> in_MEMORY_IN_OOO_ENGINE_ID ))(( in_MEMORY_IN_OOO_ENGINE_ID ));
141	if (_param->_have_port_packet_id)
142	((_Load_store_unit-> in_MEMORY_IN_PACKET_ID ))(( in_MEMORY_IN_PACKET_ID ));
143	((_Load_store_unit-> in_MEMORY_IN_OPERATION ))(( in_MEMORY_IN_OPERATION ));
144	((_Load_store_unit-> in_MEMORY_IN_TYPE ))(( in_MEMORY_IN_TYPE ));
145	((_Load_store_unit-> in_MEMORY_IN_STORE_QUEUE_PTR_WRITE))(( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE));
146	if (_param->_have_port_load_queue_ptr)
147	((_Load_store_unit-> in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ))(( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ));
148	((_Load_store_unit-> in_MEMORY_IN_HAS_IMMEDIAT ))(( in_MEMORY_IN_HAS_IMMEDIAT ));
149	((_Load_store_unit-> in_MEMORY_IN_IMMEDIAT ))(( in_MEMORY_IN_IMMEDIAT ));
150	((_Load_store_unit-> in_MEMORY_IN_DATA_RA ))(( in_MEMORY_IN_DATA_RA ));
151	((_Load_store_unit-> in_MEMORY_IN_DATA_RB ))(( in_MEMORY_IN_DATA_RB ));
152	((_Load_store_unit-> in_MEMORY_IN_DATA_RC ))(( in_MEMORY_IN_DATA_RC ));
153	((_Load_store_unit-> in_MEMORY_IN_WRITE_RD ))(( in_MEMORY_IN_WRITE_RD ));
154	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RD ))(( in_MEMORY_IN_NUM_REG_RD ));
155	((_Load_store_unit-> in_MEMORY_IN_WRITE_RE ))(( in_MEMORY_IN_WRITE_RE ));
156	((_Load_store_unit-> in_MEMORY_IN_NUM_REG_RE ))(( in_MEMORY_IN_NUM_REG_RE ));
157
158	((_Load_store_unit->out_MEMORY_OUT_VAL ))((out_MEMORY_OUT_VAL ));
159	((_Load_store_unit-> in_MEMORY_OUT_ACK ))(( in_MEMORY_OUT_ACK ));
160	if (_param->_have_port_context_id)
161	((_Load_store_unit->out_MEMORY_OUT_CONTEXT_ID ))((out_MEMORY_OUT_CONTEXT_ID ));
162	if (_param->_have_port_front_end_id)
163	((_Load_store_unit->out_MEMORY_OUT_FRONT_END_ID ))((out_MEMORY_OUT_FRONT_END_ID ));
164	if (_param->_have_port_ooo_engine_id)
165	((_Load_store_unit->out_MEMORY_OUT_OOO_ENGINE_ID ))((out_MEMORY_OUT_OOO_ENGINE_ID ));
166	if (_param->_have_port_packet_id)
167	((_Load_store_unit->out_MEMORY_OUT_PACKET_ID ))((out_MEMORY_OUT_PACKET_ID ));
168	// ((_Load_store_unit->out_MEMORY_OUT_OPERATION ))((out_MEMORY_OUT_OPERATION ));
169	((_Load_store_unit->out_MEMORY_OUT_TYPE ))((out_MEMORY_OUT_TYPE ));
170	((_Load_store_unit->out_MEMORY_OUT_WRITE_RD ))((out_MEMORY_OUT_WRITE_RD ));
171	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RD ))((out_MEMORY_OUT_NUM_REG_RD ));
172	((_Load_store_unit->out_MEMORY_OUT_DATA_RD ))((out_MEMORY_OUT_DATA_RD ));
173	((_Load_store_unit->out_MEMORY_OUT_WRITE_RE ))((out_MEMORY_OUT_WRITE_RE ));
174	((_Load_store_unit->out_MEMORY_OUT_NUM_REG_RE ))((out_MEMORY_OUT_NUM_REG_RE ));
175	((_Load_store_unit->out_MEMORY_OUT_DATA_RE ))((out_MEMORY_OUT_DATA_RE ));
176	((_Load_store_unit->out_MEMORY_OUT_EXCEPTION ))((out_MEMORY_OUT_EXCEPTION ));
177	((_Load_store_unit->out_MEMORY_OUT_NO_SEQUENCE ))((out_MEMORY_OUT_NO_SEQUENCE ));
178	((_Load_store_unit->out_MEMORY_OUT_ADDRESS ))((out_MEMORY_OUT_ADDRESS ));
179
180	((_Load_store_unit->out_DCACHE_REQ_VAL ))((out_DCACHE_REQ_VAL ));
181	((_Load_store_unit-> in_DCACHE_REQ_ACK ))(( in_DCACHE_REQ_ACK ));
182	if (_param->_have_port_dcache_context_id)
183	((_Load_store_unit->out_DCACHE_REQ_CONTEXT_ID))((out_DCACHE_REQ_CONTEXT_ID));
184	((_Load_store_unit->out_DCACHE_REQ_PACKET_ID ))((out_DCACHE_REQ_PACKET_ID ));
185	((_Load_store_unit->out_DCACHE_REQ_ADDRESS ))((out_DCACHE_REQ_ADDRESS ));
186	((_Load_store_unit->out_DCACHE_REQ_TYPE ))((out_DCACHE_REQ_TYPE ));
187	((_Load_store_unit->out_DCACHE_REQ_WDATA ))((out_DCACHE_REQ_WDATA ));
188
189	((_Load_store_unit-> in_DCACHE_RSP_VAL ))(( in_DCACHE_RSP_VAL ));
190	((_Load_store_unit->out_DCACHE_RSP_ACK ))((out_DCACHE_RSP_ACK ));
191	if (_param->_have_port_dcache_context_id)
192	((_Load_store_unit-> in_DCACHE_RSP_CONTEXT_ID))(( in_DCACHE_RSP_CONTEXT_ID));
193	((_Load_store_unit-> in_DCACHE_RSP_PACKET_ID ))(( in_DCACHE_RSP_PACKET_ID ));
194	((_Load_store_unit-> in_DCACHE_RSP_RDATA ))(( in_DCACHE_RSP_RDATA ));
195	((_Load_store_unit-> in_DCACHE_RSP_ERROR ))(( in_DCACHE_RSP_ERROR ));
196
197	{
198	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
199	{
200	((_Load_store_unit->out_BYPASS_MEMORY_VAL [i]))((out_BYPASS_MEMORY_VAL [i]));
201	if (_param->_have_port_ooo_engine_id)
202	((_Load_store_unit->out_BYPASS_MEMORY_OOO_ENGINE_ID [i]))((out_BYPASS_MEMORY_OOO_ENGINE_ID [i]));
203	((_Load_store_unit->out_BYPASS_MEMORY_NUM_REG [i]))((out_BYPASS_MEMORY_NUM_REG [i]));
204	((_Load_store_unit->out_BYPASS_MEMORY_DATA [i]))((out_BYPASS_MEMORY_DATA [i]));
205	}
206	}
207	cout << "<" << name << "> Start Simulation ............" << endl;
208	Time * _time = new Time();
209
210	/********************************************************
211	* Simulation - Begin
212	********************************************************/
213
214	// Initialisation
215
216	const uint32_t seed = 0;
217	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
218
219	srand(seed);
220
221	const int32_t percent_transaction_memory_out = 100;
222	const int32_t percent_transaction_dcache = 100;
223	const uint32_t miss_rate = 0;
224	const uint32_t miss_penality = 0;
225
226	uint32_t nb_request_memory_out=0;
227
228	MemoryRequest_t tab_request [_param->_nb_packet];
229	priority_queue<MemoryRequest_t> fifo_request;
230
231	const uint32_t size_memory = 0x100;
232	// emulation of memory
233	Memory_t * _memory = new Memory_t (1<<_param->_size_dcache_context_id, size_memory, _param->_size_general_data);
234	Cache_t * _cache = new Cache_t (miss_rate, miss_penality);
235
236	SC_START(0);
237
238	LABEL("Initialisation");
239
240	in_MEMORY_IN_VAL ->write(0);
241	in_MEMORY_OUT_ACK->write(0);
242	in_DCACHE_REQ_ACK->write(0);
243	in_DCACHE_RSP_VAL->write(0);
244
245	in_NRESET ->write(0);
246	SC_START(5);
247	in_NRESET ->write(5);
248
249	LABEL("Loop of Test");
250
251	try
252	{
253	LABEL("Structure's initialisation");
254
255	bool store_queue_use [_param->_size_store_queue];
256	uint32_t nb_store_slot_use = 0;
257	bool load_queue_use [_param->_size_load_queue ];
258
259	for (uint32_t i=0; i<_param->_size_store_queue; i++)
260	store_queue_use [i] = false;
261	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
262	load_queue_use [i] = false;
263
264
265	//--------------------------------------------------------------------------------------------------------------
266	// c c f o p o t s l i d d w n w
267	// y o r o a p y t o m a a r u r
268	// c n o o c e p o a m t t i m i
269	// l t n _ k r e r d e a a t _ t
270	// e e t e e a e _ d _ _ e r e
271	// x _ n t t _ p i r r _ _ _
272	// t e g _ i p t a a b r g s
273	// _ n i i o t r t d _ p
274	// i d n d n r _ r e
275	// d _ e _ w d c
276	// i _ w r _
277	// d i r i k
278	// d i t o
279	// t e
280	// e
281	//
282	tab_request[ 0].modif( 5,0,0,0, 0,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x10 ,0xdead1234,0,0,0);
283
284	tab_request[ 1].modif(10,0,0,0, 0,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
285
286	// READ 32b
287	tab_request[ 2].modif(12,0,0,0, 2,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,1,0,0xdead1234);
288	tab_request[ 3].modif(13,0,0,0, 3,OPERATION_MEMORY_LOAD_32_S ,TYPE_MEMORY,1,1,0x10 ,0x0 ,0x0 ,1,2,0,0xdead1234);
289
290	// READ 16b
291	tab_request[ 4].modif(14,0,0,0, 4,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,2,0x10 ,0x0 ,0x0 ,1,3,0,0x00001234);
292	tab_request[ 5].modif(15,0,0,0, 5,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,1,3,0x12 ,0x0 ,0x0 ,1,4,0,0x0000dead);
293	tab_request[ 6].modif(16,0,0,0, 6,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,5,0,0x00001234);
294	tab_request[ 7].modif(17,0,0,0, 7,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,1,1,0x12 ,0x0 ,0x0 ,1,6,0,0xffffdead);
295
296	// READ 8b
297	tab_request[ 8].modif(18,0,0,0, 8,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,7,0,0x00000034);
298	tab_request[ 9].modif(19,0,0,0, 9,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,8,0,0x00000012);
299	tab_request[10].modif(20,0,0,0,10,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,9,0,0x000000ad);
300	tab_request[11].modif(21,0,0,0,11,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,1,0,0x000000de);
301	tab_request[12].modif(22,0,0,0,12,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,0,0x10 ,0x0 ,0x0 ,1,2,0,0x00000034);
302	tab_request[13].modif(23,0,0,0,13,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,1,0x11 ,0x0 ,0x0 ,1,3,0,0x00000012);
303	tab_request[14].modif(24,0,0,0,14,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,2,0x12 ,0x0 ,0x0 ,1,4,0,0xffffffad);
304	tab_request[15].modif(25,0,0,0,15,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,1,3,0x13 ,0x0 ,0x0 ,1,5,0,0xffffffde);
305
306	// STORE 16b
307	tab_request[16].modif(30,0,0,0,16,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x20 ,0x0 ,0xffffabcd,0,0,0);
308	tab_request[17].modif(31,0,0,0,17,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x22 ,0x0 ,0xffffdcba,0,0,0);
309	tab_request[18].modif(35,0,0,0,18,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
310	tab_request[19].modif(36,0,0,0,19,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
311	tab_request[20].modif(40,0,0,0,20,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x20 ,0x0 ,0x0 ,1,0,0,0xdcbaabcd);
312
313	// STORE 8b and head / valid out order
314	tab_request[21].modif(50,0,0,0,21,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,3,0,0x1 ,0x4 ,0xffffff56,0,0,0);
315	tab_request[22].modif(55,0,0,0,22,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x1 ,0x0 ,0x0 ,0,0,0);
316	tab_request[23].modif(48,0,0,0,23,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,0,0,0x0 ,0x4 ,0xffffff78,0,0,0);
317	tab_request[24].modif(43,0,0,0,24,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
318	tab_request[25].modif(47,0,0,0,25,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,1,0,0x3 ,0x4 ,0xffffff12,0,0,0);
319	tab_request[26].modif(49,0,0,0,26,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
320	tab_request[27].modif(57,0,0,0,27,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x2 ,0x4 ,0xffffff34,0,0,0);
321	tab_request[28].modif(44,0,0,0,28,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
322	tab_request[29].modif(70,0,0,0,29,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x2 ,0x2 ,0x0 ,1,0,0,0x12345678);
323
324	// CHECK - with a store not present, store format is >=
325	tab_request[30].modif(180,0,0,0,30,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x30 ,0x21071981,0,0,0);
326	tab_request[31].modif(179,0,0,0,31,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
327	tab_request[32].modif(173,0,0,0,32,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x30 ,0x0 ,1,0,0,0x21071981);
328	tab_request[33].modif(174,0,0,0,33,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,3,0x0 ,0x30 ,0x0 ,1,0,0,0x00001981);
329	tab_request[34].modif(175,0,0,0,34,OPERATION_MEMORY_LOAD_16_Z ,TYPE_MEMORY,0,0,0x0 ,0x32 ,0x0 ,1,0,0,0x00002107);
330	tab_request[35].modif(176,0,0,0,35,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,0,1,0x0 ,0x31 ,0x0 ,1,0,0,0x00000019);
331
332	// CHECK - with a store not present, multiple store and format is different
333	tab_request[36].modif(200,0,0,0,36,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x40 ,0xffffffff,0,0,0);
334	tab_request[37].modif(200,0,0,0,37,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
335	tab_request[38].modif(220,0,0,0,38,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,1,0,0x0 ,0x42 ,0xbaba ,0,0,0);
336	tab_request[39].modif(245,0,0,0,39,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
337	tab_request[40].modif(224,0,0,0,40,OPERATION_MEMORY_STORE_8 ,TYPE_MEMORY,2,0,0x0 ,0x42 ,0xbe ,0,0,0);
338	tab_request[41].modif(240,0,0,0,41,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
339	tab_request[42].modif(228,0,0,0,42,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0xf00d ,0,0,0);
340	tab_request[43].modif(235,0,0,0,43,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
341	tab_request[44].modif(210,0,0,0,44,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x40 ,0x0 ,1,0,0,0xbabef00d);
342	tab_request[45].modif(211,0,0,0,45,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,2,3,0x0 ,0x40 ,0x0 ,1,0,0,0xbabaffff);
343	tab_request[46].modif(212,0,0,0,46,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,0,0x0 ,0x40 ,0x0 ,1,0,0,0xbabeffff);
344	tab_request[47].modif(213,0,0,0,47,OPERATION_MEMORY_LOAD_8_S ,TYPE_MEMORY,3,1,0x0 ,0x42 ,0x0 ,1,0,0,0xffffffbe);
345
346
347	// CHECK - with different ooo_engine_id
348	tab_request[48].modif(300,0,0,0,48,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,0x0 ,0xdad1900d,0,0,0);
349	tab_request[49].modif(300,0,0,0,49,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
350	tab_request[50].modif(300,0,0,1,50,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x55508570,0,0,0);
351	tab_request[51].modif(300,0,0,1,51,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,0,0,0);
352
353
354	tab_request[52].modif(320,0,0,0,52,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,2,0x0 ,0x2 ,0x0 ,1,0,0,0xffffdad1);
355	tab_request[53].modif(321,0,0,1,53,OPERATION_MEMORY_LOAD_16_S ,TYPE_MEMORY,2,3,0x0 ,0x0 ,0x0 ,1,0,0,0xffff8570);
356
357
358	// with a little exception
359	tab_request[54].modif(330,0,0,1,54,OPERATION_MEMORY_STORE_16 ,TYPE_MEMORY,2,0,0x0 ,0x0 ,0xffff6996,0,0,1);
360	tab_request[55].modif(340,0,0,1,55,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,2,0,0x0 ,0x0 ,0x0 ,0,0,0);
361	tab_request[56].modif(322,0,0,1,56,OPERATION_MEMORY_LOAD_8_Z ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,1,0,0,0x00000069); // they are a bypass (because, the cpu go in exception handler ... load is not use)
362	tab_request[57].modif(350,0,0,1,57,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,3,1,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // the memory have not change
363
364
365	// multiple event
366	// * store : miss_spec and aligment, priority : miss_spec > aligment
367	// * load : miss_spec and aligment, priority : miss_spec > aligment
368	tab_request[58].modif(410,0,0,0,58,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,3,0,0x0 ,0x1 ,0x0 ,0,0,1);
369	tab_request[59].modif(415,0,0,0,59,OPERATION_MEMORY_STORE_HEAD_KO,TYPE_MEMORY,3,0,0x0 ,0x0 ,0x0 ,0,0,0);
370
371	tab_request[60].modif(430,0,0,0,60,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,2,0x0 ,0x0 ,0x0 ,1,0,0,0xdad1900d);
372	tab_request[61].modif(400,0,0,0,61,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,3,0x0 ,0x3 ,0x0 ,1,0,0); // miss_spec and alignment
373	tab_request[62].modif(450,0,0,0,62,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,1,0,0); // bus error and alignement
374	tab_request[63].modif(460,0,0,0,63,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,0,1,0x0 ,size_memory+1,0x0 ,1,0,0); // bus error and alignement
375
376
377
378	tab_request[64].modif(500,0,0,0,64,OPERATION_MEMORY_STORE_32 ,TYPE_MEMORY,0,0,0x0 ,size_memory ,0x0 ,0,0,0); // bus error
379	tab_request[65].modif(505,0,0,0,65,OPERATION_MEMORY_STORE_HEAD_OK,TYPE_MEMORY,0,0,0x0 ,0x0 ,0x0 ,0,0,0);
380	tab_request[66].modif(550,0,0,0,65,OPERATION_MEMORY_LOAD_32_Z ,TYPE_MEMORY,1,0,0x0 ,0x0 ,0x0 ,1,0,0,0x55508570); // just to wait the dcache_rsp
381
382	const uint32_t nb_request = 64;//_param->_nb_packet;
383
384	for (uint32_t i=0; i<nb_request; i++)
385	{
386	std::cout << tab_request [i] << std::endl;
387	fifo_request.push(tab_request [i]);
388	}
389	LABEL("Simulation ...");
390
391	while (nb_request_memory_out < nb_request)
392	{
393	cout << "*********************************************" << endl;
394	cout << "Dump STORE_QUEUE_USE : " << endl;
395	cout << " use " << nb_store_slot_use << endl;
396	for (uint32_t i=0; i<_param->_size_store_queue; i++)
397	cout << " [" << i << "] " << store_queue_use [i] << endl;
398	cout << "Dump LOAD_QUEUE_USE : " << endl;
399	for (uint32_t i=0; i<_param->_size_load_queue ; i++)
400	cout << " [" << i << "] " << load_queue_use [i] << endl;
401	cout << "*********************************************" << endl;
402
403
404	// *** MEMORY_IN ***
405
406	// memory_in_val depends of three factors :
407	// 1) request's fifo is not empty ?
408	// 2) the slot destination is free ?
409	// 3) The head of request's fifo can be issue : the number of cycle is more than current cycle
410
411	bool can_execute = false;
412
413	if (not fifo_request.empty())
414	{
415	can_execute = sc_simulation_time() >= fifo_request.top()._cycle;
416	if (is_operation_memory_store(fifo_request.top()._operation))
417	can_execute &= (not store_queue_use [fifo_request.top()._store_queue_ptr_write] and (nb_store_slot_use < _param->_size_store_queue-1)) or is_operation_memory_store_head(fifo_request.top()._operation);
418	else
419	can_execute &= not load_queue_use [fifo_request.top()._load_queue_ptr_write];
420	}
421	in_MEMORY_IN_VAL ->write(can_execute);
422
423	if (not fifo_request.empty())
424	{
425	if (_param->_have_port_context_id)
426	in_MEMORY_IN_CONTEXT_ID ->write (fifo_request.top()._context_id );
427	if (_param->_have_port_front_end_id)
428	in_MEMORY_IN_FRONT_END_ID ->write (fifo_request.top()._front_end_id );
429	if (_param->_have_port_ooo_engine_id)
430	in_MEMORY_IN_OOO_ENGINE_ID ->write (fifo_request.top()._ooo_engine_id );
431	if (_param->_have_port_packet_id)
432	in_MEMORY_IN_PACKET_ID ->write (fifo_request.top()._packet_id );
433	in_MEMORY_IN_OPERATION ->write (fifo_request.top()._operation );
434	in_MEMORY_IN_TYPE ->write (fifo_request.top()._type );
435	in_MEMORY_IN_STORE_QUEUE_PTR_WRITE->write (fifo_request.top()._store_queue_ptr_write);
436	if (_param->_have_port_load_queue_ptr)
437	in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ->write (fifo_request.top()._load_queue_ptr_write );
438	in_MEMORY_IN_IMMEDIAT ->write (fifo_request.top()._immediat );
439	in_MEMORY_IN_DATA_RA ->write (fifo_request.top()._data_ra );
440	in_MEMORY_IN_DATA_RB ->write (fifo_request.top()._data_rb );
441	// in_MEMORY_IN_WRITE_RD ->write (fifo_request.top()._write_rd );
442	in_MEMORY_IN_NUM_REG_RD ->write (fifo_request.top()._num_reg_rd );
443	}
444	in_MEMORY_OUT_ACK->write((rand()%100)<percent_transaction_memory_out);
445
446	// *** DCACHE_REQ ***
447	in_DCACHE_REQ_ACK->write((rand()%100)<percent_transaction_dcache);
448
449	// *** DCACHE_RSP ***
450	bool have_rsp = _cache->have_rsp ();
451	in_DCACHE_RSP_VAL->write(have_rsp);
452
453	if (have_rsp)
454	{
455	in_DCACHE_RSP_CONTEXT_ID->write(_cache->front()._context_id);
456	in_DCACHE_RSP_PACKET_ID ->write(_cache->front()._packet_id );
457	in_DCACHE_RSP_RDATA ->write(_cache->front()._rdata );
458	in_DCACHE_RSP_ERROR ->write(_cache->front()._error );
459	}
460
461	SC_START(0);
462
463	LABEL("MEMORY_IN : %d - %d",in_MEMORY_IN_VAL ->read(),out_MEMORY_IN_ACK ->read());
464	if ( in_MEMORY_IN_VAL ->read() and out_MEMORY_IN_ACK ->read())
465	{
466	Tpacket_t packet_id = in_MEMORY_IN_PACKET_ID->read();
467
468	LABEL(" * Accepted MEMORY_IN : %d",packet_id);
469	cout << fifo_request.top();
470
471	if (is_operation_memory_store(fifo_request.top()._operation))
472	{
473	if (not is_operation_memory_store_head(fifo_request.top()._operation))
474	{
475	store_queue_use [fifo_request.top()._store_queue_ptr_write] = true;
476	nb_store_slot_use ++;
477	}
478	}
479	else
480	load_queue_use [fifo_request.top()._load_queue_ptr_write] = true;
481
482	fifo_request.pop();
483	}
484
485	LABEL("MEMORY_OUT : %d - %d",out_MEMORY_OUT_VAL->read(),in_MEMORY_OUT_ACK ->read());
486	if (out_MEMORY_OUT_VAL->read() and in_MEMORY_OUT_ACK->read())
487	{
488	Tpacket_t packet_id = out_MEMORY_OUT_PACKET_ID->read();
489
490	LABEL(" * Accepted MEMORY_OUT : %d",packet_id);
491
492	if (is_operation_memory_store(tab_request[packet_id]._operation))
493	{
494	store_queue_use [tab_request[packet_id]._store_queue_ptr_write] = false;
495	nb_store_slot_use --;
496	nb_request_memory_out +=2;
497
498	}
499	else
500	{
501	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
502	{
503	nb_request_memory_out ++;
504
505	load_queue_use [tab_request[packet_id]._load_queue_ptr_write] = false;
506	}
507	else
508	{
509	std::cout << "seth - have a load_speculative." << std::endl;
510	tab_request[packet_id]._write_spec_ko = (out_MEMORY_OUT_DATA_RD->read() != tab_request[packet_id]._data_wait);
511	tab_request[packet_id]._previous_load_speculative = 1;
512	}
513	}
514
515	std::cout << "kane - nb_request_memory_out : " << nb_request_memory_out << std::endl;
516
517	// a lot of test
518	TEST(Tpacket_t , out_MEMORY_OUT_PACKET_ID ->read(), tab_request[packet_id]._packet_id );
519	TEST(Tcontext_t , out_MEMORY_OUT_CONTEXT_ID ->read(), tab_request[packet_id]._context_id );
520	TEST(Tcontext_t , out_MEMORY_OUT_FRONT_END_ID ->read(), tab_request[packet_id]._front_end_id );
521	TEST(Tcontext_t , out_MEMORY_OUT_OOO_ENGINE_ID->read(), tab_request[packet_id]._ooo_engine_id);
522	// TEST(Toperation_t , out_MEMORY_OUT_OPERATION ->read(), tab_request[packet_id]._operation );
523	TEST(Ttype_t , out_MEMORY_OUT_TYPE ->read(), TYPE_MEMORY );
524
525	if (is_operation_memory_load (tab_request[packet_id]._operation))
526	{
527	TEST(Tgeneral_address_t, out_MEMORY_OUT_NUM_REG_RD ->read(), tab_request[packet_id]._num_reg_rd );
528	}
529
530	Tgeneral_data_t address = tab_request[packet_id]._data_ra + tab_request[packet_id]._immediat;
531
532	bool error_alignment = (address != (address & (~ mask_memory_access(tab_request[packet_id]._operation))));
533	bool berr = (address >= size_memory);
534	Texception_t exception = out_MEMORY_OUT_EXCEPTION->read();
535
536	if (is_operation_memory_store(tab_request[packet_id]._operation))
537	{
538	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 0);
539
540	// store.
541	// prioritary : miss_speculation > aligmnent > DBERR
542
543	bool test_result_ko = false;
544
545	if (tab_request[packet_id]._write_spec_ko)
546	{
547	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
548	}
549	else
550	if (error_alignment)
551	{
552	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
553	test_result_ko = true;
554	}
555	else
556	if (berr)
557	{
558	// TODO NOT SUPPORTED
559	// TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
560
561	//test_result_ko = true;
562	}
563	else
564	{
565	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
566	}
567	// In all case : test data
568	if (test_result_ko)
569	{
570	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
571	}
572	}
573	else
574	{
575	// load
576	// prioritary : miss_speculation > aligmnent > DBERR
577
578	bool is_load = is_operation_memory_load(tab_request[packet_id]._operation);
579
580	if (not (out_MEMORY_OUT_EXCEPTION->read() == EXCEPTION_MEMORY_LOAD_SPECULATIVE))
581	{
582	bool test_result_ko = false;
583
584	if (tab_request[packet_id]._write_spec_ko)
585	{
586	// IS A LOAD :D
587	TEST(Texception_t, exception, EXCEPTION_MEMORY_MISS_SPECULATION);
588	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), 1);
589	}
590	else
591	if (error_alignment)
592	{
593	TEST(Texception_t, exception, EXCEPTION_MEMORY_ALIGNMENT);
594	TEST(Tcontrol_t, out_MEMORY_OUT_WRITE_RD->read(), is_load);
595	test_result_ko = true;
596	}
597	else
598	if (berr)
599	{
600	TEST(Texception_t, exception, EXCEPTION_MEMORY_BUS_ERROR);
601	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load);
602	test_result_ko = true;
603	}
604	else
605	{
606	TEST(Texception_t, exception, EXCEPTION_MEMORY_NONE);
607	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD->read(), is_load and not tab_request[packet_id]._previous_load_speculative);
608	}
609	// In all case : test data
610	if (test_result_ko)
611	{
612	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), address);
613	}
614	else
615	{
616	TEST(Tgeneral_data_t , out_MEMORY_OUT_DATA_RD->read(), tab_request[packet_id]._data_wait);
617	}
618	}
619	else
620	{
621	TEST(Tcontrol_t , out_MEMORY_OUT_WRITE_RD ->read(), 1);
622	}
623	}
624	}
625
626	LABEL("DCACHE_REQ : %d - %d",out_DCACHE_REQ_VAL->read(),in_DCACHE_REQ_ACK ->read());
627	if (out_DCACHE_REQ_VAL->read() and in_DCACHE_REQ_ACK->read())
628	{
629	Tcontext_t context_id;
630	Tpacket_t packet_id ;
631	Tdcache_address_t address = out_DCACHE_REQ_ADDRESS->read();
632	Tdcache_data_t rdata;
633	Tdcache_error_t error = 0;
634	if (_param->_have_port_dcache_context_id)
635	context_id = out_DCACHE_REQ_CONTEXT_ID->read();
636	else
637	context_id = 0;
638
639	packet_id = (out_DCACHE_REQ_PACKET_ID ->read())>>1;
640
641	LABEL(" * Accepted DCACHE_REQ : %d",packet_id);
642
643	if (address >= size_memory)
644	{
645	// Bus error
646	error = DCACHE_ERROR_BUS_ERROR;
647	rdata = address; // convention : cache return the address fautive !
648	}
649	else
650	{
651	rdata = _memory->access (context_id, address, out_DCACHE_REQ_TYPE->read(), out_DCACHE_REQ_WDATA->read());
652	LABEL(" * rdata : 0x%x",rdata);
653	}
654
655	// test type : send or not a respons !
656	if ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_SYNCHRONIZATION) or
657	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_8 ) or
658	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_16) or
659	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_32) or
660	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_LOAD_64) or
661	((error != DCACHE_ERROR_NONE) and ((out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_8 ) or
662	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_16) or
663	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_32) or
664	(out_DCACHE_REQ_TYPE->read() == DCACHE_TYPE_STORE_64) )))
665	{
666	LABEL(" * have_dcache_rsp");
667
668	_cache->push (context_id,
669	out_DCACHE_REQ_PACKET_ID ->read(),
670	rdata,
671	error);
672	}
673	}
674
675	LABEL("DCACHE_RSP : %d - %d",in_DCACHE_RSP_VAL->read(),out_DCACHE_RSP_ACK ->read());
676	if (in_DCACHE_RSP_VAL->read() and out_DCACHE_RSP_ACK->read())
677	{
678	_cache->pop();
679	}
680
681	_cache->end_cycle();
682
683	SC_START(1);
684	}
685	}
686	catch (morpheo::ErrorMorpheo & error)
687	{
688	_memory->trace();
689	throw (error);
690	}
691
692	_memory->trace();
693
694
695	/********************************************************
696	* Simulation - End
697	********************************************************/
698
699	TEST_OK ("End of Simulation");
700	delete _time;
701	cout << "<" << name << "> ............ Stop Simulation" << endl;
702
703	delete in_CLOCK;
704	delete in_NRESET;
705
706	delete in_MEMORY_IN_VAL ;
707	delete out_MEMORY_IN_ACK ;
708	delete in_MEMORY_IN_CONTEXT_ID ;
709	delete in_MEMORY_IN_FRONT_END_ID ;
710	delete in_MEMORY_IN_OOO_ENGINE_ID ;
711	delete in_MEMORY_IN_PACKET_ID ;
712	delete in_MEMORY_IN_OPERATION ;
713	delete in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;
714	delete in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;
715	delete in_MEMORY_IN_HAS_IMMEDIAT;
716	delete in_MEMORY_IN_IMMEDIAT ;
717	delete in_MEMORY_IN_DATA_RA ;
718	delete in_MEMORY_IN_DATA_RB ;
719	delete in_MEMORY_IN_DATA_RC ;
720	delete in_MEMORY_IN_WRITE_RD ;
721	delete in_MEMORY_IN_NUM_REG_RD ;
722	delete in_MEMORY_IN_WRITE_RE ;
723	delete in_MEMORY_IN_NUM_REG_RE ;
724
725	delete out_MEMORY_OUT_VAL ;
726	delete in_MEMORY_OUT_ACK ;
727	delete out_MEMORY_OUT_CONTEXT_ID;
728	delete out_MEMORY_OUT_FRONT_END_ID;
729	delete out_MEMORY_OUT_OOO_ENGINE_ID;
730	delete out_MEMORY_OUT_PACKET_ID ;
731	// delete out_MEMORY_OUT_OPERATION ;
732	delete out_MEMORY_OUT_TYPE ;
733	delete out_MEMORY_OUT_WRITE_RD ;
734	delete out_MEMORY_OUT_NUM_REG_RD;
735	delete out_MEMORY_OUT_DATA_RD ;
736	delete out_MEMORY_OUT_WRITE_RE ;
737	delete out_MEMORY_OUT_NUM_REG_RE;
738	delete out_MEMORY_OUT_DATA_RE ;
739	delete out_MEMORY_OUT_EXCEPTION ;
740	delete out_MEMORY_OUT_NO_SEQUENCE;
741	delete out_MEMORY_OUT_ADDRESS ;
742
743	delete out_DCACHE_REQ_VAL ;
744	delete in_DCACHE_REQ_ACK ;
745	delete out_DCACHE_REQ_CONTEXT_ID;
746	delete out_DCACHE_REQ_PACKET_ID ;
747	delete out_DCACHE_REQ_ADDRESS ;
748	delete out_DCACHE_REQ_TYPE ;
749	delete out_DCACHE_REQ_WDATA ;
750
751	delete in_DCACHE_RSP_VAL ;
752	delete out_DCACHE_RSP_ACK ;
753	delete in_DCACHE_RSP_CONTEXT_ID;
754	delete in_DCACHE_RSP_PACKET_ID ;
755	delete in_DCACHE_RSP_RDATA ;
756	delete in_DCACHE_RSP_ERROR ;
757
758	{
759	delete [] out_BYPASS_MEMORY_VAL ;
760	delete [] out_BYPASS_MEMORY_OOO_ENGINE_ID;
761	delete [] out_BYPASS_MEMORY_NUM_REG ;
762	delete [] out_BYPASS_MEMORY_DATA ;
763	}
764	#endif
765
766	delete _Load_store_unit;
767	delete _memory;
768	delete _cache;
769	#ifdef STATISTICS
770	delete _parameters_statistics;
771	#endif
772	delete _param;
773	}

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