source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago

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[59]1#ifdef SYSTEMC
2/*
3 * $Id: Load_store_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $
4 *
[88]5 * [ Description ]
[59]6 *
7 */
8
9#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
[88]10#include "Behavioural/include/Allocation.h"
[59]11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22
23#undef  FUNCTION
24#define FUNCTION "Load_store_unit::allocation"
25  void Load_store_unit::allocation (void)
26  {
27    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");
28
[82]29    _component   = new Component (_usage);
[59]30
31    Entity * entity = _component->set_entity (_name       
32                                              ,"Load_store_unit"
33#ifdef POSITION
34                                              ,COMBINATORY
35#endif
36                                              );
37
38    _interfaces = entity->set_interfaces();
39
[88]40    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]41    {
42      Interface * interface = _interfaces->set_interface(""
43#ifdef POSITION
44                                                         ,IN
45                                                         ,SOUTH,
[88]46                                                         _("Generalist interface")
[59]47#endif
48                                                         );
49     
50      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
51      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
52    }
[88]53
54    // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]55    {
[88]56      ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory);
[59]57
[88]58      ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL                  ,VAL);
59      ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK                  ,ACK);
60      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID           ,"context_id"           ,Tcontext_t        ,_param->_size_context_id           );
61      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID         ,"front_end_id"         ,Tcontext_t        ,_param->_size_front_end_id         );
62      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID        ,"ooo_engine_id"        ,Tcontext_t        ,_param->_size_ooo_engine_id        );
63      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID            ,"packet_id"            ,Tpacket_t         ,_param->_size_rob_ptr              );
64      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION            ,"operation"            ,Toperation_t      ,_param->_size_operation            );
65      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE                 ,"type"                 ,Ttype_t           ,_param->_size_type                 );
66      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t        ,_param->_size_store_queue_ptr      );
67      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t        ,_param->_size_load_queue_ptr       );
68      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT         ,"has_immediat"         ,Tcontrol_t        ,1                                  );
69      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT             ,"immediat"             ,Tgeneral_data_t   ,_param->_size_general_data         );
70      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA              ,"data_ra"              ,Tgeneral_data_t   ,_param->_size_general_data         );
71      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB              ,"data_rb"              ,Tgeneral_data_t   ,_param->_size_general_data         );
72      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC              ,"data_rc"              ,Tspecial_data_t   ,_param->_size_special_data         );
73      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD             ,"write_rd"             ,Tcontrol_t        ,1                                  );
74      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD           ,"num_reg_rd"           ,Tgeneral_address_t,1                                  );
75      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE             ,"write_re"             ,Tcontrol_t        ,1                                  );
76      ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE           ,"num_reg_re"           ,Tspecial_address_t,1                                  );
[59]77    }
78
[88]79    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]80    {
[88]81      ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory);
[59]82
[88]83      ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL          ,VAL);
84      ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK          ,ACK);
85      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID   ,"context_id"    ,Tcontext_t        ,_param->_size_context_id       );
86      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id"  ,Tcontext_t        ,_param->_size_front_end_id     );
87      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t        ,_param->_size_ooo_engine_id    );
88      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID    ,"packet_id"     ,Tpacket_t         ,_param->_size_rob_ptr          );
89//    ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION    ,"operation"     ,Toperation_t      ,_param->_size_operation        );
90      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE         ,"type"          ,Ttype_t           ,_param->_size_type             );
91      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD     ,"write_rd"      ,Tcontrol_t        ,1                              );
92      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD   ,"num_reg_rd"    ,Tgeneral_address_t,_param->_size_general_register );
93      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD      ,"data_rd"       ,Tgeneral_data_t   ,_param->_size_general_data     );
94      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE     ,"write_re"      ,Tcontrol_t        ,1                              );
95      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE   ,"num_reg_re"    ,Tspecial_address_t,_param->_size_general_register );
96      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE      ,"data_re"       ,Tspecial_data_t   ,_param->_size_general_data     );
97      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION    ,"exception"     ,Texception_t      ,_param->_size_exception        );
98      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE  ,"no_sequence"   ,Tcontrol_t        ,1                              );
99      ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS      ,"address"       ,Tgeneral_data_t   ,_param->_size_general_data     );
[59]100    }
101
[88]102    // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]103    {
[88]104      ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port);
[59]105
[88]106      ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL        ,VAL);
107      ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK        ,ACK);
108      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t       ,_param->_size_dcache_context_id  );
109      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID  ,"packet_id" ,Tpacket_t        ,_param->_size_dcache_packet_id   );
110      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS    ,"address"   ,Tdcache_address_t,_param->_size_general_data);
111      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE       ,"type"      ,Tdcache_type_t   ,_param->_size_dcache_type );
112      ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA      ,"wdata"     ,Tdcache_data_t   ,_param->_size_general_data);
[59]113    }
[88]114
115    // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]116    {
[88]117      ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port);
[59]118
[88]119      ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL        ,VAL);
120      ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK        ,ACK);
121      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t     ,_param->_size_dcache_context_id  );
122      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID  ,"packet_id" ,Tpacket_t      ,_param->_size_dcache_packet_id   );
123      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA      ,"rdata"     ,Tdcache_data_t ,_param->_size_general_data);
124      ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR      ,"error"     ,Tdcache_error_t,_param->_size_dcache_error);
[59]125    }
[88]126    // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[59]127
[88]128    {
129      ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory);
[59]130           
[88]131      ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL           ,VAL);
132      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t        , _param->_size_ooo_engine_id   );
133      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG       ,"num_reg"      ,Tgeneral_address_t, _param->_size_general_register);
134      ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA          ,"data"         ,Tgeneral_data_t   , _param->_size_general_data    );
135    }
[59]136
[88]137    // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
138
139//     internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port];
140
141//     internal_MEMORY_IN_ACK           = new Tcontrol_t      [_param->_nb_inst_memory];
142//     internal_MEMORY_OUT_VAL          = new Tcontrol_t      [_param->_nb_inst_memory];
143//     internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory];
144//     internal_MEMORY_OUT_PTR          = new Tlsq_ptr_t      [_param->_nb_inst_memory];
145   
146//     internal_DCACHE_RSP_ACK          = new Tcontrol_t      [_param->_nb_cache_port];
147//     internal_DCACHE_REQ_VAL          = new Tcontrol_t      [_param->_nb_cache_port];
148//     internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port];
149
150    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
151
[59]152#ifdef POSITION
[88]153    if (usage_is_set(_usage,USE_POSITION))
154      _component->generate_file();
[59]155#endif
156
157    _store_queue                      = new Tstore_queue_entry_t              [_param->_size_store_queue];
158    _load_queue                       = new Tload_queue_entry_t               [_param->_size_load_queue];
159    _speculative_access_queue         = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue];
160    _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue);
161
162    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
163  };
164
165}; // end namespace load_store_unit
166}; // end namespace execute_unit
167}; // end namespace multi_execute_unit
168}; // end namespace execute_loop
169}; // end namespace multi_execute_loop
170}; // end namespace core
171
172}; // end namespace behavioural
173}; // end namespace morpheo             
174#endif
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