1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Load_store_unit_allocation.cpp 97 2008-12-19 15:34:00Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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10 | #include "Behavioural/include/Allocation.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_execute_unit { |
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18 | namespace execute_unit { |
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19 | namespace load_store_unit { |
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20 | |
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21 | |
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22 | |
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23 | #undef FUNCTION |
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24 | #define FUNCTION "Load_store_unit::allocation" |
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25 | void Load_store_unit::allocation (void) |
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26 | { |
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27 | log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); |
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28 | |
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29 | _component = new Component (_usage); |
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30 | |
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31 | Entity * entity = _component->set_entity (_name |
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32 | ,"Load_store_unit" |
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33 | #ifdef POSITION |
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34 | ,COMBINATORY |
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35 | #endif |
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36 | ); |
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37 | |
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38 | _interfaces = entity->set_interfaces(); |
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39 | |
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40 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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41 | { |
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42 | Interface * interface = _interfaces->set_interface("" |
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43 | #ifdef POSITION |
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44 | ,IN |
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45 | ,SOUTH, |
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46 | _("Generalist interface") |
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47 | #endif |
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48 | ); |
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49 | |
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50 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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51 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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52 | } |
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53 | |
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54 | // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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55 | { |
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56 | ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); |
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57 | |
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58 | ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); |
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59 | ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK); |
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60 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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61 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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62 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); |
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63 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); |
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64 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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65 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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66 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); |
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67 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); |
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68 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); |
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69 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); |
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70 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); |
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71 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); |
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72 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); |
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73 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); |
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74 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); |
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75 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); |
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76 | ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); |
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77 | } |
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78 | |
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79 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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80 | { |
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81 | ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); |
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82 | |
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83 | ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); |
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84 | ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK); |
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85 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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86 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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87 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); |
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88 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); |
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89 | // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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90 | // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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91 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); |
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92 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); |
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93 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); |
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94 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); |
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95 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); |
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96 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); |
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97 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); |
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98 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); |
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99 | ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); |
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100 | } |
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101 | |
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102 | // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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103 | { |
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104 | ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); |
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105 | |
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106 | ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); |
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107 | ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); |
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108 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); |
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109 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); |
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110 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); |
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111 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); |
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112 | ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); |
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113 | } |
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114 | |
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115 | // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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116 | { |
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117 | ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); |
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118 | |
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119 | ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); |
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120 | ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); |
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121 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); |
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122 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); |
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123 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); |
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124 | ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); |
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125 | } |
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126 | // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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127 | |
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128 | { |
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129 | ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); |
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130 | |
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131 | ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); |
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132 | ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id ); |
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133 | ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); |
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134 | ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); |
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135 | } |
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136 | |
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137 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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138 | |
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139 | // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; |
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140 | |
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141 | // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; |
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142 | // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; |
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143 | // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; |
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144 | // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; |
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145 | |
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146 | // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; |
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147 | // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; |
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148 | // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; |
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149 | |
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150 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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151 | |
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152 | #ifdef POSITION |
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153 | if (usage_is_set(_usage,USE_POSITION)) |
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154 | _component->generate_file(); |
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155 | #endif |
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156 | |
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157 | _store_queue = new Tstore_queue_entry_t [_param->_size_store_queue]; |
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158 | _load_queue = new Tload_queue_entry_t [_param->_size_load_queue]; |
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159 | _speculative_access_queue = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue]; |
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160 | _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue); |
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161 | |
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162 | log_printf(FUNC,Load_store_unit,FUNCTION,"End"); |
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163 | }; |
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164 | |
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165 | }; // end namespace load_store_unit |
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166 | }; // end namespace execute_unit |
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167 | }; // end namespace multi_execute_unit |
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168 | }; // end namespace execute_loop |
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169 | }; // end namespace multi_execute_loop |
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170 | }; // end namespace core |
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171 | |
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172 | }; // end namespace behavioural |
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173 | }; // end namespace morpheo |
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174 | #endif |
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