1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_execute_loop { |
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15 | namespace execute_loop { |
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16 | namespace multi_execute_unit { |
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17 | namespace execute_unit { |
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18 | namespace load_store_unit { |
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19 | |
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20 | |
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21 | |
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22 | #undef FUNCTION |
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23 | #define FUNCTION "Load_store_unit::allocation" |
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24 | void Load_store_unit::allocation (void) |
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25 | { |
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26 | string rename; |
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27 | |
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28 | log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); |
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29 | |
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30 | _component = new Component (); |
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31 | |
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32 | Entity * entity = _component->set_entity (_name |
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33 | ,"Load_store_unit" |
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34 | #ifdef POSITION |
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35 | ,COMBINATORY |
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36 | #endif |
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37 | ); |
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38 | |
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39 | _interfaces = entity->set_interfaces(); |
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40 | |
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41 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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42 | { |
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43 | Interface * interface = _interfaces->set_interface("" |
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44 | #ifdef POSITION |
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45 | ,IN |
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46 | ,SOUTH, |
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47 | "Generalist interface" |
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48 | #endif |
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49 | ); |
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50 | |
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51 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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52 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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53 | } |
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54 | // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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55 | { |
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56 | Interface_fifo * interface = _interfaces->set_interface("memory_in" |
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57 | #ifdef POSITION |
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58 | ,IN |
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59 | ,WEST |
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60 | ,"Instruction from Reservations station" |
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61 | #endif |
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62 | ); |
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63 | |
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64 | in_MEMORY_IN_VAL = interface->set_signal_valack_in (VAL); |
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65 | out_MEMORY_IN_ACK = interface->set_signal_valack_out (ACK); |
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66 | |
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67 | if (_param->_have_port_context_id) |
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68 | in_MEMORY_IN_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id" ,_param->_size_context_id ); |
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69 | if (_param->_have_port_front_end_id) |
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70 | in_MEMORY_IN_FRONT_END_ID = interface->set_signal_in <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); |
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71 | if (_param->_have_port_ooo_engine_id) |
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72 | in_MEMORY_IN_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id ); |
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73 | if (_param->_have_port_packet_id) |
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74 | in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); |
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75 | in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); |
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76 | in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage |
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77 | in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); |
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78 | // in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 ); |
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79 | in_MEMORY_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); |
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80 | in_MEMORY_IN_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); |
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81 | in_MEMORY_IN_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); |
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82 | // in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); |
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83 | // in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); |
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84 | in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,1 ); |
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85 | // in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); |
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86 | // in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 ); |
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87 | } |
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88 | |
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89 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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90 | { |
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91 | Interface_fifo * interface = _interfaces->set_interface("memory_out" |
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92 | #ifdef POSITION |
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93 | ,OUT |
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94 | ,EAST |
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95 | ,"Instruction to write queue" |
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96 | #endif |
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97 | ); |
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98 | |
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99 | out_MEMORY_OUT_VAL = interface->set_signal_valack_out(VAL); |
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100 | in_MEMORY_OUT_ACK = interface->set_signal_valack_in (ACK); |
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101 | if (_param->_have_port_context_id) |
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102 | out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id" ,_param->_size_context_id ); |
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103 | if (_param->_have_port_front_end_id) |
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104 | out_MEMORY_OUT_FRONT_END_ID = interface->set_signal_out <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); |
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105 | if (_param->_have_port_ooo_engine_id) |
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106 | out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id ); |
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107 | if (_param->_have_port_packet_id) |
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108 | out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); |
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109 | out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); |
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110 | out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); |
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111 | out_MEMORY_OUT_DATA_RD = interface->set_signal_out <Tgeneral_data_t > ("data_rd" ,_param->_size_general_data ); |
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112 | // out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); |
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113 | // out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register ); |
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114 | // out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data ); |
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115 | out_MEMORY_OUT_EXCEPTION = interface->set_signal_out <Texception_t > ("exception" ,_param->_size_exception ); |
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116 | } |
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117 | |
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118 | // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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119 | { |
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120 | Interface_fifo * interface = _interfaces->set_interface("dcache_req" |
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121 | #ifdef POSITION |
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122 | ,OUT |
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123 | ,NORTH |
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124 | ,"Request port to dcache" |
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125 | #endif |
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126 | ); |
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127 | |
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128 | out_DCACHE_REQ_VAL = interface->set_signal_valack_out(VAL); |
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129 | in_DCACHE_REQ_ACK = interface->set_signal_valack_in (ACK); |
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130 | if (_param->_have_port_dcache_context_id) |
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131 | out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); |
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132 | out_DCACHE_REQ_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); |
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133 | out_DCACHE_REQ_ADDRESS = interface->set_signal_out <Tdcache_address_t > ("address" ,_param->_size_general_data); |
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134 | out_DCACHE_REQ_TYPE = interface->set_signal_out <Tdcache_type_t > ("type" ,_param->_size_dcache_type ); |
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135 | out_DCACHE_REQ_WDATA = interface->set_signal_out <Tdcache_data_t > ("wdata" ,_param->_size_general_data); |
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136 | } |
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137 | // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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138 | { |
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139 | Interface_fifo * interface = _interfaces->set_interface("dcache_rsp" |
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140 | #ifdef POSITION |
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141 | ,IN |
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142 | ,NORTH |
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143 | ,"Respons port from dcache" |
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144 | #endif |
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145 | ); |
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146 | |
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147 | in_DCACHE_RSP_VAL = interface->set_signal_valack_in (VAL); |
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148 | out_DCACHE_RSP_ACK = interface->set_signal_valack_out(ACK); |
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149 | if (_param->_have_port_dcache_context_id) |
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150 | in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); |
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151 | in_DCACHE_RSP_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); |
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152 | in_DCACHE_RSP_RDATA = interface->set_signal_in <Tdcache_data_t > ("rdata" ,_param->_size_general_data); |
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153 | in_DCACHE_RSP_ERROR = interface->set_signal_in <Tdcache_error_t> ("error" ,_param->_size_dcache_error); |
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154 | } |
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155 | // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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156 | |
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157 | if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) |
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158 | { |
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159 | out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_size_load_queue]; |
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160 | if (_param->_have_port_ooo_engine_id) |
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161 | out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_size_load_queue]; |
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162 | out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_size_load_queue]; |
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163 | out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_size_load_queue]; |
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164 | |
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165 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
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166 | { |
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167 | Interface_fifo * interface = _interfaces->set_interface("memory_out" |
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168 | #ifdef POSITION |
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169 | ,OUT |
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170 | ,NORTH |
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171 | ,"Bypass between the load queue and the reservation station" |
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172 | #endif |
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173 | ); |
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174 | |
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175 | out_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_out(VAL); |
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176 | if (_param->_have_port_ooo_engine_id) |
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177 | out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t > ("ooo_engine_id", _param->_size_ooo_engine_id); |
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178 | out_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg" , _param->_size_general_register); |
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179 | out_BYPASS_MEMORY_DATA [i] = interface->set_signal_out <Tgeneral_data_t > ("data" , _param->_size_general_data); |
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180 | } |
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181 | } |
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182 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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183 | |
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184 | #ifdef POSITION |
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185 | _component->generate_file(); |
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186 | #endif |
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187 | |
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188 | _store_queue = new Tstore_queue_entry_t [_param->_size_store_queue]; |
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189 | _load_queue = new Tload_queue_entry_t [_param->_size_load_queue]; |
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190 | _speculative_access_queue = new Tspeculative_access_queue_entry_t [_param->_size_speculative_access_queue]; |
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191 | _speculative_access_queue_control = new morpheo::behavioural::generic::queue_control::Queue_Control (_param->_size_speculative_access_queue); |
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192 | |
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193 | log_printf(FUNC,Load_store_unit,FUNCTION,"End"); |
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194 | }; |
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195 | |
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196 | }; // end namespace load_store_unit |
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197 | }; // end namespace execute_unit |
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198 | }; // end namespace multi_execute_unit |
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199 | }; // end namespace execute_loop |
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200 | }; // end namespace multi_execute_loop |
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201 | }; // end namespace core |
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202 | |
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203 | }; // end namespace behavioural |
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204 | }; // end namespace morpheo |
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205 | #endif |
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