1 | #ifdef SYSTEMC |
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2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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3 | /* |
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4 | * $Id$ |
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5 | * |
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6 | * [ Description ] |
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7 | * |
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8 | */ |
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9 | |
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10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_execute_unit { |
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18 | namespace execute_unit { |
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19 | namespace load_store_unit { |
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20 | |
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21 | |
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22 | #undef FUNCTION |
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23 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore" |
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24 | void Load_store_unit::function_speculative_load_commit_genMoore (void) |
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25 | { |
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26 | log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); |
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27 | |
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28 | // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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29 | |
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30 | Tcontext_t memory_out_context_id = 0; |
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31 | Tpacket_t memory_out_packet_id = 0; |
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32 | Tcontrol_t memory_out_write_rd = 0; |
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33 | Tgeneral_address_t memory_out_num_reg_rd = 0; |
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34 | Tgeneral_data_t memory_out_data_rd = 0; |
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35 | // Tcontrol_t memory_out_write_re = 0; |
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36 | // Tspecial_address_t memory_out_num_reg_re = 0; |
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37 | // Tspecial_data_t memory_out_data_re = 0; |
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38 | Texception_t memory_out_exception = 0; |
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39 | |
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40 | internal_MEMORY_OUT_VAL = 0; |
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41 | |
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42 | // Test store and load queue |
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43 | // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!! |
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44 | |
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45 | // Test an store must be commited. |
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46 | if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) |
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47 | { |
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48 | internal_MEMORY_OUT_VAL = 1; |
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49 | internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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50 | |
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51 | memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id; |
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52 | memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ; |
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53 | // memory_out_write_rd |
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54 | // memory_out_num_reg_rd |
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55 | // memory_out_data_rd |
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56 | memory_out_exception = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._exception; |
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57 | } |
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58 | |
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59 | // write output |
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60 | PORT_WRITE(out_MEMORY_OUT_VAL , internal_MEMORY_OUT_VAL); |
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61 | |
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62 | PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id); |
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63 | PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id ); |
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64 | PORT_WRITE(out_MEMORY_OUT_WRITE_RD , memory_out_write_rd ); |
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65 | PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd); |
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66 | PORT_WRITE(out_MEMORY_OUT_DATA_RD , memory_out_data_rd ); |
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67 | // PORT_WRITE(out_MEMORY_OUT_WRITE_RE , memory_out_write_re ); |
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68 | // PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE, memory_out_num_reg_re); |
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69 | // PORT_WRITE(out_MEMORY_OUT_DATA_RE , memory_out_data_re ); |
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70 | PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception ); |
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71 | |
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72 | // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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73 | |
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74 | Tcontext_t dcache_req_context_id; |
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75 | Tpacket_t dcache_req_packet_id ; |
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76 | Tdcache_address_t dcache_req_address ; |
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77 | Tdcache_type_t dcache_req_type ; |
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78 | Tcontrol_t dcache_req_uncached ; |
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79 | Tdcache_data_t dcache_req_wdata ; |
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80 | |
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81 | internal_DCACHE_REQ_VAL = 0; |
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82 | |
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83 | // Test store and load queue |
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84 | |
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85 | // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!! |
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86 | |
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87 | // Test an store must be commited. |
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88 | if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE) |
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89 | { |
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90 | internal_DCACHE_REQ_VAL = 1; |
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91 | internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE; |
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92 | |
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93 | dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id; |
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94 | dcache_req_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ; |
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95 | dcache_req_address = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address ; |
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96 | dcache_req_type = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type; |
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97 | dcache_req_uncached = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached ; |
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98 | dcache_req_wdata = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata ; |
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99 | } |
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100 | |
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101 | PORT_WRITE(out_DCACHE_REQ_VAL , internal_DCACHE_REQ_VAL); |
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102 | PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id); |
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103 | PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id ); |
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104 | PORT_WRITE(out_DCACHE_REQ_ADDRESS , dcache_req_address ); |
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105 | PORT_WRITE(out_DCACHE_REQ_TYPE , dcache_req_type ); |
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106 | PORT_WRITE(out_DCACHE_REQ_UNCACHED , dcache_req_uncached ); |
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107 | PORT_WRITE(out_DCACHE_REQ_WDATA , dcache_req_wdata ); |
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108 | |
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109 | log_printf(FUNC,Load_store_unit,FUNCTION,"End"); |
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110 | }; |
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111 | |
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112 | }; // end namespace load_store_unit |
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113 | }; // end namespace execute_unit |
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114 | }; // end namespace multi_execute_unit |
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115 | }; // end namespace execute_loop |
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116 | }; // end namespace multi_execute_loop |
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117 | }; // end namespace core |
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118 | |
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119 | }; // end namespace behavioural |
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120 | }; // end namespace morpheo |
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121 | #endif |
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122 | //#endif |
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