#ifdef SYSTEMC
//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
/*
 * $Id$
 *
 * [ Description ]
 * 
 */

#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"

namespace morpheo                    {
namespace behavioural {
namespace core {
namespace multi_execute_loop {
namespace execute_loop {
namespace multi_execute_unit {
namespace execute_unit {
namespace load_store_unit {


#undef  FUNCTION
#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
  void Load_store_unit::function_speculative_load_commit_genMoore (void)
  {
    log_printf(FUNC,Load_store_unit,FUNCTION,"Begin");

    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    Tcontext_t         memory_out_context_id = 0;
    Tpacket_t          memory_out_packet_id  = 0;
    Tcontrol_t         memory_out_write_rd   = 0;
    Tgeneral_address_t memory_out_num_reg_rd = 0;
    Tgeneral_data_t    memory_out_data_rd    = 0;
//  Tcontrol_t         memory_out_write_re   = 0;
//  Tspecial_address_t memory_out_num_reg_re = 0;
//  Tspecial_data_t    memory_out_data_re    = 0;
    Texception_t       memory_out_exception  = 0;

    internal_MEMORY_OUT_VAL          = 0;

    // Test store and load queue
    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!

    // Test an store must be commited.
    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
      {
	internal_MEMORY_OUT_VAL          = 1;
	internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
	
	memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
	memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
//	memory_out_write_rd  
//	memory_out_num_reg_rd
//	memory_out_data_rd   
	memory_out_exception = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._exception;
      }

    // write output
    PORT_WRITE(out_MEMORY_OUT_VAL       , internal_MEMORY_OUT_VAL);

    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id);
    PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id );
    PORT_WRITE(out_MEMORY_OUT_WRITE_RD  , memory_out_write_rd  );
    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd);
    PORT_WRITE(out_MEMORY_OUT_DATA_RD   , memory_out_data_rd   );
//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE  , memory_out_write_re  );
//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE, memory_out_num_reg_re);
//  PORT_WRITE(out_MEMORY_OUT_DATA_RE   , memory_out_data_re   );
    PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception );

    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    Tcontext_t        dcache_req_context_id;
    Tpacket_t         dcache_req_packet_id ;
    Tdcache_address_t dcache_req_address   ;
    Tdcache_type_t    dcache_req_type      ;
    Tcontrol_t        dcache_req_uncached  ;
    Tdcache_data_t    dcache_req_wdata     ;

    internal_DCACHE_REQ_VAL          = 0;

    // Test store and load queue

    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!

    // Test an store must be commited.
    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
      {
	internal_DCACHE_REQ_VAL          = 1;
	internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;

	dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
	dcache_req_packet_id  = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
	dcache_req_address    = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address   ;
	dcache_req_type       = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type;
	dcache_req_uncached   = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached  ;
	dcache_req_wdata      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata     ;
      }

    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
    PORT_WRITE(out_DCACHE_REQ_UNCACHED  , dcache_req_uncached  );
    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
    
    log_printf(FUNC,Load_store_unit,FUNCTION,"End");
  };

}; // end namespace load_store_unit
}; // end namespace execute_unit
}; // end namespace multi_execute_unit
}; // end namespace execute_loop
}; // end namespace multi_execute_loop
}; // end namespace core

}; // end namespace behavioural
}; // end namespace morpheo              
#endif
//#endif