source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago

1) Add soc test
2) fix bug (Pc management, Decod and execute, Update prediction ...)
  • Property svn:keywords set to Id
File size: 11.2 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 101 2009-01-15 17:19:08Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22#undef  FUNCTION
23#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
24  void Load_store_unit::function_speculative_load_commit_genMoore (void)
25  {
26    log_begin(Load_store_unit,FUNCTION);
27    log_function(Load_store_unit,FUNCTION,_name.c_str());
28
29    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
30
31    Tcontext_t         memory_out_context_id    = 0;
32    Tcontext_t         memory_out_front_end_id  = 0;
33    Tcontext_t         memory_out_ooo_engine_id = 0;
34    Tpacket_t          memory_out_packet_id     = 0;
35    Tcontrol_t         memory_out_write_rd      = 0;
36    Tgeneral_address_t memory_out_num_reg_rd    = 0;
37    Tgeneral_data_t    memory_out_data_rd       = 0;
38//  Tcontrol_t         memory_out_write_re      = 0;
39//  Tspecial_address_t memory_out_num_reg_re    = 0;
40//  Tspecial_data_t    memory_out_data_re       = 0;
41    Texception_t       memory_out_exception     = 0;
42
43    internal_MEMORY_OUT_VAL = 0;
44
45    // Test store and load queue
46
47    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
48
49    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
50    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
51//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
52      {
53//      internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
54        internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
55                                   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
56       
57        if (internal_MEMORY_OUT_VAL)
58          {
59            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
60            internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
61           
62            memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
63            memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
64            memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
65            memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
66            memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
67            memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
68
69            Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
70            Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
71                                                             data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
72                                                             _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
73                                                             _load_queue [internal_MEMORY_OUT_PTR]._access_size);
74            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
75            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
76            log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
77            log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
78            log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
79            log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
80
81            Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
82            bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
83                                           (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
84
85            // if exception, rdata content the address of load, else content read data.
86            memory_out_data_rd       = (have_exception)?data_old:data_new;
87            memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
88
89            break; // we have find a entry !!! stop the search
90          }
91      }
92
93    if (not internal_MEMORY_OUT_VAL)
94      {
95        log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
96        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
97          {
98            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",reg_STORE_QUEUE_PTR_READ);
99
100            internal_MEMORY_OUT_VAL          = 1;
101            internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
102           
103            memory_out_context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
104            memory_out_front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
105            memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
106            memory_out_packet_id     = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ;
107//          memory_out_write_rd         
108//          memory_out_num_reg_rd       
109            memory_out_data_rd       = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception
110            memory_out_exception     = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception;
111          }
112      }
113    // write output
114    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
115
116    if (_param->_have_port_context_id)
117    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
118    if (_param->_have_port_front_end_id)
119    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
120    if (_param->_have_port_ooo_engine_id)
121    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
122    if (_param->_have_port_rob_ptr)
123    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
124//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
125//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
126    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
127    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
128    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
129//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
130//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
131//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
132    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
133    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
134    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
135    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
136    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
137    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
138
139    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
140
141    Tcontext_t        dcache_req_context_id;
142    Tpacket_t         dcache_req_packet_id ;
143    Tdcache_address_t dcache_req_address   ;
144    Tdcache_type_t    dcache_req_type      ;
145    Tdcache_data_t    dcache_req_wdata     ;
146
147    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
148
149    internal_DCACHE_REQ_VAL = 0;
150
151    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
152
153    // Test store and load queue
154    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
155      {
156        log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
157
158        internal_DCACHE_REQ_VAL          = 1;
159        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
160
161        if (_param->_have_port_dcache_context_id)
162          {
163            Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
164            Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
165            Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
166           
167            dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
168                                     (front_end_id <<(_param->_size_context_id)) |
169                                     (context_id));
170          }
171
172        dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
173        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
174        dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
175
176//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
177//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
178        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
179
180#ifdef SYSTEMC_VHDL_COMPATIBILITY
181        dcache_req_wdata      = 0;
182#endif
183      }
184    else
185      {
186        // Test an store must be commited.
187        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
188          {
189            internal_DCACHE_REQ_VAL          = 1;
190            internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
191           
192            if (_param->_have_port_dcache_context_id)
193              {
194                Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
195                Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
196                Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
197               
198                dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
199                                         (front_end_id <<(_param->_size_context_id)) |
200                                         (context_id));
201              }
202
203            // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
204            dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
205            dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address   ;
206            dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
207            dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata     ;
208          }
209      }
210
211    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
212    if (_param->_have_port_dcache_context_id)
213    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
214    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
215    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
216    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
217    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
218   
219    log_end(Load_store_unit,FUNCTION);
220  };
221
222}; // end namespace load_store_unit
223}; // end namespace execute_unit
224}; // end namespace multi_execute_unit
225}; // end namespace execute_loop
226}; // end namespace multi_execute_loop
227}; // end namespace core
228
229}; // end namespace behavioural
230}; // end namespace morpheo             
231#endif
232//#endif
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