source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago

1) Platforms : add new organization for test
2) Load_Store_Unit : add array to count nb_check in store_queue
3) Issue_queue and Core_Glue : rewrite the issue network
4) Special_Register_Unit : add reset value to register CID
5) Softwares : add multicontext test
6) Softwares : add SPECINT
7) Softwares : add MiBench?
7) Read_queue : inhib access for r0
8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
  • Property svn:keywords set to Id
File size: 11.7 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 117 2009-05-16 14:42:39Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22#undef  FUNCTION
23#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
24  void Load_store_unit::function_speculative_load_commit_genMoore (void)
25  {
26    log_begin(Load_store_unit,FUNCTION);
27    log_function(Load_store_unit,FUNCTION,_name.c_str());
28
29    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
30
31    Tcontext_t         memory_out_context_id    = 0;
32    Tcontext_t         memory_out_front_end_id  = 0;
33    Tcontext_t         memory_out_ooo_engine_id = 0;
34    Tpacket_t          memory_out_packet_id     = 0;
35    Tcontrol_t         memory_out_write_rd      = 0;
36    Tgeneral_address_t memory_out_num_reg_rd    = 0;
37    Tgeneral_data_t    memory_out_data_rd       = 0;
38//  Tcontrol_t         memory_out_write_re      = 0;
39//  Tspecial_address_t memory_out_num_reg_re    = 0;
40//  Tspecial_data_t    memory_out_data_re       = 0;
41    Texception_t       memory_out_exception     = 0;
42
43    internal_MEMORY_OUT_VAL = 0;
44
45    // Test store and load queue
46
47    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
48
49    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
50    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
51//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
52      {
53//      internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
54        internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK) or
55                                   (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT));
56       
57        if (internal_MEMORY_OUT_VAL)
58          {
59            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
60            internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
61           
62            memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
63            memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
64            memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
65            memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
66            memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
67            memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
68
69            Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
70            Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
71                                                             data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
72                                                             _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
73                                                             _load_queue [internal_MEMORY_OUT_PTR]._access_size);
74            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
75            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
76            log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
77            log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
78            log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
79            log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
80            log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
81
82            Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
83            bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
84                                           (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
85
86            // if exception, rdata content the address of load, else content read data.
87            memory_out_data_rd       = (have_exception)?data_old:data_new;
88            memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
89
90            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
91            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
92
93            break; // we have find a entry !!! stop the search
94          }
95      }
96
97    if (not internal_MEMORY_OUT_VAL)
98      {
99        log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
100        // Can retire an store instruction if :
101        //  * state is commit
102        //  * none load must check this store
103        if ((_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT) and
104            (reg_STORE_QUEUE_NB_CHECK [reg_STORE_QUEUE_PTR_READ] == 0))
105          {
106            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",reg_STORE_QUEUE_PTR_READ);
107
108            internal_MEMORY_OUT_VAL          = 1;
109            internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
110           
111            memory_out_context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
112            memory_out_front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
113            memory_out_ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
114            memory_out_packet_id     = _store_queue [reg_STORE_QUEUE_PTR_READ]._packet_id ;
115//          memory_out_write_rd         
116//          memory_out_num_reg_rd       
117            memory_out_data_rd       = _store_queue [reg_STORE_QUEUE_PTR_READ]._address; // to the exception
118            memory_out_exception     = _store_queue [reg_STORE_QUEUE_PTR_READ]._exception;
119          }
120      }
121    // write output
122    PORT_WRITE(out_MEMORY_OUT_VAL          [0], internal_MEMORY_OUT_VAL);
123
124    if (_param->_have_port_context_id)
125    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
126    if (_param->_have_port_front_end_id)
127    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
128    if (_param->_have_port_ooo_engine_id)
129    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
130    if (_param->_have_port_rob_ptr)
131    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
132//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
133//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
134    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
135    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
136    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
137//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
138//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
139//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
140    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
141    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
142    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
143    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
144    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], 0);
145    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
146
147    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
148
149    Tcontext_t        dcache_req_context_id;
150    Tpacket_t         dcache_req_packet_id ;
151    Tdcache_address_t dcache_req_address   ;
152    Tdcache_type_t    dcache_req_type      ;
153    Tdcache_data_t    dcache_req_wdata     ;
154
155    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
156
157    internal_DCACHE_REQ_VAL = 0;
158
159    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
160
161    // Test store and load queue
162    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
163      {
164        log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
165
166        internal_DCACHE_REQ_VAL          = 1;
167        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
168
169        if (_param->_have_port_dcache_context_id)
170          {
171            Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
172            Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
173            Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
174           
175            dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
176                                     (front_end_id <<(_param->_size_context_id)) |
177                                     (context_id));
178          }
179
180        dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
181        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
182        dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
183
184//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
185//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
186        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
187
188#ifdef SYSTEMC_VHDL_COMPATIBILITY
189        dcache_req_wdata      = 0;
190#endif
191      }
192    else
193      {
194        // Test an store must be commited.
195        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
196          {
197            internal_DCACHE_REQ_VAL          = 1;
198            internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
199           
200            if (_param->_have_port_dcache_context_id)
201              {
202                Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
203                Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
204                Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
205               
206                dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
207                                         (front_end_id <<(_param->_size_context_id)) |
208                                         (context_id));
209              }
210
211            // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
212            dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
213            dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
214            dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
215            dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
216          }
217      }
218
219    PORT_WRITE(out_DCACHE_REQ_VAL       [0], internal_DCACHE_REQ_VAL);
220    if (_param->_have_port_dcache_context_id)
221    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
222    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
223    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
224    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
225    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
226   
227    log_end(Load_store_unit,FUNCTION);
228  };
229
230}; // end namespace load_store_unit
231}; // end namespace execute_unit
232}; // end namespace multi_execute_unit
233}; // end namespace execute_loop
234}; // end namespace multi_execute_loop
235}; // end namespace core
236
237}; // end namespace behavioural
238}; // end namespace morpheo             
239#endif
240//#endif
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