source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago

1) add test with SPECINT2K
2) new config of Selftest
3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table)
4) add Function_pointer but need fix
  • Property svn:keywords set to Id
File size: 13.3 KB
Line 
1#ifdef SYSTEMC
2//#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
3/*
4 * $Id: Load_store_unit_function_speculative_load_commit_genMoore.cpp 145 2010-10-13 18:15:51Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h"
11
12namespace morpheo                    {
13namespace behavioural {
14namespace core {
15namespace multi_execute_loop {
16namespace execute_loop {
17namespace multi_execute_unit {
18namespace execute_unit {
19namespace load_store_unit {
20
21
22#undef  FUNCTION
23#define FUNCTION "Load_store_unit::function_speculative_load_commit_genMoore"
24  void Load_store_unit::function_speculative_load_commit_genMoore (void)
25  {
26    log_begin(Load_store_unit,FUNCTION);
27    log_function(Load_store_unit,FUNCTION,_name.c_str());
28
29    if (PORT_READ(in_NRESET))
30      {
31    // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
32
33    Tcontext_t         memory_out_context_id    = 0;
34    Tcontext_t         memory_out_front_end_id  = 0;
35    Tcontext_t         memory_out_ooo_engine_id = 0;
36    Tpacket_t          memory_out_packet_id     = 0;
37    Tcontrol_t         memory_out_cancel        = 0;
38    Tcontrol_t         memory_out_write_rd      = 0;
39    Tgeneral_address_t memory_out_num_reg_rd    = 0;
40    Tgeneral_data_t    memory_out_data_rd       = 0;
41//  Tcontrol_t         memory_out_write_re      = 0;
42//  Tspecial_address_t memory_out_num_reg_re    = 0;
43//  Tspecial_data_t    memory_out_data_re       = 0;
44    Tcontrol_t         memory_out_no_sequence   = 0;
45    Texception_t       memory_out_exception     = 0;
46
47    internal_MEMORY_OUT_VAL = 0;
48
49    // Test store and load queue
50
51    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test MEMORY_OUT");
52
53    log_printf(TRACE,Load_store_unit,FUNCTION,"    * Load  queue");
54    for (internal_MEMORY_OUT_PTR=0; internal_MEMORY_OUT_PTR<_param->_size_load_queue; internal_MEMORY_OUT_PTR++)
55//     for (uin32_t i=0; (i<_param->_size_load_queue) and not (find_load); i++)
56      {
57//      internal_MEMORY_OUT_PTR = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue;
58
59        // have valid entry if :
60        //  * load_queue entry need commit
61        //  * load_queue entry have rsp and can make a speculative commit
62        internal_MEMORY_OUT_VAL = ((_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT) or
63                                   (_load_queue[internal_MEMORY_OUT_PTR]._can_speculative_commit and (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK))
64                                   );
65       
66        if (internal_MEMORY_OUT_VAL)
67          {
68            log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
69            internal_MEMORY_OUT_SELECT_QUEUE = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?SELECT_LOAD_QUEUE_SPECULATIVE:SELECT_LOAD_QUEUE;
70           
71            memory_out_context_id    = _load_queue [internal_MEMORY_OUT_PTR]._context_id;
72            memory_out_front_end_id  = _load_queue [internal_MEMORY_OUT_PTR]._front_end_id;
73            memory_out_ooo_engine_id = _load_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
74            memory_out_packet_id     = _load_queue [internal_MEMORY_OUT_PTR]._packet_id ;
75            memory_out_cancel        = _load_queue [internal_MEMORY_OUT_PTR]._cancel    ;
76            memory_out_write_rd      = _load_queue [internal_MEMORY_OUT_PTR]._write_rd  ;
77            memory_out_num_reg_rd    = _load_queue [internal_MEMORY_OUT_PTR]._num_reg_rd;
78
79            Tdcache_data_t data_old = _load_queue [internal_MEMORY_OUT_PTR]._rdata;
80            Tdcache_data_t data_new = extend<Tdcache_data_t>(_param->_size_general_data,
81                                                             data_old >> _load_queue [internal_MEMORY_OUT_PTR]._shift,
82                                                             _load_queue [internal_MEMORY_OUT_PTR]._is_load_signed,
83                                                             _load_queue [internal_MEMORY_OUT_PTR]._access_size);
84            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (old) : %.8x",data_old);
85            log_printf(TRACE,Load_store_unit,FUNCTION,"    * data (new) : %.8x",data_new);
86            log_printf(TRACE,Load_store_unit,FUNCTION,"      * address      : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._address);
87            log_printf(TRACE,Load_store_unit,FUNCTION,"      * rdata        : %.8x",_load_queue [internal_MEMORY_OUT_PTR]._rdata);
88            log_printf(TRACE,Load_store_unit,FUNCTION,"      * shift        : %d",_load_queue [internal_MEMORY_OUT_PTR]._shift);
89            log_printf(TRACE,Load_store_unit,FUNCTION,"      * signed?      : %d",_load_queue [internal_MEMORY_OUT_PTR]._is_load_signed);
90            log_printf(TRACE,Load_store_unit,FUNCTION,"      * access_size  : %d",_load_queue [internal_MEMORY_OUT_PTR]._access_size);
91
92            Texception_t exception      = _load_queue [internal_MEMORY_OUT_PTR]._exception;
93            bool         have_exception = ((exception != EXCEPTION_MEMORY_NONE) and
94                                           (exception != EXCEPTION_MEMORY_MISS_SPECULATION));
95
96            // if exception, rdata content the address of load, else content read data.
97            memory_out_data_rd       = (have_exception)?data_old:data_new;
98            memory_out_exception     = (_load_queue[internal_MEMORY_OUT_PTR]._state == LOAD_QUEUE_COMMIT_CHECK)?EXCEPTION_MEMORY_LOAD_SPECULATIVE:exception;
99
100            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",exception);
101            log_printf(TRACE,Load_store_unit,FUNCTION,"      * exception    : %d",memory_out_exception);
102
103            break; // we have find a entry !!! stop the search
104          }
105      }
106
107    if (not internal_MEMORY_OUT_VAL)
108      {
109        log_printf(TRACE,Load_store_unit,FUNCTION,"    * Store queue");
110
111        for (uint32_t i=0; i<_param->_size_store_queue; ++i)
112          {
113            internal_MEMORY_OUT_PTR = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue;
114            // Can retire an store instruction if :
115            //  * state is commit
116            //  * none load must check this store
117
118
119            bool val_head = ((i==0) and
120                             (_store_queue [internal_MEMORY_OUT_PTR]._state       == STORE_QUEUE_COMMIT) and
121                             (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == true) and
122                             (reg_STORE_QUEUE_NB_CHECK [internal_MEMORY_OUT_PTR] == 0)
123                             );
124
125            bool val_commit = ((_store_queue [internal_MEMORY_OUT_PTR]._state       != STORE_QUEUE_EMPTY) and
126                               (_store_queue [internal_MEMORY_OUT_PTR]._send_commit == false));
127
128            if (val_head or val_commit)
129              {
130                log_printf(TRACE,Load_store_unit,FUNCTION,"    * find : %d",internal_MEMORY_OUT_PTR);
131               
132                internal_MEMORY_OUT_VAL          = 1;
133                internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
134               
135                memory_out_context_id    = _store_queue [internal_MEMORY_OUT_PTR]._context_id;
136                memory_out_front_end_id  = _store_queue [internal_MEMORY_OUT_PTR]._front_end_id;
137                memory_out_ooo_engine_id = _store_queue [internal_MEMORY_OUT_PTR]._ooo_engine_id;
138                memory_out_packet_id     = _store_queue [internal_MEMORY_OUT_PTR]._packet_id ;
139                memory_out_cancel        = _store_queue [internal_MEMORY_OUT_PTR]._cancel;
140//              memory_out_write_rd     
141//              memory_out_num_reg_rd   
142                memory_out_data_rd       = _store_queue [internal_MEMORY_OUT_PTR]._address; // to the exception
143                memory_out_exception     = _store_queue [internal_MEMORY_OUT_PTR]._exception;
144                memory_out_no_sequence   = val_commit;
145                break; // find an entry
146              }
147
148          }
149      }
150
151    // write output
152    if (_param->_have_port_context_id)
153    PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID   [0], memory_out_context_id   );
154    if (_param->_have_port_front_end_id)
155    PORT_WRITE(out_MEMORY_OUT_FRONT_END_ID [0], memory_out_front_end_id );
156    if (_param->_have_port_ooo_engine_id)
157    PORT_WRITE(out_MEMORY_OUT_OOO_ENGINE_ID[0], memory_out_ooo_engine_id);
158    if (_param->_have_port_rob_ptr)
159    PORT_WRITE(out_MEMORY_OUT_PACKET_ID    [0], memory_out_packet_id    );
160//  PORT_WRITE(out_MEMORY_OUT_OPERATION    [0], memory_out_operation    );
161//  PORT_WRITE(out_MEMORY_OUT_TYPE         [0], TYPE_MEMORY             );
162    PORT_WRITE(out_MEMORY_OUT_CANCEL       [0], memory_out_cancel       );
163    PORT_WRITE(out_MEMORY_OUT_WRITE_RD     [0], memory_out_write_rd     );
164    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD   [0], memory_out_num_reg_rd   );
165    PORT_WRITE(out_MEMORY_OUT_DATA_RD      [0], memory_out_data_rd      );
166//  PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], memory_out_write_re     );
167//  PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], memory_out_num_reg_re   );
168//  PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], memory_out_data_re      );
169    PORT_WRITE(out_MEMORY_OUT_WRITE_RE     [0], 0);
170    PORT_WRITE(out_MEMORY_OUT_NUM_REG_RE   [0], 0);
171    PORT_WRITE(out_MEMORY_OUT_DATA_RE      [0], 0);
172    PORT_WRITE(out_MEMORY_OUT_EXCEPTION    [0], memory_out_exception    );
173    PORT_WRITE(out_MEMORY_OUT_NO_SEQUENCE  [0], memory_out_no_sequence  );// hack
174#ifdef DEBUG
175    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], memory_out_data_rd);
176#else
177    PORT_WRITE(out_MEMORY_OUT_ADDRESS      [0], 0);
178#endif
179
180    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
181
182    Tcontext_t        dcache_req_context_id = 0;
183    Tpacket_t         dcache_req_packet_id  = 0;
184    Tdcache_address_t dcache_req_address    = 0;
185    Tdcache_type_t    dcache_req_type       = 0;
186    Tdcache_data_t    dcache_req_wdata      = 0;
187
188    log_printf(TRACE,Load_store_unit,FUNCTION,"  * Test DCACHE_REQ");
189
190    internal_DCACHE_REQ_VAL = 0;
191
192    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = (*_speculative_access_queue_control)[0];
193
194    // Test store and load queue
195    if (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE)
196      {
197        log_printf(TRACE,Load_store_unit,FUNCTION,"    * speculative_access_queue [%d]",internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ);
198
199        internal_DCACHE_REQ_VAL          = 1;
200        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
201
202        if (_param->_have_port_dcache_context_id)
203          {
204            Tcontext_t context_id    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id;
205            Tcontext_t front_end_id  = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id;
206            Tcontext_t ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id;
207           
208            dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
209                                     (front_end_id <<(_param->_size_context_id)) |
210                                     (context_id));
211          }
212
213        dcache_req_packet_id  = DCACHE_REQ_IS_LOAD(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write);
214        dcache_req_address    = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address;// & _param->_mask_address_msb;
215        dcache_req_type       = operation_to_dcache_type(_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation);
216
217//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * address            : %.8x",_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address);
218//      log_printf(TRACE,Load_store_unit,FUNCTION,"      * mask               : %.8x",_param->_mask_address_msb);
219        log_printf(TRACE,Load_store_unit,FUNCTION,"      * dcache_req_address : %.8x",dcache_req_address);
220
221#ifdef SYSTEMC_VHDL_COMPATIBILITY
222        dcache_req_wdata      = 0;
223#endif
224      }
225    else
226      {
227        // Test an store must be commited.
228        if (_store_queue [reg_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
229          {
230            internal_DCACHE_REQ_VAL          = 1;
231            internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
232           
233            if (_param->_have_port_dcache_context_id)
234              {
235                Tcontext_t context_id    = _store_queue [reg_STORE_QUEUE_PTR_READ]._context_id;
236                Tcontext_t front_end_id  = _store_queue [reg_STORE_QUEUE_PTR_READ]._front_end_id;
237                Tcontext_t ooo_engine_id = _store_queue [reg_STORE_QUEUE_PTR_READ]._ooo_engine_id;
238               
239                dcache_req_context_id = ((ooo_engine_id<<(_param->_size_context_id + _param->_size_front_end_id )) |
240                                         (front_end_id <<(_param->_size_context_id)) |
241                                         (context_id));
242              }
243
244            // FIXME : il peut avoir plusieurs store avec le même paquet_id ... pour l'instant pas très grave car pas de retour (enfin seul les bus error sont des retours)
245            dcache_req_packet_id  = DCACHE_REQ_IS_STORE(reg_STORE_QUEUE_PTR_READ);
246            dcache_req_address    = _store_queue [reg_STORE_QUEUE_PTR_READ]._address;
247            dcache_req_type       = operation_to_dcache_type(_store_queue [reg_STORE_QUEUE_PTR_READ]._operation);
248            dcache_req_wdata      = _store_queue [reg_STORE_QUEUE_PTR_READ]._wdata;
249          }
250      }
251
252    if (_param->_have_port_dcache_context_id)
253    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID[0], dcache_req_context_id);
254    PORT_WRITE(out_DCACHE_REQ_PACKET_ID [0], dcache_req_packet_id );
255    PORT_WRITE(out_DCACHE_REQ_ADDRESS   [0], dcache_req_address   );
256    PORT_WRITE(out_DCACHE_REQ_TYPE      [0], dcache_req_type      );
257    PORT_WRITE(out_DCACHE_REQ_WDATA     [0], dcache_req_wdata     );
258      }
259    else
260      {
261        // Reset
262    internal_MEMORY_OUT_VAL = 0;
263//  internal_MEMORY_OUT_PTR =0
264//  internal_MEMORY_OUT_SELECT_QUEUE = SELECT_STORE_QUEUE;
265
266    internal_DCACHE_REQ_VAL = 0;
267    internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = 0;
268//  internal_DCACHE_REQ_SELECT_QUEUE = SELECT_LOAD_QUEUE_SPECULATIVE;
269      }
270
271    // Write output
272    PORT_WRITE(out_MEMORY_OUT_VAL [0], internal_MEMORY_OUT_VAL);
273    PORT_WRITE(out_DCACHE_REQ_VAL [0], internal_DCACHE_REQ_VAL);
274
275
276    log_end(Load_store_unit,FUNCTION);
277  };
278
279}; // end namespace load_store_unit
280}; // end namespace execute_unit
281}; // end namespace multi_execute_unit
282}; // end namespace execute_loop
283}; // end namespace multi_execute_loop
284}; // end namespace core
285
286}; // end namespace behavioural
287}; // end namespace morpheo             
288#endif
289//#endif
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