[59] | 1 | #ifdef SYSTEMC |
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| 2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 3 | /* |
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| 4 | * $Id$ |
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| 5 | * |
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| 6 | * [ Description ] |
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| 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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| 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_execute_loop { |
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| 16 | namespace execute_loop { |
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| 17 | namespace multi_execute_unit { |
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| 18 | namespace execute_unit { |
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| 19 | namespace load_store_unit { |
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| 20 | |
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| 21 | |
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| 22 | #undef FUNCTION |
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| 23 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_transition" |
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| 24 | void Load_store_unit::function_speculative_load_commit_transition (void) |
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| 25 | { |
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| 26 | log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); |
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| 27 | |
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| 28 | if (PORT_READ(in_NRESET) == 0) |
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| 29 | { |
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| 30 | // Reset : clear all queue |
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| 31 | _speculative_access_queue_control->clear(); |
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| 32 | internal_MEMORY_STORE_QUEUE_PTR_READ = 0; |
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| 33 | internal_MEMORY_LOAD_QUEUE_PTR_READ = 0; |
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| 34 | |
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| 35 | for (uint32_t i=0; i< _param->_size_store_queue ; i++) |
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| 36 | _store_queue [i]._state = STORE_QUEUE_EMPTY; |
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| 37 | |
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| 38 | for (uint32_t i=0; i< _param->_size_load_queue ; i++) |
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| 39 | _load_queue [i]._state = LOAD_QUEUE_EMPTY; |
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| 40 | |
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| 41 | for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++) |
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| 42 | _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
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| 43 | } |
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| 44 | else |
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| 45 | { |
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| 46 | //================================================================ |
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| 47 | // Interface "MEMORY_IN" |
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| 48 | //================================================================ |
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| 49 | |
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| 50 | if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and |
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| 51 | ( internal_MEMORY_IN_ACK == 1)) |
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| 52 | { |
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| 53 | // Test operation : |
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| 54 | //~~~~~~~~~~~~~~~~~ |
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| 55 | // store in store_queue |
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| 56 | // load in speculation_access_queue |
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| 57 | // others in speculation_access_queue |
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| 58 | |
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[62] | 59 | Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); |
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| 60 | Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + |
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| 61 | PORT_READ(in_MEMORY_IN_DATA_RA )); |
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| 62 | bool exception_alignement = (mask_memory_access(operation) & address) != 0; |
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[59] | 63 | |
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| 64 | if (is_operation_memory_store(operation) == true) |
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| 65 | { |
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| 66 | // ======================= |
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| 67 | // ===== STORE_QUEUE ===== |
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| 68 | // ======================= |
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| 69 | // There a two store request type : |
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| 70 | // - first is operation with address and data |
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| 71 | // - second is the information of re order buffer : the store become not speculative and can access at the data cache |
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| 72 | |
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| 73 | log_printf(TRACE,Load_store_unit,FUNCTION,"store_queue"); |
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| 74 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
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| 75 | |
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| 76 | // Write pointer is define in rename stage : |
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| 77 | Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); |
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| 78 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
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| 79 | |
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| 80 | // Need read : state and exception. |
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| 81 | Tstore_queue_state_t old_state = _store_queue [index]._state; |
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| 82 | Tstore_queue_state_t new_state = old_state; |
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| 83 | bool update_info = false; |
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| 84 | |
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| 85 | Texception_t old_exception = _store_queue [index]._exception; |
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| 86 | Texception_t new_exception = old_exception; |
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| 87 | |
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| 88 | // Compute next state |
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| 89 | switch (old_state) |
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| 90 | { |
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| 91 | case STORE_QUEUE_EMPTY : |
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| 92 | { |
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| 93 | if (is_operation_memory_store_head(operation) == true) |
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| 94 | { |
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| 95 | new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE; |
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| 96 | |
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| 97 | // test if is a speculation |
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| 98 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
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| 99 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
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| 100 | else |
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| 101 | new_exception = EXCEPTION_MEMORY_NONE; |
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| 102 | } |
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| 103 | else |
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| 104 | { |
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| 105 | new_state = STORE_QUEUE_VALID_SPECULATIVE; |
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| 106 | |
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| 107 | // Test if have an exception |
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| 108 | if (exception_alignement == true) |
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| 109 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
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| 110 | else |
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| 111 | new_exception = EXCEPTION_MEMORY_NONE; |
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| 112 | |
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| 113 | update_info = true; |
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| 114 | } |
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| 115 | break; |
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| 116 | } |
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| 117 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
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| 118 | { |
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| 119 | // if (is_operation_memory_store_head(operation) == false) |
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| 120 | // { |
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| 121 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
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| 122 | |
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| 123 | // Test if have a new exception (priority : miss_speculation) |
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| 124 | if ((old_exception == EXCEPTION_MEMORY_NONE) and |
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| 125 | (exception_alignement == true)) |
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| 126 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
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| 127 | |
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| 128 | update_info = true; |
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| 129 | break; |
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| 130 | // } |
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| 131 | } |
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| 132 | case STORE_QUEUE_VALID_SPECULATIVE : |
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| 133 | { |
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| 134 | // if (is_operation_memory_store_head(operation) == true) |
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| 135 | // { |
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| 136 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
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| 137 | |
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| 138 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
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| 139 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
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| 140 | |
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| 141 | break; |
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| 142 | // } |
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| 143 | } |
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| 144 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
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| 145 | case STORE_QUEUE_COMMIT : |
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| 146 | { |
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| 147 | ErrorMorpheo("<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation"); |
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| 148 | } |
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| 149 | } |
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| 150 | |
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| 151 | _store_queue [index]._state = new_state; |
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| 152 | _store_queue [index]._exception = new_exception; |
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| 153 | |
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| 154 | if (update_info == true) |
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| 155 | { |
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| 156 | log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); |
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| 157 | |
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| 158 | _store_queue [index]._context_id = PORT_READ(in_MEMORY_IN_CONTEXT_ID ); |
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| 159 | _store_queue [index]._packet_id = PORT_READ(in_MEMORY_IN_PACKET_ID ); |
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[62] | 160 | _store_queue [index]._dcache_type = operation_to_dcache_type(operation); |
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| 161 | _store_queue [index]._uncached = 0; // is the MMU that have this info |
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[59] | 162 | _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); |
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| 163 | _store_queue [index]._address = address; |
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| 164 | _store_queue [index]._wdata = PORT_READ(in_MEMORY_IN_DATA_RB ); |
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| 165 | // _store_queue [index]._write_rd = PORT_READ(in_MEMORY_IN_WRITE_RD ); |
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| 166 | // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD ); |
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| 167 | } |
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| 168 | } |
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| 169 | else |
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| 170 | { |
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| 171 | // // ==================================== |
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| 172 | // // ===== SPECULATIVE_ACCESS_QUEUE ===== |
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| 173 | // // ==================================== |
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| 174 | |
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| 175 | // // In speculative access queue, they are many type's request |
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| 176 | // log_printf(TRACE,Load_store_unit,FUNCTION,"speculative_access_queue"); |
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| 177 | // log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
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| 178 | |
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| 179 | // // Write in reservation station |
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| 180 | // uint32_t index = _speculative_access_queue_control->push(); |
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| 181 | |
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| 182 | // log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
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| 183 | } |
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| 184 | } |
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| 185 | |
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| 186 | //================================================================ |
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| 187 | // Interface "MEMORY_OUT" |
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| 188 | //================================================================ |
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| 189 | |
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| 190 | if (( internal_MEMORY_OUT_VAL == 1) and |
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| 191 | (PORT_READ(in_MEMORY_OUT_ACK) == 1)) |
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| 192 | { |
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| 193 | switch (internal_MEMORY_OUT_SELECT_QUEUE) |
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| 194 | { |
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| 195 | case SELECT_STORE_QUEUE : |
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| 196 | { |
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| 197 | // ======================= |
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| 198 | // ===== STORE_QUEUE ===== |
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| 199 | // ======================= |
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| 200 | |
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| 201 | // Entry flush and increase the read pointer |
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| 202 | |
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| 203 | _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; |
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| 204 | |
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| 205 | internal_MEMORY_STORE_QUEUE_PTR_READ = (internal_MEMORY_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; |
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| 206 | |
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| 207 | break; |
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| 208 | } |
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| 209 | case SELECT_LOAD_QUEUE : |
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| 210 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
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| 211 | break; |
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| 212 | } |
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| 213 | } |
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[62] | 214 | |
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| 215 | //================================================================ |
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| 216 | // Interface "DCACHE_REQ" |
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| 217 | //================================================================ |
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| 218 | if (( internal_DCACHE_REQ_VAL == 1) and |
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| 219 | (PORT_READ(in_DCACHE_REQ_ACK) == 1)) |
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| 220 | { |
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| 221 | switch (internal_DCACHE_REQ_SELECT_QUEUE) |
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| 222 | { |
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| 223 | case SELECT_STORE_QUEUE : |
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| 224 | { |
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| 225 | // ======================= |
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| 226 | // ===== STORE_QUEUE ===== |
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| 227 | // ======================= |
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| 228 | |
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| 229 | // Entry flush and increase the read pointer |
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| 230 | |
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| 231 | _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT; |
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| 232 | |
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| 233 | break; |
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| 234 | } |
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| 235 | case SELECT_LOAD_QUEUE : |
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| 236 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
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| 237 | break; |
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| 238 | } |
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| 239 | } |
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| 240 | |
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| 241 | #if DEBUG>=DEBUG_TRACE |
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| 242 | // ***** dump store queue |
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| 243 | cout << "Dump store queue" << endl |
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| 244 | << "ptr_read : " << toString(static_cast<uint32_t>(internal_MEMORY_STORE_QUEUE_PTR_READ)) << endl; |
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| 245 | |
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| 246 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
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| 247 | { |
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| 248 | uint32_t j = (internal_MEMORY_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; |
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| 249 | cout << "{" << j << "}" << endl |
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| 250 | << _store_queue[j] << endl; |
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| 251 | } |
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| 252 | #endif |
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[59] | 253 | } |
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| 254 | |
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| 255 | log_printf(FUNC,Load_store_unit,FUNCTION,"End"); |
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| 256 | }; |
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| 257 | |
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| 258 | }; // end namespace load_store_unit |
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| 259 | }; // end namespace execute_unit |
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| 260 | }; // end namespace multi_execute_unit |
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| 261 | }; // end namespace execute_loop |
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| 262 | }; // end namespace multi_execute_loop |
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| 263 | }; // end namespace core |
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| 264 | |
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| 265 | }; // end namespace behavioural |
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| 266 | }; // end namespace morpheo |
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| 267 | #endif |
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| 268 | //#endif |
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