1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_execute_loop { |
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15 | namespace execute_loop { |
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16 | namespace multi_execute_unit { |
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17 | namespace execute_unit { |
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18 | namespace load_store_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_transition" |
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23 | void Load_store_unit::function_speculative_load_commit_transition (void) |
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24 | { |
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25 | log_printf(FUNC,Load_store_unit,FUNCTION,"Begin"); |
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26 | |
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27 | if (PORT_READ(in_NRESET) == 0) |
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28 | { |
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29 | // Reset : clear all queue |
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30 | _speculative_access_queue_control->clear(); |
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31 | |
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32 | reg_STORE_QUEUE_PTR_READ = 0; |
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33 | reg_LOAD_QUEUE_CHECK_PRIORITY = 0; |
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34 | |
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35 | for (uint32_t i=0; i< _param->_size_store_queue ; i++) |
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36 | _store_queue [i]._state = STORE_QUEUE_EMPTY; |
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37 | |
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38 | for (uint32_t i=0; i< _param->_size_load_queue ; i++) |
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39 | _load_queue [i]._state = LOAD_QUEUE_EMPTY; |
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40 | |
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41 | for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++) |
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42 | _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
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43 | } |
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44 | else |
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45 | { |
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46 | //================================================================ |
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47 | // Interface "PORT_CHECK" |
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48 | //================================================================ |
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49 | |
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50 | // Plusieurs moyens de faire la verification de dépendance entre les loads et les stores. |
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51 | // 1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue |
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52 | // 2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier. |
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53 | |
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54 | // solution 1) |
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55 | log_printf(TRACE,Load_store_unit,FUNCTION,"CHECK"); |
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56 | for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) |
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57 | { |
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58 | uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue; |
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59 | |
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60 | if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or |
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61 | (_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or |
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62 | (_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and |
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63 | is_operation_memory_load(_load_queue[index_load]._operation)) |
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64 | { |
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65 | log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); |
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66 | |
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67 | nb_check++; // use one port |
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68 | |
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69 | // find a entry that it need a check |
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70 | |
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71 | Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; |
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72 | bool end_check = false; |
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73 | bool change_state = false; |
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74 | bool next = false; |
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75 | |
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76 | // At the first store queue empty, stop check. |
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77 | // Explication : |
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78 | // * rename logic keep a empty case in the store queue (also size_store_queue > 1) |
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79 | // * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load. |
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80 | |
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81 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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82 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
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83 | { |
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84 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store == reg_STORE_QUEUE_PTR_READ"); |
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85 | end_check = true; |
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86 | change_state = true; |
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87 | } |
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88 | else |
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89 | { |
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90 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store != reg_STORE_QUEUE_PTR_READ"); |
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91 | |
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92 | index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming |
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93 | |
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94 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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95 | |
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96 | switch (_store_queue[index_store]._state) |
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97 | { |
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98 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
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99 | case STORE_QUEUE_COMMIT : |
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100 | case STORE_QUEUE_VALID_SPECULATIVE : |
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101 | { |
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102 | |
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103 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry"); |
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104 | |
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105 | // TODO : MMU - nous considérons que les adresses sont physique |
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106 | bool test_thread_id = true; |
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107 | |
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108 | // Test thread id. |
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109 | if (_param->_have_port_context_id) |
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110 | test_thread_id &= (_load_queue[index_load]._context_id == _store_queue[index_store]._context_id); |
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111 | if (_param->_have_port_front_end_id) |
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112 | test_thread_id &= (_load_queue[index_load]._front_end_id == _store_queue[index_store]._front_end_id); |
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113 | if (_param->_have_port_ooo_engine_id) |
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114 | test_thread_id &= (_load_queue[index_load]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id); |
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115 | |
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116 | if (test_thread_id) |
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117 | { |
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118 | log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread."); |
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119 | // the load and store are in the same thread. Now, we must test address. |
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120 | Tdcache_address_t load_addr = _load_queue [index_load ]._address; |
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121 | Tdcache_address_t store_addr = _store_queue[index_store]._address; |
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122 | |
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123 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr : %.8x.",load_addr ); |
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124 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr : %.8x.",store_addr); |
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125 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr & mask_address_msb : %.8x.",load_addr & _param->_mask_address_msb); |
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126 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb); |
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127 | // Test if the both address target the same word |
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128 | if ((load_addr & _param->_mask_address_msb) == |
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129 | (store_addr & _param->_mask_address_msb)) |
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130 | { |
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131 | log_printf(TRACE,Load_store_unit,FUNCTION," * address_msb is the same."); |
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132 | // all case - [] : store, () : load |
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133 | // (1) store_max >= load_max and store_min <= load_min ...[...(...)...]... Ok - inclusion in store |
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134 | // (2) store_min > load_max ...[...]...(...)... Ok - no conflit |
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135 | // (3) store_max < load_min ...(...)...[...]... Ok - no conflit |
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136 | // (4) store_max < load_max and store_min > load_min ...(...[...]...)... Ko - inclusion in load |
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137 | // (5) store_max >= load_max and store_min > load_min ...[...(...]...)... Ko - conflit |
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138 | // (6) store_max < load_max and store_min <= load_min ...(...[...)...]... Ko - conflit |
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139 | // but : |
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140 | // load in the cache is a word ! |
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141 | // the mask can be make when the load is commited. Also, the rdata content a full word. |
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142 | // the only case is (4) |
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143 | |
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144 | Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; |
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145 | Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; |
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146 | |
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147 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (init) : %.8x",load_data); |
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148 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (init) : %.8x",store_data); |
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149 | uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb); |
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150 | uint32_t store_num_byte_max = store_num_byte_min+(1<<memory_access(_store_queue[index_store]._operation)); |
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151 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); |
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152 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); |
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153 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); |
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154 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",_load_queue[index_load]._check_hit_byte); |
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155 | // The bypass is checked byte per byte |
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156 | for (uint32_t byte=store_num_byte_min; byte<store_num_byte_max; byte ++) |
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157 | { |
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158 | uint32_t mask = 1<<byte; |
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159 | uint32_t index = byte<<3; |
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160 | log_printf(TRACE,Load_store_unit,FUNCTION," * byte : %d",byte); |
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161 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %d",mask); |
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162 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
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163 | // Accept the bypass if they had not a previous bypass with an another store |
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164 | if ((_load_queue[index_load]._check_hit_byte&mask)==0) |
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165 | { |
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166 | log_printf(TRACE,Load_store_unit,FUNCTION," * bypass !!!"); |
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167 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_old : %.8x", load_data); |
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168 | load_data = insert<Tdcache_data_t>(load_data, store_data, index+8-1, index); |
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169 | _load_queue[index_load]._check_hit_byte |= mask; |
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170 | _load_queue[index_load]._check_hit = 1; |
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171 | change_state = true; |
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172 | |
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173 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : %.8x", load_data); |
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174 | } |
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175 | } |
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176 | |
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177 | _load_queue[index_load]._rdata = load_data; |
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178 | |
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179 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); |
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180 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",_load_queue[index_load]._check_hit_byte); |
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181 | |
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182 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); |
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183 | // The check is finish if all bit is set |
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184 | end_check = (_load_queue[index_load]._check_hit_byte == MASK_CHECK_BYTE_HIT); |
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185 | } |
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186 | } |
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187 | |
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188 | next = true; |
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189 | break; |
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190 | } |
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191 | case STORE_QUEUE_EMPTY : |
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192 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
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193 | { |
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194 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry"); |
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195 | break; |
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196 | } |
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197 | } |
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198 | } |
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199 | |
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200 | if (next) |
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201 | { |
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202 | log_printf(TRACE,Load_store_unit,FUNCTION," * next"); |
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203 | // if (_load_queue[index_load]._store_queue_ptr_write == 0) |
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204 | // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; |
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205 | // else |
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206 | // _load_queue[index_load]._store_queue_ptr_write --; |
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207 | _load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease |
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208 | |
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209 | // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ" |
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210 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
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211 | { |
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212 | end_check = true; |
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213 | change_state = true; |
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214 | } |
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215 | } |
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216 | |
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217 | if (change_state) |
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218 | { |
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219 | log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); |
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220 | |
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221 | switch (_load_queue[index_load]._state) |
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222 | { |
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223 | case LOAD_QUEUE_WAIT_CHECK : _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; break; |
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224 | case LOAD_QUEUE_COMMIT_CHECK : |
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225 | { |
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226 | if (end_check) |
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227 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
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228 | else |
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229 | _load_queue[index_load]._state = LOAD_QUEUE_CHECK; |
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230 | break; |
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231 | } |
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232 | case LOAD_QUEUE_CHECK : |
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233 | { |
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234 | if (end_check) |
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235 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
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236 | // check find a bypass. A speculative load have been committed : report a speculation miss. |
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237 | if (_load_queue[index_load]._check_hit != 0) |
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238 | { |
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239 | _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
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240 | _load_queue[index_load]._write_rd = 1; // write the good result |
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241 | } |
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242 | |
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243 | break; |
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244 | } |
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245 | default : break; |
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246 | } |
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247 | log_printf(TRACE,Load_store_unit,FUNCTION," * new state : %d",_load_queue[index_load]._state); |
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248 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); |
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249 | } |
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250 | } |
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251 | // else : don't use a port |
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252 | } |
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253 | |
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254 | //================================================================ |
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255 | // Interface "MEMORY_IN" |
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256 | //================================================================ |
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257 | |
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258 | if ((PORT_READ(in_MEMORY_IN_VAL) == 1) and |
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259 | ( internal_MEMORY_IN_ACK == 1)) |
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260 | { |
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261 | // Test operation : |
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262 | //~~~~~~~~~~~~~~~~~ |
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263 | // store in store_queue |
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264 | // load in speculation_access_queue |
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265 | // others in speculation_access_queue |
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266 | |
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267 | Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION); |
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268 | Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT) + |
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269 | PORT_READ(in_MEMORY_IN_DATA_RA )); |
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270 | bool exception_alignement = (mask_memory_access(operation) & address) != 0; |
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271 | |
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272 | if (is_operation_memory_store(operation) == true) |
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273 | { |
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274 | // ======================= |
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275 | // ===== STORE_QUEUE ===== |
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276 | // ======================= |
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277 | // There a two store request type : |
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278 | // - first is operation with address and data |
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279 | // - second is the information of re order buffer : the store become not speculative and can access at the data cache |
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280 | |
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281 | log_printf(TRACE,Load_store_unit,FUNCTION,"store_queue"); |
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282 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
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283 | |
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284 | // Write pointer is define in rename stage : |
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285 | Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); |
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286 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
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287 | |
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288 | // Need read : state and exception. |
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289 | Tstore_queue_state_t old_state = _store_queue [index]._state; |
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290 | Tstore_queue_state_t new_state = old_state; |
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291 | bool update_info = false; |
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292 | |
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293 | Texception_t old_exception = _store_queue [index]._exception; |
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294 | Texception_t new_exception = old_exception; |
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295 | |
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296 | // Compute next state |
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297 | switch (old_state) |
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298 | { |
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299 | case STORE_QUEUE_EMPTY : |
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300 | { |
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301 | if (is_operation_memory_store_head(operation) == true) |
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302 | { |
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303 | new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE; |
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304 | |
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305 | // test if is a speculation |
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306 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
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307 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
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308 | else |
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309 | new_exception = EXCEPTION_MEMORY_NONE; |
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310 | } |
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311 | else |
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312 | { |
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313 | new_state = STORE_QUEUE_VALID_SPECULATIVE; |
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314 | |
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315 | // Test if have an exception |
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316 | if (exception_alignement == true) |
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317 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
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318 | else |
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319 | new_exception = EXCEPTION_MEMORY_NONE; |
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320 | |
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321 | update_info = true; |
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322 | } |
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323 | break; |
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324 | } |
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325 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
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326 | { |
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327 | #ifdef DEBUG_TEST |
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328 | if (is_operation_memory_store_head(operation) == true) |
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329 | throw ErrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head.")); |
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330 | #endif |
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331 | // Test if have a new exception (priority : miss_speculation) |
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332 | if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE)) |
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333 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
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334 | |
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335 | if (new_exception != EXCEPTION_MEMORY_NONE) |
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336 | new_state = STORE_QUEUE_COMMIT; |
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337 | else |
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338 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
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339 | |
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340 | update_info = true; |
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341 | break; |
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342 | } |
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343 | case STORE_QUEUE_VALID_SPECULATIVE : |
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344 | { |
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345 | #ifdef DEBUG_TEST |
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346 | if (is_operation_memory_store_head(operation) == false) |
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347 | throw ErrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head.")); |
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348 | #endif |
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349 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
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350 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary |
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351 | |
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352 | if (new_exception != EXCEPTION_MEMORY_NONE) |
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353 | new_state = STORE_QUEUE_COMMIT; |
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354 | else |
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355 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
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356 | |
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357 | break; |
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358 | } |
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359 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
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360 | case STORE_QUEUE_COMMIT : |
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361 | { |
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362 | throw ErrorMorpheo("<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation"); |
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363 | } |
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364 | } |
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365 | |
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366 | _store_queue [index]._state = new_state; |
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367 | _store_queue [index]._exception = new_exception; |
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368 | |
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369 | if (update_info == true) |
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370 | { |
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371 | log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); |
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372 | |
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373 | _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID); |
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374 | _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID); |
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375 | _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID); |
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376 | _store_queue [index]._packet_id = (not _param->_have_port_packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID ); |
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377 | _store_queue [index]._operation = operation; |
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378 | _store_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); |
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379 | _store_queue [index]._address = address; |
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380 | |
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381 | // reordering data |
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382 | _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB), memory_size(operation), 0); |
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383 | // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD ); |
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384 | } |
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385 | } |
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386 | else |
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387 | { |
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388 | // ==================================== |
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389 | // ===== SPECULATIVE_ACCESS_QUEUE ===== |
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390 | // ==================================== |
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391 | |
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392 | // In speculative access queue, they are many type's request |
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393 | log_printf(TRACE,Load_store_unit,FUNCTION,"speculative_access_queue"); |
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394 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
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395 | |
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396 | // Write in reservation station |
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397 | uint32_t index = _speculative_access_queue_control->push(); |
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398 | |
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399 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); |
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400 | |
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401 | Texception_t exception; |
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402 | |
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403 | if (exception_alignement == true) |
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404 | exception = EXCEPTION_MEMORY_ALIGNMENT; |
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405 | else |
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406 | exception = EXCEPTION_MEMORY_NONE; |
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407 | |
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408 | // if exception, don't access at the cache |
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409 | // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) |
---|
410 | _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; |
---|
411 | _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID); |
---|
412 | _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID); |
---|
413 | _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID); |
---|
414 | _speculative_access_queue [index]._packet_id = (not _param->_have_port_packet_id )?0:PORT_READ(in_MEMORY_IN_PACKET_ID); |
---|
415 | |
---|
416 | _speculative_access_queue [index]._operation = operation; |
---|
417 | _speculative_access_queue [index]._load_queue_ptr_write = PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE); |
---|
418 | _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE); |
---|
419 | _speculative_access_queue [index]._address = address; |
---|
420 | // NOTE : is operation is a load, then they are a result and must write in the register file |
---|
421 | _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); |
---|
422 | _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD ); |
---|
423 | |
---|
424 | _speculative_access_queue [index]._exception = exception; |
---|
425 | |
---|
426 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
---|
427 | } |
---|
428 | } |
---|
429 | |
---|
430 | //================================================================ |
---|
431 | // Interface "MEMORY_OUT" |
---|
432 | //================================================================ |
---|
433 | |
---|
434 | if (( internal_MEMORY_OUT_VAL == 1) and |
---|
435 | (PORT_READ(in_MEMORY_OUT_ACK) == 1)) |
---|
436 | { |
---|
437 | log_printf(TRACE,Load_store_unit,FUNCTION,"MEMORY_OUT transaction"); |
---|
438 | |
---|
439 | switch (internal_MEMORY_OUT_SELECT_QUEUE) |
---|
440 | { |
---|
441 | case SELECT_STORE_QUEUE : |
---|
442 | { |
---|
443 | // ======================= |
---|
444 | // ===== STORE_QUEUE ===== |
---|
445 | // ======================= |
---|
446 | |
---|
447 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); |
---|
448 | |
---|
449 | // Entry flush and increase the read pointer |
---|
450 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; |
---|
451 | |
---|
452 | reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; |
---|
453 | |
---|
454 | break; |
---|
455 | } |
---|
456 | case SELECT_LOAD_QUEUE : |
---|
457 | { |
---|
458 | // ====================== |
---|
459 | // ===== LOAD_QUEUE ===== |
---|
460 | // ====================== |
---|
461 | |
---|
462 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); |
---|
463 | |
---|
464 | // Entry flush and increase the read pointer |
---|
465 | |
---|
466 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY; |
---|
467 | |
---|
468 | // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; |
---|
469 | |
---|
470 | break; |
---|
471 | } |
---|
472 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
---|
473 | { |
---|
474 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); |
---|
475 | |
---|
476 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; |
---|
477 | // NOTE : a speculative load write in the register file. |
---|
478 | // if the speculation is a miss, write_rd is re set at 1. |
---|
479 | _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; |
---|
480 | break; |
---|
481 | } |
---|
482 | |
---|
483 | break; |
---|
484 | } |
---|
485 | } |
---|
486 | |
---|
487 | //================================================================ |
---|
488 | // Interface "DCACHE_REQ" |
---|
489 | //================================================================ |
---|
490 | bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE); |
---|
491 | |
---|
492 | if (( internal_DCACHE_REQ_VAL == 1) and |
---|
493 | (PORT_READ(in_DCACHE_REQ_ACK) == 1)) |
---|
494 | { |
---|
495 | log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_REQ"); |
---|
496 | |
---|
497 | switch (internal_DCACHE_REQ_SELECT_QUEUE) |
---|
498 | { |
---|
499 | case SELECT_STORE_QUEUE : |
---|
500 | { |
---|
501 | // ======================= |
---|
502 | // ===== STORE_QUEUE ===== |
---|
503 | // ======================= |
---|
504 | |
---|
505 | // Entry flush and increase the read pointer |
---|
506 | |
---|
507 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT; |
---|
508 | |
---|
509 | break; |
---|
510 | } |
---|
511 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
---|
512 | { |
---|
513 | // ========================================= |
---|
514 | // ===== SELECT_LOAD_QUEUE_SPECULATIVE ===== |
---|
515 | // ========================================= |
---|
516 | |
---|
517 | load_queue_push = true; |
---|
518 | break; |
---|
519 | } |
---|
520 | case SELECT_LOAD_QUEUE : |
---|
521 | { |
---|
522 | throw ErrorMorpheo(_("Invalid selection")); |
---|
523 | break; |
---|
524 | } |
---|
525 | |
---|
526 | break; |
---|
527 | } |
---|
528 | } |
---|
529 | |
---|
530 | if (load_queue_push) |
---|
531 | { |
---|
532 | Tlsq_ptr_t ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write; |
---|
533 | Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation; |
---|
534 | Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception; |
---|
535 | bool have_exception = (exception != EXCEPTION_MEMORY_NONE); |
---|
536 | |
---|
537 | |
---|
538 | if (have_exception) |
---|
539 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
540 | else |
---|
541 | { |
---|
542 | if (have_dcache_rsp(operation)) |
---|
543 | { |
---|
544 | // load and synchronisation |
---|
545 | if (must_check(operation)) |
---|
546 | { |
---|
547 | // load |
---|
548 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK; |
---|
549 | } |
---|
550 | else |
---|
551 | { |
---|
552 | // synchronisation |
---|
553 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT; |
---|
554 | } |
---|
555 | } |
---|
556 | else |
---|
557 | { |
---|
558 | // lock, prefecth, flush and invalidate |
---|
559 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
560 | } |
---|
561 | } |
---|
562 | |
---|
563 | Tdcache_address_t address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address; |
---|
564 | Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); |
---|
565 | Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+memory_access(operation)+1,address_lsb); |
---|
566 | _load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id ; |
---|
567 | _load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id ; |
---|
568 | _load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id ; |
---|
569 | _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id ; |
---|
570 | _load_queue [ptr_write]._operation = operation; |
---|
571 | _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; |
---|
572 | _load_queue [ptr_write]._address = address; |
---|
573 | _load_queue [ptr_write]._check_hit_byte = check_hit_byte; |
---|
574 | _load_queue [ptr_write]._check_hit = 0; |
---|
575 | _load_queue [ptr_write]._shift = address<<3; |
---|
576 | _load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation); |
---|
577 | _load_queue [ptr_write]._access_size = memory_size(operation); |
---|
578 | // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. |
---|
579 | _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; |
---|
580 | |
---|
581 | _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; |
---|
582 | _load_queue [ptr_write]._exception = exception; |
---|
583 | _load_queue [ptr_write]._rdata = address; // to the exception |
---|
584 | |
---|
585 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); |
---|
586 | log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); |
---|
587 | |
---|
588 | _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
---|
589 | |
---|
590 | _speculative_access_queue_control->pop(); |
---|
591 | } |
---|
592 | |
---|
593 | //================================================================ |
---|
594 | // Interface "DCACHE_RSP" |
---|
595 | //================================================================ |
---|
596 | if ((PORT_READ(in_DCACHE_RSP_VAL)== 1) and |
---|
597 | ( internal_DCACHE_RSP_ACK == 1)) |
---|
598 | { |
---|
599 | log_printf(TRACE,Load_store_unit,FUNCTION,"DCACHE_RSP"); |
---|
600 | |
---|
601 | // don't use context_id : because there are one queue for all thread |
---|
602 | //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID); |
---|
603 | Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID ); |
---|
604 | Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA ); |
---|
605 | Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR ); |
---|
606 | |
---|
607 | log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d", packet_id); |
---|
608 | |
---|
609 | if (DCACHE_RSP_IS_LOAD(packet_id) == 1) |
---|
610 | { |
---|
611 | packet_id >>= 1; |
---|
612 | |
---|
613 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id); |
---|
614 | |
---|
615 | |
---|
616 | #ifdef DEBUG_TEST |
---|
617 | if (not have_dcache_rsp(_load_queue [packet_id]._operation)) |
---|
618 | throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons.")); |
---|
619 | #endif |
---|
620 | |
---|
621 | |
---|
622 | if (error != DCACHE_ERROR_NONE) |
---|
623 | { |
---|
624 | log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); |
---|
625 | |
---|
626 | _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; |
---|
627 | _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT; |
---|
628 | } |
---|
629 | else |
---|
630 | { |
---|
631 | log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); |
---|
632 | log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %d.",_load_queue [packet_id]._state); |
---|
633 | |
---|
634 | // FIXME : convention : if bus error, the cache return the fautive address ! |
---|
635 | // But, the load's address is aligned ! |
---|
636 | _load_queue [packet_id]._rdata = rdata; |
---|
637 | |
---|
638 | switch (_load_queue [packet_id]._state) |
---|
639 | { |
---|
640 | case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break; |
---|
641 | case LOAD_QUEUE_WAIT : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT ; break; |
---|
642 | default : throw ErrorMorpheo(_("Illegal state (dcache_rsp).")); break; |
---|
643 | } |
---|
644 | } |
---|
645 | } |
---|
646 | else |
---|
647 | { |
---|
648 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); |
---|
649 | |
---|
650 | // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! |
---|
651 | throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)")); |
---|
652 | } |
---|
653 | |
---|
654 | } |
---|
655 | |
---|
656 | // this register is to manage the priority of check -> Round robin |
---|
657 | reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue; |
---|
658 | |
---|
659 | |
---|
660 | #if DEBUG>=DEBUG_TRACE |
---|
661 | // ***** dump store queue |
---|
662 | std::cout << "Dump STORE_QUEUE :" << std::endl |
---|
663 | << "ptr_read : " << toString(static_cast<uint32_t>(reg_STORE_QUEUE_PTR_READ)) << std::endl; |
---|
664 | |
---|
665 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
666 | { |
---|
667 | uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; |
---|
668 | std::cout << "{" << j << "}" << std::endl |
---|
669 | << _store_queue[j] << std::endl; |
---|
670 | } |
---|
671 | |
---|
672 | // ***** dump speculative_access queue |
---|
673 | std::cout << "Dump SPECULATIVE_ACCESS_QUEUE :" << std::endl; |
---|
674 | |
---|
675 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
676 | { |
---|
677 | uint32_t j = (*_speculative_access_queue_control)[i]; |
---|
678 | std::cout << "{" << j << "}" << std::endl |
---|
679 | << _speculative_access_queue[j] << std::endl; |
---|
680 | } |
---|
681 | |
---|
682 | // ***** dump load queue |
---|
683 | std::cout << "Dump LOAD_QUEUE :" << std::endl |
---|
684 | << "ptr_read_check_priority : " << toString(static_cast<uint32_t>(reg_LOAD_QUEUE_CHECK_PRIORITY)) << std::endl; |
---|
685 | |
---|
686 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
687 | { |
---|
688 | uint32_t j = i; |
---|
689 | std::cout << "{" << j << "}" << std::endl |
---|
690 | << _load_queue[j] << std::endl; |
---|
691 | } |
---|
692 | |
---|
693 | #endif |
---|
694 | |
---|
695 | #ifdef STATISTICS |
---|
696 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
697 | if (_store_queue[i]._state != STORE_QUEUE_EMPTY) |
---|
698 | (*_stat_use_store_queue) ++; |
---|
699 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
700 | if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) |
---|
701 | (*_stat_use_speculative_access_queue) ++; |
---|
702 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
703 | if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) |
---|
704 | (*_stat_use_load_queue) ++; |
---|
705 | #endif |
---|
706 | } |
---|
707 | |
---|
708 | log_printf(FUNC,Load_store_unit,FUNCTION,"End"); |
---|
709 | }; |
---|
710 | |
---|
711 | }; // end namespace load_store_unit |
---|
712 | }; // end namespace execute_unit |
---|
713 | }; // end namespace multi_execute_unit |
---|
714 | }; // end namespace execute_loop |
---|
715 | }; // end namespace multi_execute_loop |
---|
716 | }; // end namespace core |
---|
717 | |
---|
718 | }; // end namespace behavioural |
---|
719 | }; // end namespace morpheo |
---|
720 | #endif |
---|