1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Load_store_unit_function_speculative_load_commit_transition.cpp 106 2009-02-09 22:55:26Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_execute_loop { |
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15 | namespace execute_loop { |
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16 | namespace multi_execute_unit { |
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17 | namespace execute_unit { |
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18 | namespace load_store_unit { |
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19 | |
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20 | template <typename T> |
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21 | T swapBytes (T data, uint32_t size_data, uint32_t size_access) |
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22 | { |
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23 | uint64_t x = static_cast<uint64_t>(data); |
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24 | |
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25 | // switch (size_data) |
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26 | // { |
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27 | // case 2 : // 16 bits |
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28 | // { |
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29 | // switch (size_access) |
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30 | // { |
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31 | // case 2 : |
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32 | // { |
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33 | // x = ((((x>> 8)&0xff) << 0) | |
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34 | // (((x>> 0)&0xff) << 8) ); |
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35 | // break; |
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36 | // } |
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37 | // default : |
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38 | // { |
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39 | // break; |
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40 | // } |
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41 | // } |
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42 | // break; |
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43 | // } |
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44 | // case 4 : // 32 bits |
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45 | // { |
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46 | // switch (size_access) |
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47 | // { |
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48 | // case 2 : |
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49 | // { |
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50 | // x = ((((x>> 8)&0xff) << 0) | |
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51 | // (((x>> 0)&0xff) << 8) | |
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52 | // (((x>>24)&0xff) << 16) | |
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53 | // (((x>>16)&0xff) << 24) ); |
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54 | // break; |
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55 | // } |
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56 | // case 4 : |
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57 | // { |
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58 | // x = ((((x>>24)&0xff) << 0) | |
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59 | // (((x>>16)&0xff) << 8) | |
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60 | // (((x>> 8)&0xff) << 16) | |
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61 | // (((x>> 0)&0xff) << 24) ); |
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62 | // break; |
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63 | // } |
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64 | // default : |
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65 | // { |
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66 | // break; |
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67 | // } |
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68 | // } |
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69 | // break; |
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70 | // } |
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71 | // case 8 : // 64 bits |
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72 | // { |
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73 | // switch (size_access) |
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74 | // { |
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75 | // case 2 : |
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76 | // { |
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77 | // x = ((((x>> 8)&0xff) << 0) | |
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78 | // (((x>> 0)&0xff) << 8) | |
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79 | // (((x>>24)&0xff) << 16) | |
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80 | // (((x>>16)&0xff) << 24) | |
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81 | // (((x>>40)&0xff) << 32) | |
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82 | // (((x>>32)&0xff) << 40) | |
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83 | // (((x>>56)&0xff) << 48) | |
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84 | // (((x>>48)&0xff) << 56) ); |
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85 | // break; |
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86 | // } |
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87 | // case 4 : |
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88 | // { |
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89 | // x = ((((x>>24)&0xff) << 0) | |
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90 | // (((x>>16)&0xff) << 8) | |
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91 | // (((x>> 8)&0xff) << 16) | |
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92 | // (((x>> 0)&0xff) << 24) | |
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93 | // (((x>>56)&0xff) << 32) | |
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94 | // (((x>>48)&0xff) << 40) | |
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95 | // (((x>>40)&0xff) << 48) | |
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96 | // (((x>>32)&0xff) << 56) ); |
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97 | // break; |
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98 | // } |
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99 | // case 8 : |
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100 | // { |
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101 | // x = ((((x>>56)&0xff) << 0) | |
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102 | // (((x>>48)&0xff) << 8) | |
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103 | // (((x>>40)&0xff) << 16) | |
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104 | // (((x>>32)&0xff) << 24) | |
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105 | // (((x>>24)&0xff) << 32) | |
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106 | // (((x>>16)&0xff) << 40) | |
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107 | // (((x>> 8)&0xff) << 48) | |
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108 | // (((x>> 0)&0xff) << 56) ); |
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109 | // break; |
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110 | // } |
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111 | // default : |
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112 | // { |
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113 | // break; |
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114 | // } |
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115 | // } |
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116 | // break; |
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117 | // } |
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118 | // default : |
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119 | // { |
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120 | // break; |
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121 | // } |
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122 | // } |
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123 | |
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124 | |
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125 | uint64_t y=0; |
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126 | |
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127 | for (uint32_t i=0; i<size_data; i+=size_access) |
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128 | { |
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129 | uint32_t offset = i<<3; |
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130 | |
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131 | switch (size_access) |
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132 | { |
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133 | case 1 : |
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134 | { |
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135 | y = x; |
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136 | break; |
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137 | } |
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138 | case 2 : |
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139 | { |
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140 | y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) | |
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141 | (((x>>( 0+offset))&0xff) << ( 8+offset)) ); |
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142 | break; |
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143 | } |
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144 | case 4 : |
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145 | { |
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146 | y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) | |
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147 | (((x>>(16+offset))&0xff) << ( 8+offset)) | |
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148 | (((x>>( 8+offset))&0xff) << (16+offset)) | |
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149 | (((x>>( 0+offset))&0xff) << (24+offset)) ); |
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150 | break; |
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151 | } |
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152 | case 8 : |
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153 | { |
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154 | y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) | |
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155 | (((x>>(48+offset))&0xff) << ( 8+offset)) | |
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156 | (((x>>(40+offset))&0xff) << (16+offset)) | |
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157 | (((x>>(32+offset))&0xff) << (24+offset)) | |
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158 | (((x>>(24+offset))&0xff) << (32+offset)) | |
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159 | (((x>>(16+offset))&0xff) << (40+offset)) | |
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160 | (((x>>( 8+offset))&0xff) << (48+offset)) | |
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161 | (((x>>( 0+offset))&0xff) << (56+offset)) ); |
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162 | break; |
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163 | } |
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164 | default : |
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165 | { |
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166 | break; |
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167 | } |
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168 | } |
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169 | } |
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170 | |
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171 | return static_cast<T>(y); |
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172 | } |
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173 | |
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174 | template <typename T> |
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175 | T swapBits (T data, uint32_t size_data, uint32_t size_access) |
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176 | { |
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177 | uint8_t x = static_cast<uint8_t>(data); |
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178 | |
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179 | uint8_t y=0; |
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180 | |
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181 | for (uint32_t i=0; i<size_data; i+=size_access) |
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182 | { |
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183 | uint32_t offset = i; |
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184 | |
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185 | switch (size_access) |
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186 | { |
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187 | case 1 : |
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188 | { |
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189 | y = x; |
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190 | break; |
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191 | } |
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192 | case 2 : |
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193 | { |
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194 | y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) | |
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195 | (((x>>( 0+offset))&0x1) << ( 1+offset)) ); |
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196 | break; |
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197 | } |
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198 | case 4 : |
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199 | { |
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200 | y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) | |
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201 | (((x>>( 2+offset))&0x1) << ( 1+offset)) | |
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202 | (((x>>( 1+offset))&0x1) << ( 2+offset)) | |
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203 | (((x>>( 0+offset))&0x1) << ( 3+offset)) ); |
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204 | break; |
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205 | } |
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206 | case 8 : |
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207 | { |
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208 | y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) | |
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209 | (((x>>( 6+offset))&0x1) << ( 1+offset)) | |
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210 | (((x>>( 5+offset))&0x1) << ( 2+offset)) | |
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211 | (((x>>( 4+offset))&0x1) << ( 3+offset)) | |
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212 | (((x>>( 3+offset))&0x1) << ( 4+offset)) | |
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213 | (((x>>( 2+offset))&0x1) << ( 5+offset)) | |
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214 | (((x>>( 1+offset))&0x1) << ( 6+offset)) | |
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215 | (((x>>( 0+offset))&0x1) << ( 7+offset)) ); |
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216 | break; |
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217 | } |
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218 | default : |
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219 | { |
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220 | break; |
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221 | } |
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222 | } |
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223 | } |
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224 | |
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225 | return static_cast<T>(y); |
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226 | } |
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227 | |
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228 | #undef FUNCTION |
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229 | #define FUNCTION "Load_store_unit::function_speculative_load_commit_transition" |
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230 | void Load_store_unit::function_speculative_load_commit_transition (void) |
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231 | { |
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232 | log_begin(Load_store_unit,FUNCTION); |
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233 | log_function(Load_store_unit,FUNCTION,_name.c_str()); |
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234 | |
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235 | if (PORT_READ(in_NRESET) == 0) |
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236 | { |
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237 | // Reset : clear all queue |
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238 | _speculative_access_queue_control->clear(); |
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239 | |
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240 | reg_STORE_QUEUE_PTR_READ = 0; |
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241 | reg_LOAD_QUEUE_CHECK_PRIORITY = 0; |
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242 | |
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243 | for (uint32_t i=0; i< _param->_size_store_queue ; i++) |
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244 | _store_queue [i]._state = STORE_QUEUE_EMPTY; |
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245 | |
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246 | for (uint32_t i=0; i< _param->_size_load_queue ; i++) |
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247 | _load_queue [i]._state = LOAD_QUEUE_EMPTY; |
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248 | |
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249 | for (uint32_t i=0; i< _param->_size_speculative_access_queue; i++) |
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250 | _speculative_access_queue [i]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
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251 | } |
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252 | else |
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253 | { |
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254 | //================================================================ |
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255 | // Interface "PORT_CHECK" |
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256 | //================================================================ |
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257 | |
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258 | // Plusieurs moyens de faire la verification de dépendance entre les loads et les stores. |
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259 | // 1) un load ne peut vérifier qu'un store par cycle. Dans ce cas port_check <= size_load_queue |
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260 | // 2) un load tente de vérifier le maximum de store par cycle. Dans ce cas ce n'est pas du pointeur d'écriture qu'il lui faut mais un vecteur de bit indiquant quel store à déjà été testé. De plus il faut un bit indiquant qu'il y a un match mais que ce n'est pas forcément le premier. |
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261 | |
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262 | // solution 1) |
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263 | log_printf(TRACE,Load_store_unit,FUNCTION," * CHECK"); |
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264 | for (uint32_t i=0, nb_check=0; (nb_check<_param->_nb_port_check) and (i<_param->_size_load_queue); i++) |
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265 | { |
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266 | // Get an index from load queue |
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267 | uint32_t index_load = (i + reg_LOAD_QUEUE_CHECK_PRIORITY)%_param->_size_load_queue; |
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268 | |
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269 | // Test if this load must ckecked store queue |
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270 | if (((_load_queue[index_load]._state == LOAD_QUEUE_WAIT_CHECK) or |
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271 | (_load_queue[index_load]._state == LOAD_QUEUE_COMMIT_CHECK) or |
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272 | (_load_queue[index_load]._state == LOAD_QUEUE_CHECK)) and |
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273 | is_operation_memory_load(_load_queue[index_load]._operation)) |
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274 | { |
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275 | log_printf(TRACE,Load_store_unit,FUNCTION," * Find a load : %d",index_load); |
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276 | |
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277 | nb_check++; // use one port |
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278 | |
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279 | // find a entry that it need a check |
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280 | Tlsq_ptr_t index_store = _load_queue[index_load]._store_queue_ptr_write; |
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281 | // Init variable |
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282 | bool end_check = false; |
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283 | bool change_state = false; |
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284 | bool next = false; |
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285 | |
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286 | // At the first store queue empty, stop check. |
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287 | // Explication : |
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288 | // * rename logic keep a empty case in the store queue (also size_store_queue > 1) |
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289 | // * when a store is out of store queue, also it was in head of re order buffer. Also, they are none previous load. |
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290 | |
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291 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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292 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); |
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293 | |
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294 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
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295 | { |
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296 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store == reg_STORE_QUEUE_PTR_READ"); |
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297 | end_check = true; |
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298 | change_state = true; |
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299 | } |
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300 | else |
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301 | { |
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302 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store != reg_STORE_QUEUE_PTR_READ"); |
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303 | |
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304 | index_store = (index_store-1)%(_param->_size_store_queue); // store_queue_ptr_write target the next slot to write, also the slot is not significatif when the load is renaming |
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305 | |
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306 | log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); |
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307 | |
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308 | // switch on store_queue state |
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309 | switch (_store_queue[index_store]._state) |
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310 | { |
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311 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
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312 | case STORE_QUEUE_COMMIT : |
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313 | case STORE_QUEUE_VALID_SPECULATIVE : |
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314 | { |
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315 | |
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316 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have a valid entry"); |
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317 | |
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318 | // TODO : MMU - nous considérons que les adresses sont physique |
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319 | bool test_thread_id = true; |
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320 | |
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321 | // Test thread id |
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322 | if (_param->_have_port_context_id) |
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323 | test_thread_id &= (_load_queue[index_load]._context_id == _store_queue[index_store]._context_id); |
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324 | if (_param->_have_port_front_end_id) |
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325 | test_thread_id &= (_load_queue[index_load]._front_end_id == _store_queue[index_store]._front_end_id); |
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326 | if (_param->_have_port_ooo_engine_id) |
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327 | test_thread_id &= (_load_queue[index_load]._ooo_engine_id == _store_queue[index_store]._ooo_engine_id); |
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328 | |
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329 | if (test_thread_id) |
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330 | { |
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331 | // the load and store are in the same thread. Now, we must test address. |
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332 | |
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333 | log_printf(TRACE,Load_store_unit,FUNCTION," * load and store is the same thread."); |
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334 | Tdcache_address_t load_addr = _load_queue [index_load ]._address; |
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335 | Tdcache_address_t store_addr = _store_queue[index_store]._address; |
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336 | |
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337 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr : %.8x.",load_addr ); |
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338 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr : %.8x.",store_addr); |
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339 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_addr & mask_address_msb : %.8x.",load_addr & _param->_mask_address_msb); |
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340 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_addr & mask_address_msb : %.8x.",store_addr & _param->_mask_address_msb); |
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341 | // Test if the both address target the same "word" |
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342 | if ((load_addr & _param->_mask_address_msb) == |
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343 | (store_addr & _param->_mask_address_msb)) |
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344 | { |
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345 | log_printf(TRACE,Load_store_unit,FUNCTION," * address_msb is the same."); |
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346 | // all case - [] : store, () : load |
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347 | // (1) store_max >= load_max and store_min <= load_min ...[...(...)...]... Ok - inclusion in store |
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348 | // (2) store_min > load_max ...[...]...(...)... Ok - no conflit |
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349 | // (3) store_max < load_min ...(...)...[...]... Ok - no conflit |
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350 | // (4) store_max < load_max and store_min > load_min ...(...[...]...)... Ko - inclusion in load |
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351 | // (5) store_max >= load_max and store_min > load_min ...[...(...]...)... Ko - conflit |
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352 | // (6) store_max < load_max and store_min <= load_min ...(...[...)...]... Ko - conflit |
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353 | // but : |
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354 | // load in the cache is a word ! |
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355 | // the mask can be make when the load is commited. Also, the rdata content a full word. |
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356 | // the only case is (4) |
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357 | |
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358 | // Read data |
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359 | bool is_big_endian = true; |
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360 | |
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361 | Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; |
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362 | Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; |
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363 | Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte; |
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364 | Tcontrol_t check_hit = _load_queue [index_load ]._check_hit; |
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365 | uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3; |
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366 | uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3; |
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367 | |
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368 | log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); |
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369 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data); |
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370 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data); |
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371 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); |
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372 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit); |
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373 | |
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374 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access ); |
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375 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access); |
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376 | |
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377 | if (is_big_endian) |
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378 | { |
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379 | // swap in little endian |
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380 | load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); |
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381 | store_data = swapBytes<Tgeneral_data_t >(store_data , _param->_size_general_data>>3,store_size_access); |
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382 | check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); |
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383 | |
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384 | |
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385 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data); |
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386 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data); |
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387 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte); |
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388 | } |
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389 | |
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390 | uint32_t store_nb_byte = (1<<memory_access(_store_queue[index_store]._operation)); |
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391 | |
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392 | // Take interval to the store |
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393 | uint32_t store_num_byte_min = (store_addr & _param->_mask_address_lsb); |
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394 | uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte; |
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395 | |
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396 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); |
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397 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); |
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398 | |
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399 | // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load]._operation)); |
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400 | |
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401 | // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb); |
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402 | // uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte; |
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403 | |
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404 | // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min); |
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405 | // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max); |
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406 | |
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407 | // for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++) |
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408 | // { |
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409 | // // Make a mask |
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410 | // uint32_t num_store_byte = num_load_byte; |
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411 | |
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412 | |
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413 | |
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414 | // The bypass is checked byte per byte |
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415 | // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed. |
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416 | for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++) |
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417 | { |
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418 | // Make a mask |
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419 | uint32_t num_load_byte = num_store_byte; |
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420 | |
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421 | // if (is_big_endian) |
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422 | // { |
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423 | // // sd 0 : 0 1 2 3 4 5 6 7 |
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424 | // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 |
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425 | // // lw 0 : 0 1 2 3 >> 0 -4 |
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426 | // // lw 4 : 4 5 6 7 >> 32 +4 |
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427 | // // lh 0 : 0 1 >> 0 -6 |
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428 | // // lh 2 : 2 3 >> 16 -2 |
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429 | // // lh 4 : 4 5 >> 32 +2 |
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430 | // // lh 6 : 6 7 >> 48 +6 |
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431 | // // lb 0 : 0 >> 0 -7 |
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432 | // // lb 1 : 1 >> 8 -5 |
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433 | // // lb 2 : 2 >> 16 -3 |
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434 | // // lb 3 : 3 >> 24 -1 |
---|
435 | // // lb 4 : 4 >> 32 +1 |
---|
436 | // // lb 5 : 5 >> 40 +3 |
---|
437 | // // lb 6 : 6 >> 48 +5 |
---|
438 | // // lb 7 : 7 >> 56 +7 |
---|
439 | |
---|
440 | // // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) |
---|
441 | |
---|
442 | // // store duplicate = all store access can be see as full size_data store |
---|
443 | // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); |
---|
444 | |
---|
445 | // // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); |
---|
446 | |
---|
447 | // // num_load_byte =num_store_byte+diff; |
---|
448 | |
---|
449 | // // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); |
---|
450 | // // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff); |
---|
451 | |
---|
452 | |
---|
453 | // num_load_byte = num_store_byte; |
---|
454 | // } |
---|
455 | // else |
---|
456 | // { |
---|
457 | // // sd 0 : 0 1 2 3 4 5 6 7 |
---|
458 | // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 |
---|
459 | // // lw 0 : 4 5 6 7 >> 0 |
---|
460 | // // lw 4 : 0 1 2 3 >> 32 |
---|
461 | // // lh 0 : 6 7 >> 0 |
---|
462 | // // lh 2 : 4 5 >> 16 |
---|
463 | // // lh 4 : 2 3 >> 32 |
---|
464 | // // lh 6 : 0 1 >> 48 |
---|
465 | // // lb 0 : 7 >> 0 |
---|
466 | // // lb 1 : 6 >> 8 |
---|
467 | // // lb 2 : 5 >> 16 |
---|
468 | // // lb 3 : 4 >> 24 |
---|
469 | // // lb 4 : 3 >> 32 |
---|
470 | // // lb 5 : 2 >> 40 |
---|
471 | // // lb 6 : 1 >> 48 |
---|
472 | // // lb 7 : 0 >> 56 |
---|
473 | |
---|
474 | // num_load_byte = num_store_byte; |
---|
475 | // } |
---|
476 | |
---|
477 | uint32_t mask = 1<<num_load_byte; |
---|
478 | |
---|
479 | log_printf(TRACE,Load_store_unit,FUNCTION," * num_store_byte : %d",num_store_byte); |
---|
480 | log_printf(TRACE,Load_store_unit,FUNCTION," * num_load_byte : %d",num_load_byte); |
---|
481 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask : %d",mask); |
---|
482 | |
---|
483 | // Accept the bypass if : |
---|
484 | // * they have not a previous bypass with an another store |
---|
485 | // * it's a valid request of load |
---|
486 | if ((check_hit_byte&mask)==0) |
---|
487 | { |
---|
488 | // Note : Store is duplicate = all store access can be see as full size_data store |
---|
489 | |
---|
490 | uint32_t num_store_bit_min = num_store_byte<<3; //*8 |
---|
491 | // uint32_t num_store_bit_max = num_store_bit_min+8-1; |
---|
492 | uint32_t num_load_bit_min = num_load_byte <<3; //*8 |
---|
493 | uint32_t num_load_bit_max = num_load_bit_min+8-1; |
---|
494 | |
---|
495 | log_printf(TRACE,Load_store_unit,FUNCTION," * bypass !!!"); |
---|
496 | // log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [%d:%d]",num_store_bit_max,num_store_bit_min); |
---|
497 | log_printf(TRACE,Load_store_unit,FUNCTION," * interval store : [..:%d]",num_store_bit_min); |
---|
498 | log_printf(TRACE,Load_store_unit,FUNCTION," * interval load : [%d:%d]",num_load_bit_max,num_load_bit_min); |
---|
499 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_old : 0x%.8x", load_data); |
---|
500 | |
---|
501 | load_data = ((((store_data>>num_store_bit_min) & 0xff) << num_load_bit_min) | |
---|
502 | mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min)); |
---|
503 | |
---|
504 | check_hit_byte |= mask; |
---|
505 | check_hit = 1; |
---|
506 | change_state = true; |
---|
507 | |
---|
508 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata_new : 0x%.8x", load_data); |
---|
509 | } |
---|
510 | } |
---|
511 | |
---|
512 | if (is_big_endian) |
---|
513 | { |
---|
514 | // swap in little endian |
---|
515 | load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); |
---|
516 | check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); |
---|
517 | |
---|
518 | |
---|
519 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data); |
---|
520 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte); |
---|
521 | } |
---|
522 | |
---|
523 | _load_queue[index_load]._rdata = load_data; |
---|
524 | _load_queue[index_load]._check_hit_byte = check_hit_byte; |
---|
525 | _load_queue[index_load]._check_hit = check_hit; |
---|
526 | |
---|
527 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); |
---|
528 | |
---|
529 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit); |
---|
530 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); |
---|
531 | |
---|
532 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); |
---|
533 | log_printf(TRACE,Load_store_unit,FUNCTION," * mask_check_hit_byte: %x",_param->_mask_check_hit_byte); |
---|
534 | // The check is finish if all bit is set |
---|
535 | end_check = (_load_queue[index_load]._check_hit_byte == _param->_mask_check_hit_byte); |
---|
536 | } |
---|
537 | } |
---|
538 | |
---|
539 | next = true; |
---|
540 | break; |
---|
541 | } |
---|
542 | case STORE_QUEUE_EMPTY : |
---|
543 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
---|
544 | { |
---|
545 | log_printf(TRACE,Load_store_unit,FUNCTION," * store have an invalid entry"); |
---|
546 | break; |
---|
547 | } |
---|
548 | } |
---|
549 | } |
---|
550 | |
---|
551 | if (next) |
---|
552 | { |
---|
553 | log_printf(TRACE,Load_store_unit,FUNCTION," * next"); |
---|
554 | log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); |
---|
555 | // if (_load_queue[index_load]._store_queue_ptr_write == 0) |
---|
556 | // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; |
---|
557 | // else |
---|
558 | // _load_queue[index_load]._store_queue_ptr_write --; |
---|
559 | _load_queue[index_load]._store_queue_ptr_write = index_store; // because the index store have be decrease |
---|
560 | |
---|
561 | // FIXME : peut n'est pas obliger de faire cette comparaison. Au prochain cycle on le détectera que les pointeur sont égaux. Ceci évitera d'avoir deux comparateurs avec le registre "reg_STORE_QUEUE_PTR_READ" |
---|
562 | if (index_store == reg_STORE_QUEUE_PTR_READ) |
---|
563 | { |
---|
564 | end_check = true; |
---|
565 | change_state = true; |
---|
566 | } |
---|
567 | } |
---|
568 | |
---|
569 | if (change_state) |
---|
570 | { |
---|
571 | log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); |
---|
572 | log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); |
---|
573 | |
---|
574 | log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str()); |
---|
575 | |
---|
576 | switch (_load_queue[index_load]._state) |
---|
577 | { |
---|
578 | case LOAD_QUEUE_WAIT_CHECK : |
---|
579 | { |
---|
580 | if (end_check) |
---|
581 | _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; |
---|
582 | break; |
---|
583 | } |
---|
584 | case LOAD_QUEUE_COMMIT_CHECK : |
---|
585 | { |
---|
586 | if (end_check) |
---|
587 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
---|
588 | else |
---|
589 | _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end |
---|
590 | break; |
---|
591 | } |
---|
592 | case LOAD_QUEUE_CHECK : |
---|
593 | { |
---|
594 | if (end_check) |
---|
595 | _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; |
---|
596 | |
---|
597 | // check find a bypass. A speculative load have been committed : report a speculation miss. |
---|
598 | if ((_load_queue[index_load]._check_hit != 0)// and |
---|
599 | // (_load_queue[index_load]._write_rd == 0) |
---|
600 | ) |
---|
601 | { |
---|
602 | _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
---|
603 | _load_queue[index_load]._write_rd = 1; // write the good result |
---|
604 | } |
---|
605 | |
---|
606 | break; |
---|
607 | } |
---|
608 | default : break; |
---|
609 | } |
---|
610 | log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); |
---|
611 | log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); |
---|
612 | } |
---|
613 | } |
---|
614 | // else : don't use a port |
---|
615 | } |
---|
616 | |
---|
617 | //================================================================ |
---|
618 | // Interface "MEMORY_IN" |
---|
619 | //================================================================ |
---|
620 | |
---|
621 | if ((PORT_READ(in_MEMORY_IN_VAL [internal_MEMORY_IN_PORT]) == 1) and |
---|
622 | ( internal_MEMORY_IN_ACK == 1)) |
---|
623 | { |
---|
624 | log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_IN [%d]",internal_MEMORY_IN_PORT); |
---|
625 | |
---|
626 | // Test operation : |
---|
627 | //~~~~~~~~~~~~~~~~~ |
---|
628 | // store in store_queue |
---|
629 | // load in speculation_access_queue |
---|
630 | // others in speculation_access_queue |
---|
631 | |
---|
632 | #ifdef DEBUG_TEST |
---|
633 | if (PORT_READ(in_MEMORY_IN_TYPE [internal_MEMORY_IN_PORT]) != TYPE_MEMORY) |
---|
634 | throw ERRORMORPHEO(FUNCTION,"The type is different at 'TYPE_MEMORY'"); |
---|
635 | #endif |
---|
636 | Toperation_t operation = PORT_READ(in_MEMORY_IN_OPERATION[internal_MEMORY_IN_PORT]); |
---|
637 | Tgeneral_data_t address = (PORT_READ(in_MEMORY_IN_IMMEDIAT[internal_MEMORY_IN_PORT]) + |
---|
638 | PORT_READ(in_MEMORY_IN_DATA_RA [internal_MEMORY_IN_PORT])); |
---|
639 | bool exception_alignement = (mask_memory_access(operation) & address) != 0; |
---|
640 | |
---|
641 | if (is_operation_memory_store(operation) == true) |
---|
642 | { |
---|
643 | // ======================= |
---|
644 | // ===== STORE_QUEUE ===== |
---|
645 | // ======================= |
---|
646 | // There a two store request type : |
---|
647 | // - first is operation with address and data |
---|
648 | // - second is the information of re order buffer : the store become not speculative and can access at the data cache |
---|
649 | |
---|
650 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue"); |
---|
651 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
---|
652 | |
---|
653 | // Write pointer is define in rename stage : |
---|
654 | Tlsq_ptr_t index = PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
655 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
---|
656 | |
---|
657 | // Need read : state and exception. |
---|
658 | Tstore_queue_state_t old_state = _store_queue [index]._state; |
---|
659 | Tstore_queue_state_t new_state = old_state; |
---|
660 | bool update_info = false; |
---|
661 | |
---|
662 | Texception_t old_exception = _store_queue [index]._exception; |
---|
663 | Texception_t new_exception = old_exception; |
---|
664 | |
---|
665 | // Compute next state |
---|
666 | switch (old_state) |
---|
667 | { |
---|
668 | case STORE_QUEUE_EMPTY : |
---|
669 | { |
---|
670 | if (is_operation_memory_store_head(operation) == true) |
---|
671 | { |
---|
672 | new_state = STORE_QUEUE_NO_VALID_NO_SPECULATIVE; |
---|
673 | |
---|
674 | // test if is a speculation |
---|
675 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
---|
676 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; |
---|
677 | else |
---|
678 | new_exception = EXCEPTION_MEMORY_NONE; |
---|
679 | } |
---|
680 | else |
---|
681 | { |
---|
682 | new_state = STORE_QUEUE_VALID_SPECULATIVE; |
---|
683 | |
---|
684 | // Test if have an exception |
---|
685 | if (exception_alignement == true) |
---|
686 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
687 | else |
---|
688 | new_exception = EXCEPTION_MEMORY_NONE; |
---|
689 | |
---|
690 | update_info = true; |
---|
691 | } |
---|
692 | break; |
---|
693 | } |
---|
694 | case STORE_QUEUE_NO_VALID_NO_SPECULATIVE : |
---|
695 | { |
---|
696 | #ifdef DEBUG_TEST |
---|
697 | if (is_operation_memory_store_head(operation) == true) |
---|
698 | throw ErrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_NO_VALID_NO_SPECULATIVE\", also a previous store_head have been receiveid. But this operation is a store_head.")); |
---|
699 | #endif |
---|
700 | // Test if have a new exception (priority : miss_speculation) |
---|
701 | if ((exception_alignement == true) and (old_exception == EXCEPTION_MEMORY_NONE)) |
---|
702 | new_exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
703 | |
---|
704 | if (new_exception != EXCEPTION_MEMORY_NONE) |
---|
705 | new_state = STORE_QUEUE_COMMIT; |
---|
706 | else |
---|
707 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
---|
708 | |
---|
709 | update_info = true; |
---|
710 | break; |
---|
711 | } |
---|
712 | case STORE_QUEUE_VALID_SPECULATIVE : |
---|
713 | { |
---|
714 | #ifdef DEBUG_TEST |
---|
715 | if (is_operation_memory_store_head(operation) == false) |
---|
716 | throw ErrorMorpheo(_("Transaction in memory_in's interface, actual state of store_queue is \"STORE_QUEUE_VALID_SPECULATIVE\", also a previous access with register and address have been receiveid. But this operation is a not store_head.")); |
---|
717 | #endif |
---|
718 | if (operation == OPERATION_MEMORY_STORE_HEAD_KO) |
---|
719 | new_exception = EXCEPTION_MEMORY_MISS_SPECULATION; // great prioritary |
---|
720 | |
---|
721 | if (new_exception != EXCEPTION_MEMORY_NONE) |
---|
722 | new_state = STORE_QUEUE_COMMIT; |
---|
723 | else |
---|
724 | new_state = STORE_QUEUE_VALID_NO_SPECULATIVE; |
---|
725 | |
---|
726 | break; |
---|
727 | } |
---|
728 | case STORE_QUEUE_VALID_NO_SPECULATIVE : |
---|
729 | case STORE_QUEUE_COMMIT : |
---|
730 | { |
---|
731 | throw ErrorMorpheo("<Load_store_unit::function_speculative_load_commit_transition> Invalid state and operation"); |
---|
732 | } |
---|
733 | } |
---|
734 | |
---|
735 | _store_queue [index]._state = new_state; |
---|
736 | _store_queue [index]._exception = new_exception; |
---|
737 | |
---|
738 | if (update_info == true) |
---|
739 | { |
---|
740 | log_printf(TRACE,Load_store_unit,FUNCTION," * Update information"); |
---|
741 | |
---|
742 | _store_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); |
---|
743 | _store_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); |
---|
744 | _store_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); |
---|
745 | _store_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); |
---|
746 | _store_queue [index]._operation = operation; |
---|
747 | _store_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
748 | _store_queue [index]._address = address; |
---|
749 | |
---|
750 | // reordering data |
---|
751 | _store_queue [index]._wdata = duplicate<Tgeneral_data_t>(_param->_size_general_data,PORT_READ(in_MEMORY_IN_DATA_RB[internal_MEMORY_IN_PORT]), memory_size(operation), 0); |
---|
752 | // _store_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); |
---|
753 | } |
---|
754 | } |
---|
755 | else |
---|
756 | { |
---|
757 | // ==================================== |
---|
758 | // ===== SPECULATIVE_ACCESS_QUEUE ===== |
---|
759 | // ==================================== |
---|
760 | |
---|
761 | // In speculative access queue, they are many type's request |
---|
762 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); |
---|
763 | log_printf(TRACE,Load_store_unit,FUNCTION," * PUSH"); |
---|
764 | |
---|
765 | // Write in reservation station |
---|
766 | uint32_t index = _speculative_access_queue_control->push(); |
---|
767 | |
---|
768 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d", index); |
---|
769 | |
---|
770 | Texception_t exception; |
---|
771 | |
---|
772 | if (exception_alignement == true) |
---|
773 | exception = EXCEPTION_MEMORY_ALIGNMENT; |
---|
774 | else |
---|
775 | exception = EXCEPTION_MEMORY_NONE; |
---|
776 | |
---|
777 | // if exception, don't access at the cache |
---|
778 | // NOTE : type "other" (lock, invalidate, flush and sync) can't make an alignement exception (access is equivalent at a 8 bits) |
---|
779 | _speculative_access_queue [index]._state = (exception == EXCEPTION_MEMORY_NONE)?SPECULATIVE_ACCESS_QUEUE_WAIT_CACHE:SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE; |
---|
780 | _speculative_access_queue [index]._context_id = (not _param->_have_port_context_id )?0:PORT_READ(in_MEMORY_IN_CONTEXT_ID [internal_MEMORY_IN_PORT]); |
---|
781 | _speculative_access_queue [index]._front_end_id = (not _param->_have_port_front_end_id )?0:PORT_READ(in_MEMORY_IN_FRONT_END_ID [internal_MEMORY_IN_PORT]); |
---|
782 | _speculative_access_queue [index]._ooo_engine_id = (not _param->_have_port_ooo_engine_id)?0:PORT_READ(in_MEMORY_IN_OOO_ENGINE_ID[internal_MEMORY_IN_PORT]); |
---|
783 | _speculative_access_queue [index]._packet_id = (not _param->_have_port_rob_ptr )?0:PORT_READ(in_MEMORY_IN_PACKET_ID [internal_MEMORY_IN_PORT]); |
---|
784 | |
---|
785 | _speculative_access_queue [index]._operation = operation; |
---|
786 | _speculative_access_queue [index]._load_queue_ptr_write = (not _param->_have_port_load_queue_ptr)?0:PORT_READ(in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
787 | _speculative_access_queue [index]._store_queue_ptr_write= PORT_READ(in_MEMORY_IN_STORE_QUEUE_PTR_WRITE[internal_MEMORY_IN_PORT]); |
---|
788 | _speculative_access_queue [index]._address = address; |
---|
789 | // NOTE : is operation is a load, then they are a result and must write in the register file |
---|
790 | _speculative_access_queue [index]._write_rd = is_operation_memory_load(operation); |
---|
791 | _speculative_access_queue [index]._num_reg_rd = PORT_READ(in_MEMORY_IN_NUM_REG_RD [internal_MEMORY_IN_PORT]); |
---|
792 | |
---|
793 | _speculative_access_queue [index]._exception = exception; |
---|
794 | |
---|
795 | log_printf(TRACE,Load_store_unit,FUNCTION," * index : %d",index); |
---|
796 | } |
---|
797 | } |
---|
798 | |
---|
799 | //================================================================ |
---|
800 | // Interface "MEMORY_OUT" |
---|
801 | //================================================================ |
---|
802 | |
---|
803 | if (( internal_MEMORY_OUT_VAL == 1) and |
---|
804 | (PORT_READ(in_MEMORY_OUT_ACK[0]) == 1)) |
---|
805 | { |
---|
806 | log_printf(TRACE,Load_store_unit,FUNCTION," * MEMORY_OUT[0] transaction"); |
---|
807 | |
---|
808 | switch (internal_MEMORY_OUT_SELECT_QUEUE) |
---|
809 | { |
---|
810 | case SELECT_STORE_QUEUE : |
---|
811 | { |
---|
812 | // ======================= |
---|
813 | // ===== STORE_QUEUE ===== |
---|
814 | // ======================= |
---|
815 | |
---|
816 | log_printf(TRACE,Load_store_unit,FUNCTION," * store_queue [%d]",reg_STORE_QUEUE_PTR_READ); |
---|
817 | |
---|
818 | // Entry flush and increase the read pointer |
---|
819 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_EMPTY; |
---|
820 | |
---|
821 | reg_STORE_QUEUE_PTR_READ = (reg_STORE_QUEUE_PTR_READ+1)%_param->_size_store_queue; |
---|
822 | |
---|
823 | break; |
---|
824 | } |
---|
825 | case SELECT_LOAD_QUEUE : |
---|
826 | { |
---|
827 | // ====================== |
---|
828 | // ===== LOAD_QUEUE ===== |
---|
829 | // ====================== |
---|
830 | |
---|
831 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d]",internal_MEMORY_OUT_PTR); |
---|
832 | |
---|
833 | // Entry flush and increase the read pointer |
---|
834 | |
---|
835 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_EMPTY; |
---|
836 | |
---|
837 | // reg_LOAD_QUEUE_PTR_READ = (reg_LOAD_QUEUE_PTR_READ+1)%_param->_size_load_queue; |
---|
838 | |
---|
839 | break; |
---|
840 | } |
---|
841 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
---|
842 | { |
---|
843 | log_printf(TRACE,Load_store_unit,FUNCTION," * load_queue [%d] (speculative)",internal_MEMORY_OUT_PTR); |
---|
844 | |
---|
845 | _load_queue [internal_MEMORY_OUT_PTR]._state = LOAD_QUEUE_CHECK; |
---|
846 | // NOTE : a speculative load write in the register file. |
---|
847 | // if the speculation is a miss, write_rd is re set at 1. |
---|
848 | _load_queue [internal_MEMORY_OUT_PTR]._write_rd = 0; |
---|
849 | break; |
---|
850 | } |
---|
851 | |
---|
852 | break; |
---|
853 | } |
---|
854 | } |
---|
855 | |
---|
856 | //================================================================ |
---|
857 | // Interface "DCACHE_REQ" |
---|
858 | //================================================================ |
---|
859 | bool load_queue_push = (_speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._state == SPECULATIVE_ACCESS_QUEUE_WAIT_LOAD_QUEUE); |
---|
860 | |
---|
861 | if (( internal_DCACHE_REQ_VAL == 1) and |
---|
862 | (PORT_READ(in_DCACHE_REQ_ACK[0]) == 1)) |
---|
863 | { |
---|
864 | log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_REQ [0]"); |
---|
865 | |
---|
866 | switch (internal_DCACHE_REQ_SELECT_QUEUE) |
---|
867 | { |
---|
868 | case SELECT_STORE_QUEUE : |
---|
869 | { |
---|
870 | // ======================= |
---|
871 | // ===== STORE_QUEUE ===== |
---|
872 | // ======================= |
---|
873 | |
---|
874 | // Entry flush and increase the read pointer |
---|
875 | |
---|
876 | _store_queue [reg_STORE_QUEUE_PTR_READ]._state = STORE_QUEUE_COMMIT; |
---|
877 | |
---|
878 | break; |
---|
879 | } |
---|
880 | case SELECT_LOAD_QUEUE_SPECULATIVE : |
---|
881 | { |
---|
882 | // ========================================= |
---|
883 | // ===== SELECT_LOAD_QUEUE_SPECULATIVE ===== |
---|
884 | // ========================================= |
---|
885 | |
---|
886 | load_queue_push = true; |
---|
887 | break; |
---|
888 | } |
---|
889 | case SELECT_LOAD_QUEUE : |
---|
890 | { |
---|
891 | throw ErrorMorpheo(_("Invalid selection")); |
---|
892 | break; |
---|
893 | } |
---|
894 | |
---|
895 | break; |
---|
896 | } |
---|
897 | } |
---|
898 | |
---|
899 | if (load_queue_push) |
---|
900 | { |
---|
901 | Tlsq_ptr_t ptr_write = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._load_queue_ptr_write; |
---|
902 | Toperation_t operation = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._operation; |
---|
903 | Texception_t exception = _speculative_access_queue[internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._exception; |
---|
904 | bool have_exception = (exception != EXCEPTION_MEMORY_NONE); |
---|
905 | |
---|
906 | if (have_exception) |
---|
907 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
908 | else |
---|
909 | { |
---|
910 | if (have_dcache_rsp(operation)) |
---|
911 | { |
---|
912 | // load and synchronisation |
---|
913 | if (must_check(operation)) |
---|
914 | { |
---|
915 | // load |
---|
916 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT_CHECK; |
---|
917 | } |
---|
918 | else |
---|
919 | { |
---|
920 | // synchronisation |
---|
921 | _load_queue [ptr_write]._state = LOAD_QUEUE_WAIT; |
---|
922 | } |
---|
923 | } |
---|
924 | else |
---|
925 | { |
---|
926 | // lock, prefecth, flush and invalidate |
---|
927 | _load_queue [ptr_write]._state = LOAD_QUEUE_COMMIT; |
---|
928 | } |
---|
929 | } |
---|
930 | |
---|
931 | Tdcache_address_t address = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._address; |
---|
932 | Tdcache_address_t address_lsb = (address & _param->_mask_address_lsb); |
---|
933 | Tdcache_address_t check_hit_byte = gen_mask_not<Tdcache_address_t>(address_lsb+(memory_size(operation)>>3)-1,address_lsb) & _param->_mask_check_hit_byte; |
---|
934 | |
---|
935 | log_printf(TRACE,Load_store_unit,FUNCTION," * address : 0x%.8x", address); |
---|
936 | log_printf(TRACE,Load_store_unit,FUNCTION," * address_lsb : 0x%.8x", address_lsb); |
---|
937 | log_printf(TRACE,Load_store_unit,FUNCTION," * operation : %d", operation); |
---|
938 | log_printf(TRACE,Load_store_unit,FUNCTION," * memory_size : %d", memory_size(operation)); |
---|
939 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x", check_hit_byte); |
---|
940 | |
---|
941 | _load_queue [ptr_write]._context_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._context_id; |
---|
942 | _load_queue [ptr_write]._front_end_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._front_end_id; |
---|
943 | _load_queue [ptr_write]._ooo_engine_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._ooo_engine_id; |
---|
944 | _load_queue [ptr_write]._packet_id = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._packet_id; |
---|
945 | _load_queue [ptr_write]._operation = operation; |
---|
946 | _load_queue [ptr_write]._store_queue_ptr_write = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._store_queue_ptr_write; |
---|
947 | _load_queue [ptr_write]._address = address; |
---|
948 | _load_queue [ptr_write]._check_hit_byte = check_hit_byte; |
---|
949 | _load_queue [ptr_write]._check_hit = 0; |
---|
950 | _load_queue [ptr_write]._shift = address_lsb<<3;// *8 |
---|
951 | _load_queue [ptr_write]._is_load_signed = is_operation_memory_load_signed(operation); |
---|
952 | _load_queue [ptr_write]._access_size = memory_size(operation); |
---|
953 | // NOTE : if have an exception, must write in register, because a depend instruction wait the load data. |
---|
954 | _load_queue [ptr_write]._write_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._write_rd ; |
---|
955 | |
---|
956 | _load_queue [ptr_write]._num_reg_rd = _speculative_access_queue [internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ]._num_reg_rd ; |
---|
957 | _load_queue [ptr_write]._exception = exception; |
---|
958 | _load_queue [ptr_write]._rdata = address; // to the exception |
---|
959 | |
---|
960 | log_printf(TRACE,Load_store_unit,FUNCTION," * speculative_access_queue"); |
---|
961 | log_printf(TRACE,Load_store_unit,FUNCTION," * POP[%d]",(*_speculative_access_queue_control)[0]); |
---|
962 | |
---|
963 | _speculative_access_queue [(*_speculative_access_queue_control)[0]]._state = SPECULATIVE_ACCESS_QUEUE_EMPTY; |
---|
964 | |
---|
965 | _speculative_access_queue_control->pop(); |
---|
966 | } |
---|
967 | |
---|
968 | //================================================================ |
---|
969 | // Interface "DCACHE_RSP" |
---|
970 | //================================================================ |
---|
971 | if ((PORT_READ(in_DCACHE_RSP_VAL[0])== 1) and |
---|
972 | ( internal_DCACHE_RSP_ACK == 1)) |
---|
973 | { |
---|
974 | log_printf(TRACE,Load_store_unit,FUNCTION," * DCACHE_RSP [0]"); |
---|
975 | |
---|
976 | // don't use context_id : because there are one queue for all thread |
---|
977 | //Tcontext_t context_id = PORT_READ(in_DCACHE_RSP_CONTEXT_ID[0]); |
---|
978 | Tpacket_t packet_id = PORT_READ(in_DCACHE_RSP_PACKET_ID [0]); |
---|
979 | Tdcache_data_t rdata = PORT_READ(in_DCACHE_RSP_RDATA [0]); |
---|
980 | Tdcache_error_t error = PORT_READ(in_DCACHE_RSP_ERROR [0]); |
---|
981 | |
---|
982 | log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); |
---|
983 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1); |
---|
984 | log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); |
---|
985 | log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); |
---|
986 | |
---|
987 | if (DCACHE_RSP_IS_LOAD(packet_id) == 1) |
---|
988 | { |
---|
989 | packet_id >>= 1; |
---|
990 | |
---|
991 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD"); |
---|
992 | |
---|
993 | #ifdef DEBUG_TEST |
---|
994 | if (not have_dcache_rsp(_load_queue [packet_id]._operation)) |
---|
995 | throw ErrorMorpheo(_("Receive of respons, but the corresponding operation don't wait a respons.")); |
---|
996 | #endif |
---|
997 | |
---|
998 | Tdcache_data_t data = _load_queue [packet_id]._rdata; |
---|
999 | |
---|
1000 | log_printf(TRACE,Load_store_unit,FUNCTION," * data construction"); |
---|
1001 | log_printf(TRACE,Load_store_unit,FUNCTION," * data from cache : 0x%.8x",rdata); |
---|
1002 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (before) : 0x%.8x", data); |
---|
1003 | log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : 0x%x" ,_load_queue [packet_id]._check_hit_byte); |
---|
1004 | for (uint32_t i=0;i<(_param->_size_general_data>>3)/*8*/; ++i) |
---|
1005 | // Test if this byte has been checked |
---|
1006 | if ((_load_queue [packet_id]._check_hit_byte & (1<<i)) == 0) |
---|
1007 | { |
---|
1008 | log_printf(TRACE,Load_store_unit,FUNCTION," * no previous check ]%d:%d]",(i+1)<<3,i<<3); |
---|
1009 | data = insert<Tdcache_data_t>(data,rdata,((i+1)<<3)-1,i<<3); |
---|
1010 | } |
---|
1011 | log_printf(TRACE,Load_store_unit,FUNCTION," * data (after) : 0x%.8x", data); |
---|
1012 | |
---|
1013 | _load_queue [packet_id]._rdata = data; |
---|
1014 | |
---|
1015 | if (error != DCACHE_ERROR_NONE) |
---|
1016 | { |
---|
1017 | log_printf(TRACE,Load_store_unit,FUNCTION," * have a bus error !!!"); |
---|
1018 | |
---|
1019 | _load_queue [packet_id]._exception = EXCEPTION_MEMORY_BUS_ERROR; |
---|
1020 | _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT; |
---|
1021 | } |
---|
1022 | else |
---|
1023 | { |
---|
1024 | log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); |
---|
1025 | log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str()); |
---|
1026 | |
---|
1027 | // FIXME : convention : if bus error, the cache return the fautive address ! |
---|
1028 | // But, the load's address is aligned ! |
---|
1029 | |
---|
1030 | switch (_load_queue [packet_id]._state) |
---|
1031 | { |
---|
1032 | case LOAD_QUEUE_WAIT_CHECK : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT_CHECK; break; |
---|
1033 | case LOAD_QUEUE_WAIT : _load_queue [packet_id]._state = LOAD_QUEUE_COMMIT ; break; |
---|
1034 | default : throw ErrorMorpheo(_("Illegal state (dcache_rsp).")); break; |
---|
1035 | } |
---|
1036 | } |
---|
1037 | } |
---|
1038 | else |
---|
1039 | { |
---|
1040 | log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a STORE"); |
---|
1041 | |
---|
1042 | // TODO : les stores ne génére pas de réponse sauf quand c'est un bus error !!! |
---|
1043 | throw ERRORMORPHEO(FUNCTION,_("dcache_rsp : no respons to a write. (TODO : manage bus error to the store operation.)")); |
---|
1044 | } |
---|
1045 | |
---|
1046 | } |
---|
1047 | |
---|
1048 | // this register is to manage the priority of check -> Round robin |
---|
1049 | reg_LOAD_QUEUE_CHECK_PRIORITY = (reg_LOAD_QUEUE_CHECK_PRIORITY+1)%_param->_size_load_queue; |
---|
1050 | |
---|
1051 | |
---|
1052 | #if defined(DEBUG) and (DEBUG>=DEBUG_TRACE) |
---|
1053 | // ***** dump store queue |
---|
1054 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump STORE_QUEUE"); |
---|
1055 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); |
---|
1056 | |
---|
1057 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
1058 | { |
---|
1059 | uint32_t j = (reg_STORE_QUEUE_PTR_READ+i)%_param->_size_store_queue; |
---|
1060 | |
---|
1061 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.8x, %.2d, %s", |
---|
1062 | j, |
---|
1063 | _store_queue[j]._context_id , |
---|
1064 | _store_queue[j]._front_end_id , |
---|
1065 | _store_queue[j]._ooo_engine_id , |
---|
1066 | _store_queue[j]._packet_id , |
---|
1067 | _store_queue[j]._operation , |
---|
1068 | _store_queue[j]._load_queue_ptr_write, |
---|
1069 | _store_queue[j]._address , |
---|
1070 | _store_queue[j]._wdata , |
---|
1071 | //_store_queue[j]._write_rd , |
---|
1072 | //_store_queue[j]._num_reg_rd , |
---|
1073 | _store_queue[j]._exception , |
---|
1074 | toString(_store_queue[j]._state).c_str()); |
---|
1075 | } |
---|
1076 | |
---|
1077 | // ***** dump speculative_access queue |
---|
1078 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump SPECULATIVE_ACCESS_QUEUE"); |
---|
1079 | |
---|
1080 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
1081 | { |
---|
1082 | uint32_t j = (*_speculative_access_queue_control)[i]; |
---|
1083 | |
---|
1084 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d %.4d, %.8x, %.1d %.4d, %.2d, %s", |
---|
1085 | j, |
---|
1086 | _speculative_access_queue[j]._context_id , |
---|
1087 | _speculative_access_queue[j]._front_end_id , |
---|
1088 | _speculative_access_queue[j]._ooo_engine_id , |
---|
1089 | _speculative_access_queue[j]._packet_id , |
---|
1090 | _speculative_access_queue[j]._operation , |
---|
1091 | _speculative_access_queue[j]._load_queue_ptr_write, |
---|
1092 | _speculative_access_queue[j]._store_queue_ptr_write, |
---|
1093 | _speculative_access_queue[j]._address , |
---|
1094 | _speculative_access_queue[j]._write_rd , |
---|
1095 | _speculative_access_queue[j]._num_reg_rd , |
---|
1096 | _speculative_access_queue[j]._exception , |
---|
1097 | toString(_speculative_access_queue[j]._state).c_str()); |
---|
1098 | } |
---|
1099 | |
---|
1100 | // ***** dump load queue |
---|
1101 | log_printf(TRACE,Load_store_unit,FUNCTION," * Dump LOAD_QUEUE"); |
---|
1102 | log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read_check_priority : %d",reg_LOAD_QUEUE_CHECK_PRIORITY); |
---|
1103 | |
---|
1104 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
1105 | { |
---|
1106 | uint32_t j = i; |
---|
1107 | |
---|
1108 | log_printf(TRACE,Load_store_unit,FUNCTION," [%.4d] %.4d %.4d %.4d, %.4d, %.4d, %.4d, %.8x %.1x %.1d %.2d %.1d %.2d, %.8x, %.1d %.4d, %.2d, %s", |
---|
1109 | j, |
---|
1110 | _load_queue[j]._context_id , |
---|
1111 | _load_queue[j]._front_end_id , |
---|
1112 | _load_queue[j]._ooo_engine_id , |
---|
1113 | _load_queue[j]._packet_id , |
---|
1114 | _load_queue[j]._operation , |
---|
1115 | _load_queue[j]._store_queue_ptr_write, |
---|
1116 | _load_queue[j]._address , |
---|
1117 | _load_queue[j]._check_hit_byte , |
---|
1118 | _load_queue[j]._check_hit , |
---|
1119 | _load_queue[j]._shift , |
---|
1120 | _load_queue[j]._is_load_signed , |
---|
1121 | _load_queue[j]._access_size , |
---|
1122 | _load_queue[j]._rdata , |
---|
1123 | _load_queue[j]._write_rd , |
---|
1124 | _load_queue[j]._num_reg_rd , |
---|
1125 | _load_queue[j]._exception , |
---|
1126 | toString(_load_queue[j]._state).c_str()); |
---|
1127 | } |
---|
1128 | #endif |
---|
1129 | |
---|
1130 | #ifdef STATISTICS |
---|
1131 | if (usage_is_set(_usage,USE_STATISTICS)) |
---|
1132 | { |
---|
1133 | for (uint32_t i=0; i<_param->_size_store_queue; i++) |
---|
1134 | if (_store_queue[i]._state != STORE_QUEUE_EMPTY) |
---|
1135 | (*_stat_use_store_queue) ++; |
---|
1136 | for (uint32_t i=0; i<_param->_size_speculative_access_queue; i++) |
---|
1137 | if (_speculative_access_queue[i]._state != SPECULATIVE_ACCESS_QUEUE_EMPTY) |
---|
1138 | (*_stat_use_speculative_access_queue) ++; |
---|
1139 | for (uint32_t i=0; i<_param->_size_load_queue; i++) |
---|
1140 | if (_load_queue[i]._state != LOAD_QUEUE_EMPTY) |
---|
1141 | (*_stat_use_load_queue) ++; |
---|
1142 | } |
---|
1143 | #endif |
---|
1144 | } |
---|
1145 | |
---|
1146 | log_end(Load_store_unit,FUNCTION); |
---|
1147 | }; |
---|
1148 | |
---|
1149 | }; // end namespace load_store_unit |
---|
1150 | }; // end namespace execute_unit |
---|
1151 | }; // end namespace multi_execute_unit |
---|
1152 | }; // end namespace execute_loop |
---|
1153 | }; // end namespace multi_execute_loop |
---|
1154 | }; // end namespace core |
---|
1155 | |
---|
1156 | }; // end namespace behavioural |
---|
1157 | }; // end namespace morpheo |
---|
1158 | #endif |
---|