[55] | 1 | /* |
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| 2 | * $Id: test.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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[97] | 8 | #define NB_ITERATION 1 |
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[112] | 9 | #define CYCLE_MAX (10000*NB_ITERATION) |
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[55] | 10 | |
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| 11 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h" |
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| 12 | #include "Common/include/Test.h" |
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[75] | 13 | #include "Common/include/BitManipulation.h" |
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[55] | 14 | |
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| 15 | void test (string name, |
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| 16 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters * _param) |
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| 17 | { |
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| 18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 19 | |
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| 20 | #ifdef STATISTICS |
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| 21 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 22 | #endif |
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| 23 | |
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[88] | 24 | Tusage_t _usage = USE_ALL; |
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| 25 | |
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| 26 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 27 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 28 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 29 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 30 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 31 | _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 32 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 33 | |
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[82] | 34 | Reservation_station * _Reservation_station = new Reservation_station |
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| 35 | (name.c_str(), |
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[55] | 36 | #ifdef STATISTICS |
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[82] | 37 | _parameters_statistics, |
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[55] | 38 | #endif |
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[82] | 39 | _param, |
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[88] | 40 | _usage); |
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[55] | 41 | |
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| 42 | #ifdef SYSTEMC |
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| 43 | /********************************************************************* |
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| 44 | * Déclarations des signaux |
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| 45 | *********************************************************************/ |
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| 46 | string rename = ""; |
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| 47 | |
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| 48 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 49 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 50 | |
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[69] | 51 | sc_signal<Tcontrol_t > * in_INSERT_VAL = new sc_signal<Tcontrol_t >; |
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| 52 | sc_signal<Tcontrol_t > * out_INSERT_ACK = new sc_signal<Tcontrol_t >; |
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| 53 | sc_signal<Tcontext_t > * in_INSERT_CONTEXT_ID = new sc_signal<Tcontext_t >; |
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| 54 | sc_signal<Tcontext_t > * in_INSERT_FRONT_END_ID = new sc_signal<Tcontext_t >; |
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| 55 | sc_signal<Tcontext_t > * in_INSERT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >; |
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| 56 | sc_signal<Tpacket_t > * in_INSERT_ROB_ID = new sc_signal<Tpacket_t >; |
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| 57 | sc_signal<Toperation_t > * in_INSERT_OPERATION = new sc_signal<Toperation_t >; |
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| 58 | sc_signal<Ttype_t > * in_INSERT_TYPE = new sc_signal<Ttype_t >; |
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[76] | 59 | sc_signal<Tlsq_ptr_t > * in_INSERT_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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| 60 | sc_signal<Tlsq_ptr_t > * in_INSERT_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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[69] | 61 | sc_signal<Tcontrol_t > * in_INSERT_HAS_IMMEDIAT = new sc_signal<Tcontrol_t >; |
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| 62 | sc_signal<Tgeneral_data_t > * in_INSERT_IMMEDIAT = new sc_signal<Tgeneral_data_t >; |
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| 63 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RA = new sc_signal<Tcontrol_t >; |
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| 64 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RA = new sc_signal<Tgeneral_address_t>; |
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| 65 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RA_VAL = new sc_signal<Tcontrol_t >; |
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| 66 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RA = new sc_signal<Tgeneral_data_t >; |
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| 67 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RB = new sc_signal<Tcontrol_t >; |
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| 68 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RB = new sc_signal<Tgeneral_address_t>; |
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| 69 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RB_VAL = new sc_signal<Tcontrol_t >; |
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| 70 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RB = new sc_signal<Tgeneral_data_t >; |
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| 71 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RC = new sc_signal<Tcontrol_t >; |
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| 72 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RC = new sc_signal<Tspecial_address_t>; |
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| 73 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RC_VAL = new sc_signal<Tcontrol_t >; |
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| 74 | sc_signal<Tspecial_data_t > * in_INSERT_DATA_RC = new sc_signal<Tspecial_data_t >; |
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| 75 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RD = new sc_signal<Tcontrol_t >; |
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| 76 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>; |
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| 77 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RE = new sc_signal<Tcontrol_t >; |
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| 78 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RE = new sc_signal<Tspecial_address_t>; |
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[55] | 79 | |
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[69] | 80 | sc_signal<Tcontrol_t > ** out_RETIRE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 81 | sc_signal<Tcontrol_t > ** in_RETIRE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 82 | sc_signal<Tcontext_t > ** out_RETIRE_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 83 | sc_signal<Tcontext_t > ** out_RETIRE_FRONT_END_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 84 | sc_signal<Tcontext_t > ** out_RETIRE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 85 | sc_signal<Tpacket_t > ** out_RETIRE_ROB_ID = new sc_signal<Tpacket_t > * [_param->_nb_inst_retire]; |
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| 86 | sc_signal<Toperation_t > ** out_RETIRE_OPERATION = new sc_signal<Toperation_t > * [_param->_nb_inst_retire]; |
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| 87 | sc_signal<Ttype_t > ** out_RETIRE_TYPE = new sc_signal<Ttype_t > * [_param->_nb_inst_retire]; |
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[76] | 88 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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| 89 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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[69] | 90 | sc_signal<Tcontrol_t > ** out_RETIRE_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 91 | sc_signal<Tgeneral_data_t > ** out_RETIRE_IMMEDIAT = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 92 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RA = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 93 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RB = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 94 | sc_signal<Tspecial_data_t > ** out_RETIRE_DATA_RC = new sc_signal<Tspecial_data_t > * [_param->_nb_inst_retire]; |
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| 95 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RD = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 96 | sc_signal<Tgeneral_address_t> ** out_RETIRE_NUM_REG_RD = new sc_signal<Tgeneral_address_t> * [_param->_nb_inst_retire]; |
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| 97 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RE = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 98 | sc_signal<Tspecial_address_t> ** out_RETIRE_NUM_REG_RE = new sc_signal<Tspecial_address_t> * [_param->_nb_inst_retire]; |
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[55] | 99 | |
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[69] | 100 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 101 | { |
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[69] | 102 | out_RETIRE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 103 | in_RETIRE_ACK [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 104 | out_RETIRE_CONTEXT_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 105 | out_RETIRE_FRONT_END_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 106 | out_RETIRE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 107 | out_RETIRE_ROB_ID [i] = new sc_signal<Tpacket_t > (rename.c_str()); |
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| 108 | out_RETIRE_OPERATION [i] = new sc_signal<Toperation_t > (rename.c_str()); |
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| 109 | out_RETIRE_TYPE [i] = new sc_signal<Ttype_t > (rename.c_str()); |
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[76] | 110 | out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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| 111 | out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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[69] | 112 | out_RETIRE_HAS_IMMEDIAT [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 113 | out_RETIRE_IMMEDIAT [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 114 | out_RETIRE_DATA_RA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 115 | out_RETIRE_DATA_RB [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 116 | out_RETIRE_DATA_RC [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 117 | out_RETIRE_WRITE_RD [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 118 | out_RETIRE_NUM_REG_RD [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 119 | out_RETIRE_WRITE_RE [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 120 | out_RETIRE_NUM_REG_RE [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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[55] | 121 | } |
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| 122 | |
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[69] | 123 | sc_signal<Tcontrol_t > ** in_GPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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| 124 | sc_signal<Tcontext_t > ** in_GPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_write]; |
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| 125 | sc_signal<Tgeneral_address_t> ** in_GPR_WRITE_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_write]; |
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| 126 | sc_signal<Tgeneral_data_t > ** in_GPR_WRITE_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_write]; |
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[55] | 127 | |
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| 128 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 129 | { |
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[69] | 130 | in_GPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 131 | in_GPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 132 | in_GPR_WRITE_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 133 | in_GPR_WRITE_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 134 | } |
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| 135 | |
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[69] | 136 | sc_signal<Tcontrol_t > ** in_SPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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| 137 | sc_signal<Tcontext_t > ** in_SPR_WRITE_OOO_ENGINE_ID= new sc_signal<Tcontext_t > * [_param->_nb_spr_write]; |
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| 138 | sc_signal<Tspecial_address_t> ** in_SPR_WRITE_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_write]; |
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| 139 | sc_signal<Tspecial_data_t > ** in_SPR_WRITE_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_write]; |
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[55] | 140 | |
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| 141 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 142 | { |
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[69] | 143 | in_SPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 144 | in_SPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 145 | in_SPR_WRITE_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 146 | in_SPR_WRITE_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 147 | } |
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| 148 | |
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[69] | 149 | sc_signal<Tcontext_t > ** in_BYPASS_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_write]; |
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| 150 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_GPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 151 | sc_signal<Tgeneral_address_t> ** in_BYPASS_WRITE_GPR_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_write]; |
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| 152 | sc_signal<Tgeneral_data_t > ** in_BYPASS_WRITE_GPR_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_write]; |
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| 153 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_SPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 154 | sc_signal<Tspecial_address_t> ** in_BYPASS_WRITE_SPR_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_bypass_write]; |
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| 155 | sc_signal<Tspecial_data_t > ** in_BYPASS_WRITE_SPR_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_bypass_write]; |
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[55] | 156 | |
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| 157 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 158 | { |
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[69] | 159 | in_BYPASS_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 160 | in_BYPASS_WRITE_GPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 161 | in_BYPASS_WRITE_GPR_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 162 | in_BYPASS_WRITE_GPR_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 163 | in_BYPASS_WRITE_SPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 164 | in_BYPASS_WRITE_SPR_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 165 | in_BYPASS_WRITE_SPR_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 166 | } |
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[69] | 167 | sc_signal<Tcontrol_t > ** in_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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| 168 | sc_signal<Tcontext_t > ** in_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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| 169 | sc_signal<Tgeneral_address_t> ** in_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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| 170 | sc_signal<Tgeneral_data_t > ** in_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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[55] | 171 | |
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| 172 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 173 | { |
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[69] | 174 | in_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 175 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 176 | in_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 177 | in_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 178 | } |
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| 179 | |
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| 180 | /******************************************************** |
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| 181 | * Instanciation |
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| 182 | ********************************************************/ |
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| 183 | |
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| 184 | cout << "<" << name << "> Instanciation of _Reservation_station" << endl; |
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| 185 | |
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| 186 | (*(_Reservation_station->in_CLOCK)) (*(in_CLOCK)); |
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| 187 | (*(_Reservation_station->in_NRESET)) (*(in_NRESET)); |
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| 188 | |
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[69] | 189 | (*(_Reservation_station-> in_INSERT_VAL )) (*( in_INSERT_VAL )); |
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| 190 | (*(_Reservation_station->out_INSERT_ACK )) (*(out_INSERT_ACK )); |
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| 191 | if (_param->_have_port_context_id) |
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| 192 | (*(_Reservation_station-> in_INSERT_CONTEXT_ID )) (*( in_INSERT_CONTEXT_ID )); |
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| 193 | if (_param->_have_port_front_end_id) |
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| 194 | (*(_Reservation_station-> in_INSERT_FRONT_END_ID )) (*( in_INSERT_FRONT_END_ID )); |
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| 195 | if (_param->_have_port_ooo_engine_id) |
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| 196 | (*(_Reservation_station-> in_INSERT_OOO_ENGINE_ID )) (*( in_INSERT_OOO_ENGINE_ID )); |
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[88] | 197 | if (_param->_have_port_rob_ptr) |
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[69] | 198 | (*(_Reservation_station-> in_INSERT_ROB_ID )) (*( in_INSERT_ROB_ID )); |
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| 199 | (*(_Reservation_station-> in_INSERT_OPERATION )) (*( in_INSERT_OPERATION )); |
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| 200 | (*(_Reservation_station-> in_INSERT_TYPE )) (*( in_INSERT_TYPE )); |
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[76] | 201 | (*(_Reservation_station-> in_INSERT_STORE_QUEUE_PTR_WRITE)) (*( in_INSERT_STORE_QUEUE_PTR_WRITE)); |
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[78] | 202 | if (_param->_have_port_load_queue_ptr) |
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[76] | 203 | (*(_Reservation_station-> in_INSERT_LOAD_QUEUE_PTR_WRITE )) (*( in_INSERT_LOAD_QUEUE_PTR_WRITE )); |
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[69] | 204 | (*(_Reservation_station-> in_INSERT_HAS_IMMEDIAT )) (*( in_INSERT_HAS_IMMEDIAT )); |
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| 205 | (*(_Reservation_station-> in_INSERT_IMMEDIAT )) (*( in_INSERT_IMMEDIAT )); |
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| 206 | // (*(_Reservation_station-> in_INSERT_READ_RA )) (*( in_INSERT_READ_RA )); |
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| 207 | (*(_Reservation_station-> in_INSERT_NUM_REG_RA )) (*( in_INSERT_NUM_REG_RA )); |
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| 208 | (*(_Reservation_station-> in_INSERT_DATA_RA_VAL )) (*( in_INSERT_DATA_RA_VAL )); |
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| 209 | (*(_Reservation_station-> in_INSERT_DATA_RA )) (*( in_INSERT_DATA_RA )); |
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| 210 | // (*(_Reservation_station-> in_INSERT_READ_RB )) (*( in_INSERT_READ_RB )); |
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| 211 | (*(_Reservation_station-> in_INSERT_NUM_REG_RB )) (*( in_INSERT_NUM_REG_RB )); |
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| 212 | (*(_Reservation_station-> in_INSERT_DATA_RB_VAL )) (*( in_INSERT_DATA_RB_VAL )); |
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| 213 | (*(_Reservation_station-> in_INSERT_DATA_RB )) (*( in_INSERT_DATA_RB )); |
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| 214 | // (*(_Reservation_station-> in_INSERT_READ_RC )) (*( in_INSERT_READ_RC )); |
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| 215 | (*(_Reservation_station-> in_INSERT_NUM_REG_RC )) (*( in_INSERT_NUM_REG_RC )); |
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| 216 | (*(_Reservation_station-> in_INSERT_DATA_RC_VAL )) (*( in_INSERT_DATA_RC_VAL )); |
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| 217 | (*(_Reservation_station-> in_INSERT_DATA_RC )) (*( in_INSERT_DATA_RC )); |
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| 218 | (*(_Reservation_station-> in_INSERT_WRITE_RD )) (*( in_INSERT_WRITE_RD )); |
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| 219 | (*(_Reservation_station-> in_INSERT_NUM_REG_RD )) (*( in_INSERT_NUM_REG_RD )); |
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| 220 | (*(_Reservation_station-> in_INSERT_WRITE_RE )) (*( in_INSERT_WRITE_RE )); |
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| 221 | (*(_Reservation_station-> in_INSERT_NUM_REG_RE )) (*( in_INSERT_NUM_REG_RE )); |
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[55] | 222 | |
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[69] | 223 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 224 | { |
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[69] | 225 | (*(_Reservation_station->out_RETIRE_VAL [i])) (*(out_RETIRE_VAL [i])); |
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| 226 | (*(_Reservation_station-> in_RETIRE_ACK [i])) (*( in_RETIRE_ACK [i])); |
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| 227 | if (_param->_have_port_context_id) |
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| 228 | (*(_Reservation_station->out_RETIRE_CONTEXT_ID [i])) (*(out_RETIRE_CONTEXT_ID [i])); |
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| 229 | if (_param->_have_port_front_end_id) |
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| 230 | (*(_Reservation_station->out_RETIRE_FRONT_END_ID [i])) (*(out_RETIRE_FRONT_END_ID [i])); |
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| 231 | if (_param->_have_port_ooo_engine_id) |
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| 232 | (*(_Reservation_station->out_RETIRE_OOO_ENGINE_ID [i])) (*(out_RETIRE_OOO_ENGINE_ID [i])); |
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[88] | 233 | if (_param->_have_port_rob_ptr) |
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[69] | 234 | (*(_Reservation_station->out_RETIRE_ROB_ID [i])) (*(out_RETIRE_ROB_ID [i])); |
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| 235 | (*(_Reservation_station->out_RETIRE_OPERATION [i])) (*(out_RETIRE_OPERATION [i])); |
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| 236 | (*(_Reservation_station->out_RETIRE_TYPE [i])) (*(out_RETIRE_TYPE [i])); |
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[76] | 237 | (*(_Reservation_station->out_RETIRE_STORE_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_STORE_QUEUE_PTR_WRITE [i])); |
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[78] | 238 | if (_param->_have_port_load_queue_ptr) |
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[76] | 239 | (*(_Reservation_station->out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])); |
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[69] | 240 | (*(_Reservation_station->out_RETIRE_HAS_IMMEDIAT [i])) (*(out_RETIRE_HAS_IMMEDIAT [i])); |
---|
| 241 | (*(_Reservation_station->out_RETIRE_IMMEDIAT [i])) (*(out_RETIRE_IMMEDIAT [i])); |
---|
| 242 | (*(_Reservation_station->out_RETIRE_DATA_RA [i])) (*(out_RETIRE_DATA_RA [i])); |
---|
| 243 | (*(_Reservation_station->out_RETIRE_DATA_RB [i])) (*(out_RETIRE_DATA_RB [i])); |
---|
| 244 | (*(_Reservation_station->out_RETIRE_DATA_RC [i])) (*(out_RETIRE_DATA_RC [i])); |
---|
| 245 | (*(_Reservation_station->out_RETIRE_WRITE_RD [i])) (*(out_RETIRE_WRITE_RD [i])); |
---|
| 246 | (*(_Reservation_station->out_RETIRE_NUM_REG_RD [i])) (*(out_RETIRE_NUM_REG_RD [i])); |
---|
| 247 | (*(_Reservation_station->out_RETIRE_WRITE_RE [i])) (*(out_RETIRE_WRITE_RE [i])); |
---|
| 248 | (*(_Reservation_station->out_RETIRE_NUM_REG_RE [i])) (*(out_RETIRE_NUM_REG_RE [i])); |
---|
[55] | 249 | } |
---|
| 250 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 251 | { |
---|
| 252 | (*(_Reservation_station-> in_GPR_WRITE_VAL [i])) (*( in_GPR_WRITE_VAL [i])); |
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[69] | 253 | if (_param->_have_port_ooo_engine_id) |
---|
| 254 | (*(_Reservation_station-> in_GPR_WRITE_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 255 | (*(_Reservation_station-> in_GPR_WRITE_NUM_REG [i])) (*( in_GPR_WRITE_NUM_REG [i])); |
---|
| 256 | (*(_Reservation_station-> in_GPR_WRITE_DATA [i])) (*( in_GPR_WRITE_DATA [i])); |
---|
| 257 | } |
---|
| 258 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 259 | { |
---|
| 260 | (*(_Reservation_station-> in_SPR_WRITE_VAL [i])) (*( in_SPR_WRITE_VAL [i])); |
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[69] | 261 | if (_param->_have_port_ooo_engine_id) |
---|
| 262 | (*(_Reservation_station-> in_SPR_WRITE_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 263 | (*(_Reservation_station-> in_SPR_WRITE_NUM_REG [i])) (*( in_SPR_WRITE_NUM_REG [i])); |
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| 264 | (*(_Reservation_station-> in_SPR_WRITE_DATA [i])) (*( in_SPR_WRITE_DATA [i])); |
---|
| 265 | } |
---|
| 266 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 267 | { |
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[69] | 268 | if (_param->_have_port_ooo_engine_id) |
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| 269 | (*(_Reservation_station-> in_BYPASS_WRITE_OOO_ENGINE_ID [i])) (*( in_BYPASS_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 270 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_VAL [i])) (*( in_BYPASS_WRITE_GPR_VAL [i])); |
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| 271 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_NUM_REG [i])) (*( in_BYPASS_WRITE_GPR_NUM_REG [i])); |
---|
| 272 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_DATA [i])) (*( in_BYPASS_WRITE_GPR_DATA [i])); |
---|
| 273 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_VAL [i])) (*( in_BYPASS_WRITE_SPR_VAL [i])); |
---|
| 274 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_NUM_REG [i])) (*( in_BYPASS_WRITE_SPR_NUM_REG [i])); |
---|
| 275 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_DATA [i])) (*( in_BYPASS_WRITE_SPR_DATA [i])); |
---|
| 276 | } |
---|
| 277 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
| 278 | { |
---|
| 279 | (*(_Reservation_station-> in_BYPASS_MEMORY_VAL [i])) (*( in_BYPASS_MEMORY_VAL [i])); |
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[69] | 280 | if (_param->_have_port_ooo_engine_id) |
---|
| 281 | (*(_Reservation_station-> in_BYPASS_MEMORY_OOO_ENGINE_ID [i])) (*( in_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
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[55] | 282 | (*(_Reservation_station-> in_BYPASS_MEMORY_NUM_REG [i])) (*( in_BYPASS_MEMORY_NUM_REG [i])); |
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| 283 | (*(_Reservation_station-> in_BYPASS_MEMORY_DATA [i])) (*( in_BYPASS_MEMORY_DATA [i])); |
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| 284 | } |
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| 285 | |
---|
| 286 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 287 | Time * _time = new Time(); |
---|
| 288 | |
---|
| 289 | /******************************************************** |
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| 290 | * Simulation - Begin |
---|
| 291 | ********************************************************/ |
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| 292 | |
---|
| 293 | // Initialisation |
---|
| 294 | |
---|
| 295 | const uint32_t nb_request = _param->_nb_packet; |
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[69] | 296 | const uint32_t seed = 0; |
---|
| 297 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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[55] | 298 | srand(seed); |
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| 299 | |
---|
[69] | 300 | Tcontext_t _ooo_engine_id [nb_request]; |
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[55] | 301 | Tcontrol_t _read_ra [nb_request]; |
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| 302 | Tgeneral_address_t _num_reg_ra [nb_request]; |
---|
| 303 | Tcontrol_t _read_rb [nb_request]; |
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| 304 | Tgeneral_address_t _num_reg_rb [nb_request]; |
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| 305 | Tcontrol_t _read_rc [nb_request]; |
---|
| 306 | Tspecial_address_t _num_reg_rc [nb_request]; |
---|
| 307 | |
---|
| 308 | // emulation of registerFile |
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[69] | 309 | Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; |
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| 310 | Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; |
---|
| 311 | Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; |
---|
| 312 | Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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[55] | 313 | |
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| 314 | SC_START(0); |
---|
| 315 | |
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| 316 | LABEL("Initialisation"); |
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[69] | 317 | in_INSERT_VAL ->write(0); |
---|
| 318 | for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) |
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| 319 | in_RETIRE_ACK [i]->write(0); |
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[55] | 320 | for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) |
---|
| 321 | in_GPR_WRITE_VAL [i]->write(0); |
---|
| 322 | for (uint32_t i=0; i<_param->_nb_spr_write ; i++) |
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| 323 | in_SPR_WRITE_VAL [i]->write(0); |
---|
| 324 | for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) |
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| 325 | { |
---|
| 326 | in_BYPASS_WRITE_GPR_VAL [i]->write(0); |
---|
| 327 | in_BYPASS_WRITE_SPR_VAL [i]->write(0); |
---|
| 328 | } |
---|
| 329 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 330 | in_BYPASS_MEMORY_VAL [i]->write(0); |
---|
| 331 | |
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| 332 | in_NRESET->write(0); |
---|
| 333 | SC_START(5); |
---|
| 334 | in_NRESET->write(1); |
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| 335 | |
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| 336 | LABEL("Loop of Test"); |
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| 337 | |
---|
| 338 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 339 | { |
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[82] | 340 | LABEL("Iteration %d",iteration); |
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[55] | 341 | |
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| 342 | int32_t percent_transaction_queue_in = (rand()%50)+25; |
---|
| 343 | int32_t percent_transaction_queue_out = (rand()%50)+25; |
---|
| 344 | int32_t percent_registerfile_valid = (rand()%50)+25; |
---|
| 345 | int32_t percent_transaction_registerfile = (rand()%50)+25; |
---|
| 346 | int32_t percent_transaction_bypass = (rand()%50)+25; |
---|
| 347 | |
---|
| 348 | LABEL("Initialisation"); |
---|
| 349 | |
---|
| 350 | for (uint32_t i=0; i<nb_request; i++) |
---|
| 351 | { |
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[69] | 352 | _ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ; |
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[55] | 353 | _read_ra [i] = rand()% 2 ; |
---|
| 354 | _num_reg_ra [i] = rand()% _param->_nb_general_register ; |
---|
| 355 | _read_rb [i] = rand()% 2 ; |
---|
| 356 | _num_reg_rb [i] = rand()% _param->_nb_general_register ; |
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| 357 | _read_rc [i] = rand()% 2 ; |
---|
| 358 | _num_reg_rc [i] = rand()% _param->_nb_special_register ; |
---|
| 359 | } |
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| 360 | |
---|
| 361 | // emulation of registerFile |
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[69] | 362 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
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[55] | 363 | { |
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| 364 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 365 | { |
---|
| 366 | _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
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[75] | 367 | _gpr [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[55] | 368 | } |
---|
| 369 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 370 | { |
---|
| 371 | _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
[75] | 372 | _spr [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
[55] | 373 | } |
---|
| 374 | } |
---|
| 375 | // End initialisation ....... |
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| 376 | |
---|
| 377 | uint32_t request_in = 0; |
---|
| 378 | uint32_t request_out = 0; |
---|
| 379 | bool request_out_wait [nb_request]; |
---|
| 380 | |
---|
| 381 | for (uint32_t i=0; i<nb_request; i++) |
---|
| 382 | request_out_wait [i] = true; |
---|
[69] | 383 | |
---|
| 384 | bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
| 385 | bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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| 386 | bool need_gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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| 387 | bool need_spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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[55] | 388 | |
---|
[69] | 389 | |
---|
| 390 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
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| 391 | { |
---|
| 392 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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| 393 | need_gpr [j][i] = false; |
---|
| 394 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
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| 395 | need_spr [j][i] = false; |
---|
| 396 | } |
---|
| 397 | |
---|
[55] | 398 | while (request_out < nb_request) |
---|
| 399 | { |
---|
[69] | 400 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
[55] | 401 | { |
---|
[69] | 402 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 403 | can_gpr_use [j][i] = true; |
---|
| 404 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 405 | can_spr_use [j][i] = true; |
---|
[55] | 406 | } |
---|
[69] | 407 | |
---|
| 408 | Tcontrol_t insert_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); |
---|
| 409 | Tcontext_t insert_ooo_engine_id; |
---|
| 410 | Tgeneral_address_t insert_num_reg_ra; |
---|
| 411 | Tgeneral_address_t insert_num_reg_rb; |
---|
| 412 | Tspecial_address_t insert_num_reg_rc; |
---|
| 413 | |
---|
| 414 | in_INSERT_VAL ->write(insert_val); |
---|
| 415 | if (insert_val) |
---|
[55] | 416 | { |
---|
[69] | 417 | bool data_val; |
---|
| 418 | insert_ooo_engine_id = _ooo_engine_id [request_in]; |
---|
| 419 | insert_num_reg_ra = _num_reg_ra [request_in]; |
---|
| 420 | insert_num_reg_rb = _num_reg_rb [request_in]; |
---|
| 421 | insert_num_reg_rc = _num_reg_rc [request_in]; |
---|
[55] | 422 | |
---|
[69] | 423 | if (_param->_have_port_context_id) |
---|
| 424 | in_INSERT_CONTEXT_ID ->write((2*insert_ooo_engine_id)%_param->_nb_context ); |
---|
| 425 | if (_param->_have_port_front_end_id) |
---|
| 426 | in_INSERT_FRONT_END_ID ->write((3*insert_ooo_engine_id)%_param->_nb_front_end); |
---|
| 427 | if (_param->_have_port_ooo_engine_id) |
---|
| 428 | in_INSERT_OOO_ENGINE_ID ->write(insert_ooo_engine_id); |
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[88] | 429 | if (_param->_have_port_rob_ptr) |
---|
[69] | 430 | in_INSERT_ROB_ID ->write(request_in); |
---|
| 431 | in_INSERT_OPERATION ->write(0); |
---|
| 432 | in_INSERT_TYPE ->write(0); |
---|
[76] | 433 | in_INSERT_STORE_QUEUE_PTR_WRITE->write(0); |
---|
[78] | 434 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 435 | in_INSERT_LOAD_QUEUE_PTR_WRITE ->write(0); |
---|
[69] | 436 | in_INSERT_HAS_IMMEDIAT->write(0); |
---|
| 437 | in_INSERT_IMMEDIAT ->write(0); |
---|
| 438 | // in_INSERT_READ_RA ->write(_read_ra[request_in]); |
---|
| 439 | data_val = not(_read_ra[request_in]) or _gpr_val[insert_num_reg_ra][insert_ooo_engine_id]; |
---|
[55] | 440 | |
---|
[69] | 441 | need_gpr [insert_ooo_engine_id][insert_num_reg_ra] |= not data_val; |
---|
[55] | 442 | |
---|
[69] | 443 | in_INSERT_NUM_REG_RA ->write(insert_num_reg_ra); |
---|
| 444 | in_INSERT_DATA_RA_VAL ->write(data_val); |
---|
| 445 | in_INSERT_DATA_RA ->write((data_val)?_gpr[insert_num_reg_ra][insert_ooo_engine_id]:0); |
---|
| 446 | // in_INSERT_READ_RB ->write(_read_rb[request_in]); |
---|
| 447 | data_val = not(_read_rb[request_in]) or _gpr_val[insert_num_reg_rb][insert_ooo_engine_id]; |
---|
| 448 | |
---|
| 449 | need_gpr [insert_ooo_engine_id][insert_num_reg_rb] |= not data_val; |
---|
| 450 | |
---|
| 451 | in_INSERT_NUM_REG_RB ->write(insert_num_reg_rb); |
---|
| 452 | in_INSERT_DATA_RB_VAL ->write(data_val); |
---|
| 453 | in_INSERT_DATA_RB ->write((data_val)?_gpr[insert_num_reg_rb][insert_ooo_engine_id]:0); |
---|
| 454 | // in_INSERT_READ_RC ->write(_read_rc[request_in]); |
---|
| 455 | data_val = not(_read_rc[request_in]) or _spr_val[insert_num_reg_rc][insert_ooo_engine_id]; |
---|
| 456 | |
---|
| 457 | need_spr [insert_ooo_engine_id][insert_num_reg_rc] |= not data_val; |
---|
| 458 | |
---|
| 459 | in_INSERT_NUM_REG_RC ->write(insert_num_reg_rc); |
---|
| 460 | in_INSERT_DATA_RC_VAL ->write(data_val); |
---|
| 461 | in_INSERT_DATA_RC ->write((data_val)?_spr[insert_num_reg_rc][insert_ooo_engine_id]:0); |
---|
| 462 | in_INSERT_WRITE_RD ->write(0); |
---|
| 463 | in_INSERT_NUM_REG_RD ->write(0); |
---|
| 464 | in_INSERT_WRITE_RE ->write(0); |
---|
| 465 | in_INSERT_NUM_REG_RE ->write(0); |
---|
| 466 | |
---|
| 467 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_ra] = false; |
---|
| 468 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_rb] = false; |
---|
| 469 | can_spr_use [insert_ooo_engine_id][insert_num_reg_rc] = false; |
---|
| 470 | } |
---|
| 471 | |
---|
| 472 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 473 | in_RETIRE_ACK[i]->write((rand()%100)<percent_transaction_queue_out); |
---|
| 474 | |
---|
[55] | 475 | LABEL("Bypass Network :"); |
---|
| 476 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 477 | { |
---|
| 478 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 479 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 480 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
[75] | 481 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[69] | 482 | |
---|
| 483 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
[55] | 484 | |
---|
[69] | 485 | in_GPR_WRITE_VAL [i]->write(val); |
---|
| 486 | if (_param->_have_port_ooo_engine_id) |
---|
| 487 | in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 488 | in_GPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 489 | in_GPR_WRITE_DATA [i]->write(data); |
---|
| 490 | |
---|
[55] | 491 | if (val) |
---|
| 492 | { |
---|
[82] | 493 | LABEL(" * GPR_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
---|
[69] | 494 | can_gpr_use [ooo_engine][num_reg] = false; |
---|
| 495 | need_gpr [ooo_engine][num_reg] = false; |
---|
| 496 | |
---|
| 497 | |
---|
| 498 | _gpr [num_reg][ooo_engine] = data; |
---|
| 499 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 500 | } |
---|
| 501 | } |
---|
| 502 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 503 | { |
---|
| 504 | Tspecial_address_t num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 505 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 506 | Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
[75] | 507 | Tspecial_data_t data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
[55] | 508 | |
---|
[69] | 509 | val = (val and can_spr_use [ooo_engine][num_reg] and need_spr[ooo_engine][num_reg]); |
---|
| 510 | |
---|
| 511 | in_SPR_WRITE_VAL [i]->write(val); |
---|
| 512 | if (_param->_have_port_ooo_engine_id) |
---|
| 513 | in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 514 | in_SPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 515 | in_SPR_WRITE_DATA [i]->write(data); |
---|
| 516 | |
---|
[55] | 517 | if (val == 1) |
---|
| 518 | { |
---|
[82] | 519 | LABEL(" * SPR_WRITE [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
---|
| 520 | |
---|
[69] | 521 | can_spr_use [ooo_engine][num_reg] = false; |
---|
| 522 | need_spr[ooo_engine][num_reg] = false; |
---|
| 523 | |
---|
| 524 | _spr [num_reg][ooo_engine] = data; |
---|
| 525 | _spr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 526 | } |
---|
| 527 | } |
---|
| 528 | |
---|
| 529 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
| 530 | { |
---|
[69] | 531 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 532 | if (_param->_have_port_ooo_engine_id) |
---|
| 533 | in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
[55] | 534 | |
---|
| 535 | Tgeneral_address_t gpr_num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 536 | Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
[75] | 537 | Tgeneral_data_t gpr_data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[55] | 538 | |
---|
[69] | 539 | gpr_val = (gpr_val and can_gpr_use [ooo_engine][gpr_num_reg] and need_gpr[ooo_engine][gpr_num_reg]); |
---|
| 540 | |
---|
[55] | 541 | in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); |
---|
| 542 | in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); |
---|
| 543 | in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); |
---|
| 544 | |
---|
| 545 | if (gpr_val) |
---|
| 546 | { |
---|
[82] | 547 | LABEL(" * BYPASS_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,gpr_num_reg,ooo_engine,gpr_data); |
---|
[69] | 548 | can_gpr_use [ooo_engine][gpr_num_reg] = false; |
---|
| 549 | need_gpr[ooo_engine][gpr_num_reg] = false; |
---|
| 550 | |
---|
| 551 | _gpr [gpr_num_reg][ooo_engine] = gpr_data; |
---|
| 552 | _gpr_val [gpr_num_reg][ooo_engine] = 1; |
---|
[55] | 553 | } |
---|
| 554 | |
---|
| 555 | Tspecial_address_t spr_num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 556 | Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
[75] | 557 | Tspecial_data_t spr_data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
[55] | 558 | |
---|
[69] | 559 | spr_val = (spr_val and can_spr_use [ooo_engine][spr_num_reg] and need_spr[ooo_engine][spr_num_reg]); |
---|
| 560 | |
---|
[55] | 561 | in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); |
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| 562 | in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); |
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| 563 | in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); |
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| 564 | |
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| 565 | if (spr_val) |
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| 566 | { |
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[82] | 567 | LABEL(" * BYPASS_WRITE [%d] - spr[%d][%d] <- 0x%x",i,spr_num_reg,ooo_engine,spr_data); |
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| 568 | |
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[69] | 569 | can_spr_use [ooo_engine][spr_num_reg] = false; |
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| 570 | need_spr[ooo_engine][spr_num_reg] = false; |
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| 571 | |
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| 572 | _spr [spr_num_reg][ooo_engine] = spr_data; |
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| 573 | _spr_val [spr_num_reg][ooo_engine] = 1; |
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[55] | 574 | } |
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| 575 | |
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| 576 | } |
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| 577 | |
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| 578 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 579 | { |
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[69] | 580 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
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| 581 | if (_param->_have_port_ooo_engine_id) |
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| 582 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); |
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[55] | 583 | |
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[69] | 584 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
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| 585 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
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[75] | 586 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
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[55] | 587 | |
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[69] | 588 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
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[55] | 589 | |
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[69] | 590 | in_BYPASS_MEMORY_VAL [i]->write(val); |
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| 591 | in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); |
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| 592 | in_BYPASS_MEMORY_DATA [i]->write(data); |
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| 593 | |
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| 594 | if (val) |
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[55] | 595 | { |
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[82] | 596 | LABEL(" * BYPASS_MEMORY [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
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| 597 | |
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[69] | 598 | can_gpr_use [ooo_engine][num_reg] = false; |
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| 599 | need_gpr [ooo_engine][num_reg] = false; |
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| 600 | |
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| 601 | _gpr [num_reg][ooo_engine] = data; |
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| 602 | _gpr_val [num_reg][ooo_engine] = 1; |
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[55] | 603 | } |
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| 604 | } |
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| 605 | SC_START(0); // to mealy function |
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| 606 | |
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[69] | 607 | // LABEL("Test INSERT : "+toString(in_INSERT_VAL->read())+","+toString(out_INSERT_ACK->read())); |
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| 608 | if (( in_INSERT_VAL->read() == 1) and |
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| 609 | (out_INSERT_ACK->read() == 1)) |
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[55] | 610 | { |
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[82] | 611 | LABEL("Accepted INSERT number : %d",request_in); |
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[55] | 612 | request_in ++; |
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| 613 | } |
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| 614 | |
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[69] | 615 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 616 | { |
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[82] | 617 | LABEL("Test RETIRE %d : %d,%d",i,out_RETIRE_VAL[i]->read(),in_RETIRE_ACK[i]->read()); |
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[69] | 618 | if ((out_RETIRE_VAL [i]->read() == 1) and |
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| 619 | ( in_RETIRE_ACK [i]->read() == 1)) |
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[55] | 620 | { |
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[69] | 621 | Tpacket_t rob_id; |
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[88] | 622 | if (_param->_have_port_rob_ptr) |
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[69] | 623 | rob_id = out_RETIRE_ROB_ID [i]->read(); |
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| 624 | else |
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| 625 | rob_id = 0; |
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[82] | 626 | LABEL("Accepted RETIRE [%d] number : %d, request number : %d",i,rob_id,request_out); |
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[69] | 627 | TEST(bool, request_out_wait [rob_id] , true); |
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[55] | 628 | |
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| 629 | request_out ++; |
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[69] | 630 | request_out_wait [rob_id] = false; |
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[55] | 631 | |
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[69] | 632 | Tcontext_t ooo_engine_id = _ooo_engine_id [rob_id]; |
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[55] | 633 | |
---|
[69] | 634 | if (_param->_have_port_context_id) |
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| 635 | TEST(Tcontext_t ,out_RETIRE_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); |
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| 636 | if (_param->_have_port_front_end_id) |
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| 637 | TEST(Tcontext_t ,out_RETIRE_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); |
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| 638 | if (_param->_have_port_ooo_engine_id) |
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| 639 | TEST(Tcontext_t ,out_RETIRE_OOO_ENGINE_ID[i]->read(),ooo_engine_id); |
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| 640 | |
---|
| 641 | if (_read_ra [rob_id]) |
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| 642 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RA [i]->read(),_gpr[_num_reg_ra[rob_id]][ooo_engine_id]); |
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[55] | 643 | |
---|
[69] | 644 | if (_read_rb [rob_id]) |
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| 645 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RB [i]->read(),_gpr[_num_reg_rb[rob_id]][ooo_engine_id]); |
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[55] | 646 | |
---|
[69] | 647 | if (_read_rc [rob_id]) |
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| 648 | TEST(Tspecial_data_t ,out_RETIRE_DATA_RC [i]->read(),_spr[_num_reg_rc[rob_id]][ooo_engine_id]); |
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| 649 | |
---|
| 650 | // need_gpr [ooo_engine_id][_num_reg_ra[rob_id]]= true; |
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| 651 | // need_gpr [ooo_engine_id][_num_reg_rb[rob_id]]= true; |
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| 652 | // need_spr [ooo_engine_id][_num_reg_rc[rob_id]]= true; |
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[55] | 653 | } |
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| 654 | } |
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| 655 | |
---|
| 656 | SC_START(1); |
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| 657 | } |
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| 658 | } |
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| 659 | |
---|
| 660 | /******************************************************** |
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| 661 | * Simulation - End |
---|
| 662 | ********************************************************/ |
---|
| 663 | |
---|
| 664 | TEST_OK ("End of Simulation"); |
---|
| 665 | delete _time; |
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| 666 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 667 | |
---|
| 668 | delete in_CLOCK ; |
---|
| 669 | delete in_NRESET; |
---|
| 670 | |
---|
[69] | 671 | delete in_INSERT_VAL ; |
---|
| 672 | delete out_INSERT_ACK ; |
---|
| 673 | if (_param->_have_port_context_id) |
---|
| 674 | delete in_INSERT_CONTEXT_ID ; |
---|
| 675 | if (_param->_have_port_front_end_id) |
---|
| 676 | delete in_INSERT_FRONT_END_ID ; |
---|
| 677 | if (_param->_have_port_ooo_engine_id) |
---|
| 678 | delete in_INSERT_OOO_ENGINE_ID ; |
---|
[88] | 679 | if (_param->_have_port_rob_ptr) |
---|
[69] | 680 | delete in_INSERT_ROB_ID ; |
---|
| 681 | delete in_INSERT_OPERATION ; |
---|
| 682 | delete in_INSERT_TYPE ; |
---|
[76] | 683 | delete in_INSERT_STORE_QUEUE_PTR_WRITE; |
---|
[78] | 684 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 685 | delete in_INSERT_LOAD_QUEUE_PTR_WRITE ; |
---|
[69] | 686 | delete in_INSERT_HAS_IMMEDIAT; |
---|
| 687 | delete in_INSERT_IMMEDIAT ; |
---|
| 688 | //delete in_INSERT_READ_RA ; |
---|
| 689 | delete in_INSERT_NUM_REG_RA ; |
---|
| 690 | delete in_INSERT_DATA_RA_VAL ; |
---|
| 691 | delete in_INSERT_DATA_RA ; |
---|
| 692 | //delete in_INSERT_READ_RB ; |
---|
| 693 | delete in_INSERT_NUM_REG_RB ; |
---|
| 694 | delete in_INSERT_DATA_RB_VAL ; |
---|
| 695 | delete in_INSERT_DATA_RB ; |
---|
| 696 | //delete in_INSERT_READ_RC ; |
---|
| 697 | delete in_INSERT_NUM_REG_RC ; |
---|
| 698 | delete in_INSERT_DATA_RC_VAL ; |
---|
| 699 | delete in_INSERT_DATA_RC ; |
---|
| 700 | delete in_INSERT_WRITE_RD ; |
---|
| 701 | delete in_INSERT_NUM_REG_RD ; |
---|
| 702 | delete in_INSERT_WRITE_RE ; |
---|
| 703 | delete in_INSERT_NUM_REG_RE ; |
---|
[55] | 704 | |
---|
[69] | 705 | delete [] out_RETIRE_VAL ; |
---|
| 706 | delete [] in_RETIRE_ACK ; |
---|
| 707 | if (_param->_have_port_context_id) |
---|
| 708 | delete [] out_RETIRE_CONTEXT_ID ; |
---|
| 709 | if (_param->_have_port_front_end_id) |
---|
| 710 | delete [] out_RETIRE_FRONT_END_ID; |
---|
| 711 | if (_param->_have_port_ooo_engine_id) |
---|
| 712 | delete [] out_RETIRE_OOO_ENGINE_ID ; |
---|
[88] | 713 | if (_param->_have_port_rob_ptr) |
---|
[69] | 714 | delete [] out_RETIRE_ROB_ID ; |
---|
| 715 | delete [] out_RETIRE_OPERATION ; |
---|
| 716 | delete [] out_RETIRE_TYPE ; |
---|
[76] | 717 | delete [] out_RETIRE_STORE_QUEUE_PTR_WRITE; |
---|
[78] | 718 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 719 | delete [] out_RETIRE_LOAD_QUEUE_PTR_WRITE ; |
---|
[69] | 720 | delete [] out_RETIRE_HAS_IMMEDIAT; |
---|
| 721 | delete [] out_RETIRE_IMMEDIAT ; |
---|
| 722 | delete [] out_RETIRE_DATA_RA ; |
---|
| 723 | delete [] out_RETIRE_DATA_RB ; |
---|
| 724 | delete [] out_RETIRE_DATA_RC ; |
---|
| 725 | delete [] out_RETIRE_WRITE_RD ; |
---|
| 726 | delete [] out_RETIRE_NUM_REG_RD ; |
---|
| 727 | delete [] out_RETIRE_WRITE_RE ; |
---|
| 728 | delete [] out_RETIRE_NUM_REG_RE ; |
---|
[55] | 729 | |
---|
| 730 | delete [] in_GPR_WRITE_VAL ; |
---|
[69] | 731 | if (_param->_have_port_ooo_engine_id) |
---|
| 732 | delete [] in_GPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 733 | delete [] in_GPR_WRITE_NUM_REG ; |
---|
| 734 | delete [] in_GPR_WRITE_DATA ; |
---|
| 735 | |
---|
| 736 | delete [] in_SPR_WRITE_VAL ; |
---|
[69] | 737 | if (_param->_have_port_ooo_engine_id) |
---|
| 738 | delete [] in_SPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 739 | delete [] in_SPR_WRITE_NUM_REG ; |
---|
| 740 | delete [] in_SPR_WRITE_DATA ; |
---|
| 741 | |
---|
[69] | 742 | if (_param->_have_port_ooo_engine_id) |
---|
| 743 | delete [] in_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
[55] | 744 | delete [] in_BYPASS_WRITE_GPR_VAL ; |
---|
| 745 | delete [] in_BYPASS_WRITE_GPR_NUM_REG; |
---|
| 746 | delete [] in_BYPASS_WRITE_GPR_DATA ; |
---|
| 747 | delete [] in_BYPASS_WRITE_SPR_VAL ; |
---|
| 748 | delete [] in_BYPASS_WRITE_SPR_NUM_REG; |
---|
| 749 | delete [] in_BYPASS_WRITE_SPR_DATA ; |
---|
| 750 | |
---|
| 751 | delete [] in_BYPASS_MEMORY_VAL ; |
---|
[69] | 752 | if (_param->_have_port_ooo_engine_id) |
---|
| 753 | delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
[55] | 754 | delete [] in_BYPASS_MEMORY_NUM_REG ; |
---|
| 755 | delete [] in_BYPASS_MEMORY_DATA ; |
---|
| 756 | #endif |
---|
| 757 | |
---|
| 758 | delete _Reservation_station; |
---|
| 759 | #ifdef STATISTICS |
---|
| 760 | delete _parameters_statistics; |
---|
| 761 | #endif |
---|
| 762 | } |
---|