[55] | 1 | /* |
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| 2 | * $Id: test.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/SelfTest/include/test.h" |
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| 10 | #include "Common/include/Test.h" |
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[75] | 11 | #include "Common/include/BitManipulation.h" |
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[55] | 12 | |
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[69] | 13 | #define NB_ITERATION 2 |
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| 14 | #define CYCLE_MAX (2048*NB_ITERATION) |
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[55] | 15 | |
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| 16 | #define LABEL(str) \ |
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| 17 | { \ |
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| 18 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ |
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| 19 | } while(0) |
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| 20 | |
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| 21 | static uint32_t cycle = 0; |
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| 22 | |
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| 23 | #define SC_START(cycle_offset) \ |
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| 24 | do \ |
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| 25 | { \ |
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| 26 | /*cout << "SC_START (begin)" << endl;*/ \ |
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| 27 | \ |
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| 28 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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| 29 | sc_start(cycle_offset); \ |
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| 30 | if (cycle_current != cycle) \ |
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| 31 | { \ |
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| 32 | cycle = cycle_current; \ |
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| 33 | cout << "##########[ cycle "<< cycle << " ]" << endl; \ |
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| 34 | } \ |
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| 35 | \ |
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| 36 | if (cycle_current > CYCLE_MAX) \ |
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| 37 | { \ |
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| 38 | TEST_KO("Maximal cycles Reached"); \ |
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| 39 | } \ |
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| 40 | /*cout << "SC_START (end )" << endl;*/ \ |
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| 41 | } while(0) |
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| 42 | |
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| 43 | void test (string name, |
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| 44 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Parameters * _param) |
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| 45 | { |
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| 46 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 47 | |
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| 48 | #ifdef STATISTICS |
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| 49 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 50 | #endif |
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| 51 | |
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| 52 | Reservation_station * _Reservation_station = new Reservation_station (name.c_str(), |
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| 53 | #ifdef STATISTICS |
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| 54 | _parameters_statistics, |
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| 55 | #endif |
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| 56 | _param); |
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| 57 | |
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| 58 | #ifdef SYSTEMC |
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| 59 | /********************************************************************* |
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| 60 | * Déclarations des signaux |
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| 61 | *********************************************************************/ |
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| 62 | string rename = ""; |
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| 63 | |
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| 64 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 65 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 66 | |
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[69] | 67 | sc_signal<Tcontrol_t > * in_INSERT_VAL = new sc_signal<Tcontrol_t >; |
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| 68 | sc_signal<Tcontrol_t > * out_INSERT_ACK = new sc_signal<Tcontrol_t >; |
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| 69 | sc_signal<Tcontext_t > * in_INSERT_CONTEXT_ID = new sc_signal<Tcontext_t >; |
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| 70 | sc_signal<Tcontext_t > * in_INSERT_FRONT_END_ID = new sc_signal<Tcontext_t >; |
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| 71 | sc_signal<Tcontext_t > * in_INSERT_OOO_ENGINE_ID = new sc_signal<Tcontext_t >; |
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| 72 | sc_signal<Tpacket_t > * in_INSERT_ROB_ID = new sc_signal<Tpacket_t >; |
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| 73 | sc_signal<Toperation_t > * in_INSERT_OPERATION = new sc_signal<Toperation_t >; |
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| 74 | sc_signal<Ttype_t > * in_INSERT_TYPE = new sc_signal<Ttype_t >; |
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[76] | 75 | sc_signal<Tlsq_ptr_t > * in_INSERT_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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| 76 | sc_signal<Tlsq_ptr_t > * in_INSERT_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t>; |
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[69] | 77 | sc_signal<Tcontrol_t > * in_INSERT_HAS_IMMEDIAT = new sc_signal<Tcontrol_t >; |
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| 78 | sc_signal<Tgeneral_data_t > * in_INSERT_IMMEDIAT = new sc_signal<Tgeneral_data_t >; |
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| 79 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RA = new sc_signal<Tcontrol_t >; |
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| 80 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RA = new sc_signal<Tgeneral_address_t>; |
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| 81 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RA_VAL = new sc_signal<Tcontrol_t >; |
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| 82 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RA = new sc_signal<Tgeneral_data_t >; |
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| 83 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RB = new sc_signal<Tcontrol_t >; |
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| 84 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RB = new sc_signal<Tgeneral_address_t>; |
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| 85 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RB_VAL = new sc_signal<Tcontrol_t >; |
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| 86 | sc_signal<Tgeneral_data_t > * in_INSERT_DATA_RB = new sc_signal<Tgeneral_data_t >; |
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| 87 | //sc_signal<Tcontrol_t > * in_INSERT_READ_RC = new sc_signal<Tcontrol_t >; |
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| 88 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RC = new sc_signal<Tspecial_address_t>; |
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| 89 | sc_signal<Tcontrol_t > * in_INSERT_DATA_RC_VAL = new sc_signal<Tcontrol_t >; |
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| 90 | sc_signal<Tspecial_data_t > * in_INSERT_DATA_RC = new sc_signal<Tspecial_data_t >; |
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| 91 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RD = new sc_signal<Tcontrol_t >; |
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| 92 | sc_signal<Tgeneral_address_t> * in_INSERT_NUM_REG_RD = new sc_signal<Tgeneral_address_t>; |
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| 93 | sc_signal<Tcontrol_t > * in_INSERT_WRITE_RE = new sc_signal<Tcontrol_t >; |
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| 94 | sc_signal<Tspecial_address_t> * in_INSERT_NUM_REG_RE = new sc_signal<Tspecial_address_t>; |
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[55] | 95 | |
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[69] | 96 | sc_signal<Tcontrol_t > ** out_RETIRE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 97 | sc_signal<Tcontrol_t > ** in_RETIRE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 98 | sc_signal<Tcontext_t > ** out_RETIRE_CONTEXT_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 99 | sc_signal<Tcontext_t > ** out_RETIRE_FRONT_END_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 100 | sc_signal<Tcontext_t > ** out_RETIRE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_inst_retire]; |
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| 101 | sc_signal<Tpacket_t > ** out_RETIRE_ROB_ID = new sc_signal<Tpacket_t > * [_param->_nb_inst_retire]; |
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| 102 | sc_signal<Toperation_t > ** out_RETIRE_OPERATION = new sc_signal<Toperation_t > * [_param->_nb_inst_retire]; |
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| 103 | sc_signal<Ttype_t > ** out_RETIRE_TYPE = new sc_signal<Ttype_t > * [_param->_nb_inst_retire]; |
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[76] | 104 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_STORE_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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| 105 | sc_signal<Tlsq_ptr_t > ** out_RETIRE_LOAD_QUEUE_PTR_WRITE = new sc_signal<Tlsq_ptr_t> * [_param->_nb_inst_retire]; |
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[69] | 106 | sc_signal<Tcontrol_t > ** out_RETIRE_HAS_IMMEDIAT = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 107 | sc_signal<Tgeneral_data_t > ** out_RETIRE_IMMEDIAT = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 108 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RA = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 109 | sc_signal<Tgeneral_data_t > ** out_RETIRE_DATA_RB = new sc_signal<Tgeneral_data_t > * [_param->_nb_inst_retire]; |
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| 110 | sc_signal<Tspecial_data_t > ** out_RETIRE_DATA_RC = new sc_signal<Tspecial_data_t > * [_param->_nb_inst_retire]; |
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| 111 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RD = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 112 | sc_signal<Tgeneral_address_t> ** out_RETIRE_NUM_REG_RD = new sc_signal<Tgeneral_address_t> * [_param->_nb_inst_retire]; |
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| 113 | sc_signal<Tcontrol_t > ** out_RETIRE_WRITE_RE = new sc_signal<Tcontrol_t > * [_param->_nb_inst_retire]; |
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| 114 | sc_signal<Tspecial_address_t> ** out_RETIRE_NUM_REG_RE = new sc_signal<Tspecial_address_t> * [_param->_nb_inst_retire]; |
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[55] | 115 | |
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[69] | 116 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 117 | { |
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[69] | 118 | out_RETIRE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 119 | in_RETIRE_ACK [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 120 | out_RETIRE_CONTEXT_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 121 | out_RETIRE_FRONT_END_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 122 | out_RETIRE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 123 | out_RETIRE_ROB_ID [i] = new sc_signal<Tpacket_t > (rename.c_str()); |
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| 124 | out_RETIRE_OPERATION [i] = new sc_signal<Toperation_t > (rename.c_str()); |
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| 125 | out_RETIRE_TYPE [i] = new sc_signal<Ttype_t > (rename.c_str()); |
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[76] | 126 | out_RETIRE_STORE_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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| 127 | out_RETIRE_LOAD_QUEUE_PTR_WRITE [i] = new sc_signal<Tlsq_ptr_t> (rename.c_str()); |
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[69] | 128 | out_RETIRE_HAS_IMMEDIAT [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 129 | out_RETIRE_IMMEDIAT [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 130 | out_RETIRE_DATA_RA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 131 | out_RETIRE_DATA_RB [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 132 | out_RETIRE_DATA_RC [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 133 | out_RETIRE_WRITE_RD [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 134 | out_RETIRE_NUM_REG_RD [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 135 | out_RETIRE_WRITE_RE [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 136 | out_RETIRE_NUM_REG_RE [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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[55] | 137 | } |
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| 138 | |
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[69] | 139 | sc_signal<Tcontrol_t > ** in_GPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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| 140 | sc_signal<Tcontext_t > ** in_GPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_write]; |
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| 141 | sc_signal<Tgeneral_address_t> ** in_GPR_WRITE_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_write]; |
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| 142 | sc_signal<Tgeneral_data_t > ** in_GPR_WRITE_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_write]; |
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[55] | 143 | |
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| 144 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 145 | { |
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[69] | 146 | in_GPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 147 | in_GPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 148 | in_GPR_WRITE_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 149 | in_GPR_WRITE_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 150 | } |
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| 151 | |
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[69] | 152 | sc_signal<Tcontrol_t > ** in_SPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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| 153 | sc_signal<Tcontext_t > ** in_SPR_WRITE_OOO_ENGINE_ID= new sc_signal<Tcontext_t > * [_param->_nb_spr_write]; |
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| 154 | sc_signal<Tspecial_address_t> ** in_SPR_WRITE_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_write]; |
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| 155 | sc_signal<Tspecial_data_t > ** in_SPR_WRITE_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_write]; |
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[55] | 156 | |
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| 157 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 158 | { |
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[69] | 159 | in_SPR_WRITE_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 160 | in_SPR_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 161 | in_SPR_WRITE_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 162 | in_SPR_WRITE_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 163 | } |
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| 164 | |
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[69] | 165 | sc_signal<Tcontext_t > ** in_BYPASS_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_write]; |
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| 166 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_GPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 167 | sc_signal<Tgeneral_address_t> ** in_BYPASS_WRITE_GPR_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_write]; |
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| 168 | sc_signal<Tgeneral_data_t > ** in_BYPASS_WRITE_GPR_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_write]; |
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| 169 | sc_signal<Tcontrol_t > ** in_BYPASS_WRITE_SPR_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_write]; |
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| 170 | sc_signal<Tspecial_address_t> ** in_BYPASS_WRITE_SPR_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_bypass_write]; |
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| 171 | sc_signal<Tspecial_data_t > ** in_BYPASS_WRITE_SPR_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_bypass_write]; |
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[55] | 172 | |
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| 173 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 174 | { |
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[69] | 175 | in_BYPASS_WRITE_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 176 | in_BYPASS_WRITE_GPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 177 | in_BYPASS_WRITE_GPR_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 178 | in_BYPASS_WRITE_GPR_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 179 | in_BYPASS_WRITE_SPR_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 180 | in_BYPASS_WRITE_SPR_NUM_REG [i] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 181 | in_BYPASS_WRITE_SPR_DATA [i] = new sc_signal<Tspecial_data_t > (rename.c_str()); |
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[55] | 182 | } |
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[69] | 183 | sc_signal<Tcontrol_t > ** in_BYPASS_MEMORY_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_bypass_memory]; |
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| 184 | sc_signal<Tcontext_t > ** in_BYPASS_MEMORY_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_bypass_memory]; |
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| 185 | sc_signal<Tgeneral_address_t> ** in_BYPASS_MEMORY_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_bypass_memory]; |
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| 186 | sc_signal<Tgeneral_data_t > ** in_BYPASS_MEMORY_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_bypass_memory]; |
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[55] | 187 | |
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| 188 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 189 | { |
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[69] | 190 | in_BYPASS_MEMORY_VAL [i] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 191 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i] = new sc_signal<Tcontext_t > (rename.c_str()); |
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| 192 | in_BYPASS_MEMORY_NUM_REG [i] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 193 | in_BYPASS_MEMORY_DATA [i] = new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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[55] | 194 | } |
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| 195 | |
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| 196 | /******************************************************** |
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| 197 | * Instanciation |
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| 198 | ********************************************************/ |
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| 199 | |
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| 200 | cout << "<" << name << "> Instanciation of _Reservation_station" << endl; |
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| 201 | |
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| 202 | (*(_Reservation_station->in_CLOCK)) (*(in_CLOCK)); |
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| 203 | (*(_Reservation_station->in_NRESET)) (*(in_NRESET)); |
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| 204 | |
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[69] | 205 | (*(_Reservation_station-> in_INSERT_VAL )) (*( in_INSERT_VAL )); |
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| 206 | (*(_Reservation_station->out_INSERT_ACK )) (*(out_INSERT_ACK )); |
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| 207 | if (_param->_have_port_context_id) |
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| 208 | (*(_Reservation_station-> in_INSERT_CONTEXT_ID )) (*( in_INSERT_CONTEXT_ID )); |
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| 209 | if (_param->_have_port_front_end_id) |
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| 210 | (*(_Reservation_station-> in_INSERT_FRONT_END_ID )) (*( in_INSERT_FRONT_END_ID )); |
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| 211 | if (_param->_have_port_ooo_engine_id) |
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| 212 | (*(_Reservation_station-> in_INSERT_OOO_ENGINE_ID )) (*( in_INSERT_OOO_ENGINE_ID )); |
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| 213 | if (_param->_have_port_rob_id) |
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| 214 | (*(_Reservation_station-> in_INSERT_ROB_ID )) (*( in_INSERT_ROB_ID )); |
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| 215 | (*(_Reservation_station-> in_INSERT_OPERATION )) (*( in_INSERT_OPERATION )); |
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| 216 | (*(_Reservation_station-> in_INSERT_TYPE )) (*( in_INSERT_TYPE )); |
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[76] | 217 | (*(_Reservation_station-> in_INSERT_STORE_QUEUE_PTR_WRITE)) (*( in_INSERT_STORE_QUEUE_PTR_WRITE)); |
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[78] | 218 | if (_param->_have_port_load_queue_ptr) |
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[76] | 219 | (*(_Reservation_station-> in_INSERT_LOAD_QUEUE_PTR_WRITE )) (*( in_INSERT_LOAD_QUEUE_PTR_WRITE )); |
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[69] | 220 | (*(_Reservation_station-> in_INSERT_HAS_IMMEDIAT )) (*( in_INSERT_HAS_IMMEDIAT )); |
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| 221 | (*(_Reservation_station-> in_INSERT_IMMEDIAT )) (*( in_INSERT_IMMEDIAT )); |
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| 222 | // (*(_Reservation_station-> in_INSERT_READ_RA )) (*( in_INSERT_READ_RA )); |
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| 223 | (*(_Reservation_station-> in_INSERT_NUM_REG_RA )) (*( in_INSERT_NUM_REG_RA )); |
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| 224 | (*(_Reservation_station-> in_INSERT_DATA_RA_VAL )) (*( in_INSERT_DATA_RA_VAL )); |
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| 225 | (*(_Reservation_station-> in_INSERT_DATA_RA )) (*( in_INSERT_DATA_RA )); |
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| 226 | // (*(_Reservation_station-> in_INSERT_READ_RB )) (*( in_INSERT_READ_RB )); |
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| 227 | (*(_Reservation_station-> in_INSERT_NUM_REG_RB )) (*( in_INSERT_NUM_REG_RB )); |
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| 228 | (*(_Reservation_station-> in_INSERT_DATA_RB_VAL )) (*( in_INSERT_DATA_RB_VAL )); |
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| 229 | (*(_Reservation_station-> in_INSERT_DATA_RB )) (*( in_INSERT_DATA_RB )); |
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| 230 | // (*(_Reservation_station-> in_INSERT_READ_RC )) (*( in_INSERT_READ_RC )); |
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| 231 | (*(_Reservation_station-> in_INSERT_NUM_REG_RC )) (*( in_INSERT_NUM_REG_RC )); |
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| 232 | (*(_Reservation_station-> in_INSERT_DATA_RC_VAL )) (*( in_INSERT_DATA_RC_VAL )); |
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| 233 | (*(_Reservation_station-> in_INSERT_DATA_RC )) (*( in_INSERT_DATA_RC )); |
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| 234 | (*(_Reservation_station-> in_INSERT_WRITE_RD )) (*( in_INSERT_WRITE_RD )); |
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| 235 | (*(_Reservation_station-> in_INSERT_NUM_REG_RD )) (*( in_INSERT_NUM_REG_RD )); |
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| 236 | (*(_Reservation_station-> in_INSERT_WRITE_RE )) (*( in_INSERT_WRITE_RE )); |
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| 237 | (*(_Reservation_station-> in_INSERT_NUM_REG_RE )) (*( in_INSERT_NUM_REG_RE )); |
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[55] | 238 | |
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[69] | 239 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 240 | { |
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[69] | 241 | (*(_Reservation_station->out_RETIRE_VAL [i])) (*(out_RETIRE_VAL [i])); |
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| 242 | (*(_Reservation_station-> in_RETIRE_ACK [i])) (*( in_RETIRE_ACK [i])); |
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| 243 | if (_param->_have_port_context_id) |
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| 244 | (*(_Reservation_station->out_RETIRE_CONTEXT_ID [i])) (*(out_RETIRE_CONTEXT_ID [i])); |
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| 245 | if (_param->_have_port_front_end_id) |
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| 246 | (*(_Reservation_station->out_RETIRE_FRONT_END_ID [i])) (*(out_RETIRE_FRONT_END_ID [i])); |
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| 247 | if (_param->_have_port_ooo_engine_id) |
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| 248 | (*(_Reservation_station->out_RETIRE_OOO_ENGINE_ID [i])) (*(out_RETIRE_OOO_ENGINE_ID [i])); |
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| 249 | if (_param->_have_port_rob_id) |
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| 250 | (*(_Reservation_station->out_RETIRE_ROB_ID [i])) (*(out_RETIRE_ROB_ID [i])); |
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| 251 | (*(_Reservation_station->out_RETIRE_OPERATION [i])) (*(out_RETIRE_OPERATION [i])); |
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| 252 | (*(_Reservation_station->out_RETIRE_TYPE [i])) (*(out_RETIRE_TYPE [i])); |
---|
[76] | 253 | (*(_Reservation_station->out_RETIRE_STORE_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_STORE_QUEUE_PTR_WRITE [i])); |
---|
[78] | 254 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 255 | (*(_Reservation_station->out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])) (*(out_RETIRE_LOAD_QUEUE_PTR_WRITE [i])); |
---|
[69] | 256 | (*(_Reservation_station->out_RETIRE_HAS_IMMEDIAT [i])) (*(out_RETIRE_HAS_IMMEDIAT [i])); |
---|
| 257 | (*(_Reservation_station->out_RETIRE_IMMEDIAT [i])) (*(out_RETIRE_IMMEDIAT [i])); |
---|
| 258 | (*(_Reservation_station->out_RETIRE_DATA_RA [i])) (*(out_RETIRE_DATA_RA [i])); |
---|
| 259 | (*(_Reservation_station->out_RETIRE_DATA_RB [i])) (*(out_RETIRE_DATA_RB [i])); |
---|
| 260 | (*(_Reservation_station->out_RETIRE_DATA_RC [i])) (*(out_RETIRE_DATA_RC [i])); |
---|
| 261 | (*(_Reservation_station->out_RETIRE_WRITE_RD [i])) (*(out_RETIRE_WRITE_RD [i])); |
---|
| 262 | (*(_Reservation_station->out_RETIRE_NUM_REG_RD [i])) (*(out_RETIRE_NUM_REG_RD [i])); |
---|
| 263 | (*(_Reservation_station->out_RETIRE_WRITE_RE [i])) (*(out_RETIRE_WRITE_RE [i])); |
---|
| 264 | (*(_Reservation_station->out_RETIRE_NUM_REG_RE [i])) (*(out_RETIRE_NUM_REG_RE [i])); |
---|
[55] | 265 | } |
---|
| 266 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 267 | { |
---|
| 268 | (*(_Reservation_station-> in_GPR_WRITE_VAL [i])) (*( in_GPR_WRITE_VAL [i])); |
---|
[69] | 269 | if (_param->_have_port_ooo_engine_id) |
---|
| 270 | (*(_Reservation_station-> in_GPR_WRITE_OOO_ENGINE_ID [i])) (*( in_GPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 271 | (*(_Reservation_station-> in_GPR_WRITE_NUM_REG [i])) (*( in_GPR_WRITE_NUM_REG [i])); |
---|
| 272 | (*(_Reservation_station-> in_GPR_WRITE_DATA [i])) (*( in_GPR_WRITE_DATA [i])); |
---|
| 273 | } |
---|
| 274 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 275 | { |
---|
| 276 | (*(_Reservation_station-> in_SPR_WRITE_VAL [i])) (*( in_SPR_WRITE_VAL [i])); |
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[69] | 277 | if (_param->_have_port_ooo_engine_id) |
---|
| 278 | (*(_Reservation_station-> in_SPR_WRITE_OOO_ENGINE_ID [i])) (*( in_SPR_WRITE_OOO_ENGINE_ID [i])); |
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[55] | 279 | (*(_Reservation_station-> in_SPR_WRITE_NUM_REG [i])) (*( in_SPR_WRITE_NUM_REG [i])); |
---|
| 280 | (*(_Reservation_station-> in_SPR_WRITE_DATA [i])) (*( in_SPR_WRITE_DATA [i])); |
---|
| 281 | } |
---|
| 282 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
| 283 | { |
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[69] | 284 | if (_param->_have_port_ooo_engine_id) |
---|
| 285 | (*(_Reservation_station-> in_BYPASS_WRITE_OOO_ENGINE_ID [i])) (*( in_BYPASS_WRITE_OOO_ENGINE_ID [i])); |
---|
[55] | 286 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_VAL [i])) (*( in_BYPASS_WRITE_GPR_VAL [i])); |
---|
| 287 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_NUM_REG [i])) (*( in_BYPASS_WRITE_GPR_NUM_REG [i])); |
---|
| 288 | (*(_Reservation_station-> in_BYPASS_WRITE_GPR_DATA [i])) (*( in_BYPASS_WRITE_GPR_DATA [i])); |
---|
| 289 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_VAL [i])) (*( in_BYPASS_WRITE_SPR_VAL [i])); |
---|
| 290 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_NUM_REG [i])) (*( in_BYPASS_WRITE_SPR_NUM_REG [i])); |
---|
| 291 | (*(_Reservation_station-> in_BYPASS_WRITE_SPR_DATA [i])) (*( in_BYPASS_WRITE_SPR_DATA [i])); |
---|
| 292 | } |
---|
| 293 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
| 294 | { |
---|
| 295 | (*(_Reservation_station-> in_BYPASS_MEMORY_VAL [i])) (*( in_BYPASS_MEMORY_VAL [i])); |
---|
[69] | 296 | if (_param->_have_port_ooo_engine_id) |
---|
| 297 | (*(_Reservation_station-> in_BYPASS_MEMORY_OOO_ENGINE_ID [i])) (*( in_BYPASS_MEMORY_OOO_ENGINE_ID [i])); |
---|
[55] | 298 | (*(_Reservation_station-> in_BYPASS_MEMORY_NUM_REG [i])) (*( in_BYPASS_MEMORY_NUM_REG [i])); |
---|
| 299 | (*(_Reservation_station-> in_BYPASS_MEMORY_DATA [i])) (*( in_BYPASS_MEMORY_DATA [i])); |
---|
| 300 | } |
---|
| 301 | |
---|
| 302 | cout << "<" << name << "> Start Simulation ............" << endl; |
---|
| 303 | Time * _time = new Time(); |
---|
| 304 | |
---|
| 305 | /******************************************************** |
---|
| 306 | * Simulation - Begin |
---|
| 307 | ********************************************************/ |
---|
| 308 | |
---|
| 309 | // Initialisation |
---|
| 310 | |
---|
| 311 | const uint32_t nb_request = _param->_nb_packet; |
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[69] | 312 | const uint32_t seed = 0; |
---|
| 313 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
---|
[55] | 314 | srand(seed); |
---|
| 315 | |
---|
[69] | 316 | Tcontext_t _ooo_engine_id [nb_request]; |
---|
[55] | 317 | Tcontrol_t _read_ra [nb_request]; |
---|
| 318 | Tgeneral_address_t _num_reg_ra [nb_request]; |
---|
| 319 | Tcontrol_t _read_rb [nb_request]; |
---|
| 320 | Tgeneral_address_t _num_reg_rb [nb_request]; |
---|
| 321 | Tcontrol_t _read_rc [nb_request]; |
---|
| 322 | Tspecial_address_t _num_reg_rc [nb_request]; |
---|
| 323 | |
---|
| 324 | // emulation of registerFile |
---|
[69] | 325 | Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; |
---|
| 326 | Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; |
---|
| 327 | Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; |
---|
| 328 | Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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[55] | 329 | |
---|
| 330 | SC_START(0); |
---|
| 331 | |
---|
| 332 | LABEL("Initialisation"); |
---|
[69] | 333 | in_INSERT_VAL ->write(0); |
---|
| 334 | for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) |
---|
| 335 | in_RETIRE_ACK [i]->write(0); |
---|
[55] | 336 | for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) |
---|
| 337 | in_GPR_WRITE_VAL [i]->write(0); |
---|
| 338 | for (uint32_t i=0; i<_param->_nb_spr_write ; i++) |
---|
| 339 | in_SPR_WRITE_VAL [i]->write(0); |
---|
| 340 | for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) |
---|
| 341 | { |
---|
| 342 | in_BYPASS_WRITE_GPR_VAL [i]->write(0); |
---|
| 343 | in_BYPASS_WRITE_SPR_VAL [i]->write(0); |
---|
| 344 | } |
---|
| 345 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
---|
| 346 | in_BYPASS_MEMORY_VAL [i]->write(0); |
---|
| 347 | |
---|
| 348 | in_NRESET->write(0); |
---|
| 349 | SC_START(5); |
---|
| 350 | in_NRESET->write(1); |
---|
| 351 | |
---|
| 352 | LABEL("Loop of Test"); |
---|
| 353 | |
---|
| 354 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
---|
| 355 | { |
---|
| 356 | LABEL("Iteration "+toString(iteration)); |
---|
| 357 | |
---|
| 358 | int32_t percent_transaction_queue_in = (rand()%50)+25; |
---|
| 359 | int32_t percent_transaction_queue_out = (rand()%50)+25; |
---|
| 360 | int32_t percent_registerfile_valid = (rand()%50)+25; |
---|
| 361 | int32_t percent_transaction_registerfile = (rand()%50)+25; |
---|
| 362 | int32_t percent_transaction_bypass = (rand()%50)+25; |
---|
| 363 | |
---|
| 364 | LABEL("Initialisation"); |
---|
| 365 | |
---|
| 366 | for (uint32_t i=0; i<nb_request; i++) |
---|
| 367 | { |
---|
[69] | 368 | _ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ; |
---|
[55] | 369 | _read_ra [i] = rand()% 2 ; |
---|
| 370 | _num_reg_ra [i] = rand()% _param->_nb_general_register ; |
---|
| 371 | _read_rb [i] = rand()% 2 ; |
---|
| 372 | _num_reg_rb [i] = rand()% _param->_nb_general_register ; |
---|
| 373 | _read_rc [i] = rand()% 2 ; |
---|
| 374 | _num_reg_rc [i] = rand()% _param->_nb_special_register ; |
---|
| 375 | } |
---|
| 376 | |
---|
| 377 | // emulation of registerFile |
---|
[69] | 378 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
[55] | 379 | { |
---|
| 380 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 381 | { |
---|
| 382 | _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
[75] | 383 | _gpr [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[55] | 384 | } |
---|
| 385 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 386 | { |
---|
| 387 | _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
[75] | 388 | _spr [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
[55] | 389 | } |
---|
| 390 | } |
---|
| 391 | // End initialisation ....... |
---|
| 392 | |
---|
| 393 | uint32_t request_in = 0; |
---|
| 394 | uint32_t request_out = 0; |
---|
| 395 | bool request_out_wait [nb_request]; |
---|
| 396 | |
---|
| 397 | for (uint32_t i=0; i<nb_request; i++) |
---|
| 398 | request_out_wait [i] = true; |
---|
[69] | 399 | |
---|
| 400 | bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
| 401 | bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
---|
| 402 | bool need_gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
| 403 | bool need_spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
---|
[55] | 404 | |
---|
[69] | 405 | |
---|
| 406 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
| 407 | { |
---|
| 408 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 409 | need_gpr [j][i] = false; |
---|
| 410 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 411 | need_spr [j][i] = false; |
---|
| 412 | } |
---|
| 413 | |
---|
[55] | 414 | while (request_out < nb_request) |
---|
| 415 | { |
---|
[69] | 416 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
[55] | 417 | { |
---|
[69] | 418 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
| 419 | can_gpr_use [j][i] = true; |
---|
| 420 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
| 421 | can_spr_use [j][i] = true; |
---|
[55] | 422 | } |
---|
[69] | 423 | |
---|
| 424 | Tcontrol_t insert_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); |
---|
| 425 | Tcontext_t insert_ooo_engine_id; |
---|
| 426 | Tgeneral_address_t insert_num_reg_ra; |
---|
| 427 | Tgeneral_address_t insert_num_reg_rb; |
---|
| 428 | Tspecial_address_t insert_num_reg_rc; |
---|
| 429 | |
---|
| 430 | in_INSERT_VAL ->write(insert_val); |
---|
| 431 | if (insert_val) |
---|
[55] | 432 | { |
---|
[69] | 433 | bool data_val; |
---|
| 434 | insert_ooo_engine_id = _ooo_engine_id [request_in]; |
---|
| 435 | insert_num_reg_ra = _num_reg_ra [request_in]; |
---|
| 436 | insert_num_reg_rb = _num_reg_rb [request_in]; |
---|
| 437 | insert_num_reg_rc = _num_reg_rc [request_in]; |
---|
[55] | 438 | |
---|
[69] | 439 | if (_param->_have_port_context_id) |
---|
| 440 | in_INSERT_CONTEXT_ID ->write((2*insert_ooo_engine_id)%_param->_nb_context ); |
---|
| 441 | if (_param->_have_port_front_end_id) |
---|
| 442 | in_INSERT_FRONT_END_ID ->write((3*insert_ooo_engine_id)%_param->_nb_front_end); |
---|
| 443 | if (_param->_have_port_ooo_engine_id) |
---|
| 444 | in_INSERT_OOO_ENGINE_ID ->write(insert_ooo_engine_id); |
---|
| 445 | if (_param->_have_port_rob_id) |
---|
| 446 | in_INSERT_ROB_ID ->write(request_in); |
---|
| 447 | in_INSERT_OPERATION ->write(0); |
---|
| 448 | in_INSERT_TYPE ->write(0); |
---|
[76] | 449 | in_INSERT_STORE_QUEUE_PTR_WRITE->write(0); |
---|
[78] | 450 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 451 | in_INSERT_LOAD_QUEUE_PTR_WRITE ->write(0); |
---|
[69] | 452 | in_INSERT_HAS_IMMEDIAT->write(0); |
---|
| 453 | in_INSERT_IMMEDIAT ->write(0); |
---|
| 454 | // in_INSERT_READ_RA ->write(_read_ra[request_in]); |
---|
| 455 | data_val = not(_read_ra[request_in]) or _gpr_val[insert_num_reg_ra][insert_ooo_engine_id]; |
---|
[55] | 456 | |
---|
[69] | 457 | need_gpr [insert_ooo_engine_id][insert_num_reg_ra] |= not data_val; |
---|
[55] | 458 | |
---|
[69] | 459 | in_INSERT_NUM_REG_RA ->write(insert_num_reg_ra); |
---|
| 460 | in_INSERT_DATA_RA_VAL ->write(data_val); |
---|
| 461 | in_INSERT_DATA_RA ->write((data_val)?_gpr[insert_num_reg_ra][insert_ooo_engine_id]:0); |
---|
| 462 | // in_INSERT_READ_RB ->write(_read_rb[request_in]); |
---|
| 463 | data_val = not(_read_rb[request_in]) or _gpr_val[insert_num_reg_rb][insert_ooo_engine_id]; |
---|
| 464 | |
---|
| 465 | need_gpr [insert_ooo_engine_id][insert_num_reg_rb] |= not data_val; |
---|
| 466 | |
---|
| 467 | in_INSERT_NUM_REG_RB ->write(insert_num_reg_rb); |
---|
| 468 | in_INSERT_DATA_RB_VAL ->write(data_val); |
---|
| 469 | in_INSERT_DATA_RB ->write((data_val)?_gpr[insert_num_reg_rb][insert_ooo_engine_id]:0); |
---|
| 470 | // in_INSERT_READ_RC ->write(_read_rc[request_in]); |
---|
| 471 | data_val = not(_read_rc[request_in]) or _spr_val[insert_num_reg_rc][insert_ooo_engine_id]; |
---|
| 472 | |
---|
| 473 | need_spr [insert_ooo_engine_id][insert_num_reg_rc] |= not data_val; |
---|
| 474 | |
---|
| 475 | in_INSERT_NUM_REG_RC ->write(insert_num_reg_rc); |
---|
| 476 | in_INSERT_DATA_RC_VAL ->write(data_val); |
---|
| 477 | in_INSERT_DATA_RC ->write((data_val)?_spr[insert_num_reg_rc][insert_ooo_engine_id]:0); |
---|
| 478 | in_INSERT_WRITE_RD ->write(0); |
---|
| 479 | in_INSERT_NUM_REG_RD ->write(0); |
---|
| 480 | in_INSERT_WRITE_RE ->write(0); |
---|
| 481 | in_INSERT_NUM_REG_RE ->write(0); |
---|
| 482 | |
---|
| 483 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_ra] = false; |
---|
| 484 | can_gpr_use [insert_ooo_engine_id][insert_num_reg_rb] = false; |
---|
| 485 | can_spr_use [insert_ooo_engine_id][insert_num_reg_rc] = false; |
---|
| 486 | } |
---|
| 487 | |
---|
| 488 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 489 | in_RETIRE_ACK[i]->write((rand()%100)<percent_transaction_queue_out); |
---|
| 490 | |
---|
[55] | 491 | LABEL("Bypass Network :"); |
---|
| 492 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 493 | { |
---|
| 494 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 495 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 496 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
[75] | 497 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[69] | 498 | |
---|
| 499 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
---|
[55] | 500 | |
---|
[69] | 501 | in_GPR_WRITE_VAL [i]->write(val); |
---|
| 502 | if (_param->_have_port_ooo_engine_id) |
---|
| 503 | in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 504 | in_GPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 505 | in_GPR_WRITE_DATA [i]->write(data); |
---|
| 506 | |
---|
[55] | 507 | if (val) |
---|
| 508 | { |
---|
[69] | 509 | LABEL(" * GPR_WRITE ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
| 510 | can_gpr_use [ooo_engine][num_reg] = false; |
---|
| 511 | need_gpr [ooo_engine][num_reg] = false; |
---|
| 512 | |
---|
| 513 | |
---|
| 514 | _gpr [num_reg][ooo_engine] = data; |
---|
| 515 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 516 | } |
---|
| 517 | } |
---|
| 518 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 519 | { |
---|
| 520 | Tspecial_address_t num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 521 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 522 | Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
[75] | 523 | Tspecial_data_t data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
[55] | 524 | |
---|
[69] | 525 | val = (val and can_spr_use [ooo_engine][num_reg] and need_spr[ooo_engine][num_reg]); |
---|
| 526 | |
---|
| 527 | in_SPR_WRITE_VAL [i]->write(val); |
---|
| 528 | if (_param->_have_port_ooo_engine_id) |
---|
| 529 | in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
| 530 | in_SPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
| 531 | in_SPR_WRITE_DATA [i]->write(data); |
---|
| 532 | |
---|
[55] | 533 | if (val == 1) |
---|
| 534 | { |
---|
[69] | 535 | LABEL(" * SPR_WRITE ["+toString(i)+"] - spr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
---|
| 536 | can_spr_use [ooo_engine][num_reg] = false; |
---|
| 537 | need_spr[ooo_engine][num_reg] = false; |
---|
| 538 | |
---|
| 539 | _spr [num_reg][ooo_engine] = data; |
---|
| 540 | _spr_val [num_reg][ooo_engine] = 1; |
---|
[55] | 541 | } |
---|
| 542 | } |
---|
| 543 | |
---|
| 544 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
| 545 | { |
---|
[69] | 546 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
---|
| 547 | if (_param->_have_port_ooo_engine_id) |
---|
| 548 | in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
[55] | 549 | |
---|
| 550 | Tgeneral_address_t gpr_num_reg = rand()% _param->_nb_general_register; |
---|
[69] | 551 | Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
[75] | 552 | Tgeneral_data_t gpr_data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
[55] | 553 | |
---|
[69] | 554 | gpr_val = (gpr_val and can_gpr_use [ooo_engine][gpr_num_reg] and need_gpr[ooo_engine][gpr_num_reg]); |
---|
| 555 | |
---|
[55] | 556 | in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); |
---|
| 557 | in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); |
---|
| 558 | in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); |
---|
| 559 | |
---|
| 560 | if (gpr_val) |
---|
| 561 | { |
---|
[69] | 562 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - gpr["+toString(gpr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(gpr_data)); |
---|
| 563 | can_gpr_use [ooo_engine][gpr_num_reg] = false; |
---|
| 564 | need_gpr[ooo_engine][gpr_num_reg] = false; |
---|
| 565 | |
---|
| 566 | _gpr [gpr_num_reg][ooo_engine] = gpr_data; |
---|
| 567 | _gpr_val [gpr_num_reg][ooo_engine] = 1; |
---|
[55] | 568 | } |
---|
| 569 | |
---|
| 570 | Tspecial_address_t spr_num_reg = rand()% _param->_nb_special_register; |
---|
[69] | 571 | Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
[75] | 572 | Tspecial_data_t spr_data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
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[55] | 573 | |
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[69] | 574 | spr_val = (spr_val and can_spr_use [ooo_engine][spr_num_reg] and need_spr[ooo_engine][spr_num_reg]); |
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| 575 | |
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[55] | 576 | in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); |
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| 577 | in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); |
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| 578 | in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); |
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| 579 | |
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| 580 | if (spr_val) |
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| 581 | { |
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[69] | 582 | LABEL(" * BYPASS_WRITE ["+toString(i)+"] - spr["+toString(spr_num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(spr_data)); |
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| 583 | can_spr_use [ooo_engine][spr_num_reg] = false; |
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| 584 | need_spr[ooo_engine][spr_num_reg] = false; |
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| 585 | |
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| 586 | _spr [spr_num_reg][ooo_engine] = spr_data; |
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| 587 | _spr_val [spr_num_reg][ooo_engine] = 1; |
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[55] | 588 | } |
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| 589 | |
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| 590 | } |
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| 591 | |
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| 592 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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| 593 | { |
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[69] | 594 | Tcontext_t ooo_engine = rand()% _param->_nb_ooo_engine; |
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| 595 | if (_param->_have_port_ooo_engine_id) |
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| 596 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); |
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[55] | 597 | |
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[69] | 598 | Tgeneral_address_t num_reg = rand()% _param->_nb_general_register; |
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| 599 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
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[75] | 600 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
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[55] | 601 | |
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[69] | 602 | val = (val and can_gpr_use [ooo_engine][num_reg] and need_gpr [ooo_engine][num_reg]); |
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[55] | 603 | |
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[69] | 604 | in_BYPASS_MEMORY_VAL [i]->write(val); |
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| 605 | in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); |
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| 606 | in_BYPASS_MEMORY_DATA [i]->write(data); |
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| 607 | |
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| 608 | if (val) |
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[55] | 609 | { |
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[69] | 610 | LABEL(" * BYPASS_MEMORY ["+toString(i)+"] - gpr["+toString(num_reg)+"]["+toString(ooo_engine)+"] <- "+toString(data)); |
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| 611 | can_gpr_use [ooo_engine][num_reg] = false; |
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| 612 | need_gpr [ooo_engine][num_reg] = false; |
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| 613 | |
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| 614 | _gpr [num_reg][ooo_engine] = data; |
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| 615 | _gpr_val [num_reg][ooo_engine] = 1; |
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[55] | 616 | } |
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| 617 | } |
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| 618 | SC_START(0); // to mealy function |
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| 619 | |
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[69] | 620 | // LABEL("Test INSERT : "+toString(in_INSERT_VAL->read())+","+toString(out_INSERT_ACK->read())); |
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| 621 | if (( in_INSERT_VAL->read() == 1) and |
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| 622 | (out_INSERT_ACK->read() == 1)) |
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[55] | 623 | { |
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[69] | 624 | LABEL("Accepted INSERT number : "+toString(request_in)); |
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[55] | 625 | request_in ++; |
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| 626 | } |
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| 627 | |
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[69] | 628 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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[55] | 629 | { |
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[69] | 630 | LABEL("Test RETIRE "+toString(i)+" : "+toString(out_RETIRE_VAL[i]->read())+","+toString(in_RETIRE_ACK[i]->read())); |
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| 631 | if ((out_RETIRE_VAL [i]->read() == 1) and |
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| 632 | ( in_RETIRE_ACK [i]->read() == 1)) |
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[55] | 633 | { |
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[69] | 634 | Tpacket_t rob_id; |
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| 635 | if (_param->_have_port_rob_id) |
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| 636 | rob_id = out_RETIRE_ROB_ID [i]->read(); |
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| 637 | else |
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| 638 | rob_id = 0; |
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| 639 | LABEL("Accepted RETIRE ["+toString(i)+"] number : "+toString(rob_id)+", request number : "+toString(request_out)); |
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| 640 | TEST(bool, request_out_wait [rob_id] , true); |
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[55] | 641 | |
---|
| 642 | request_out ++; |
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[69] | 643 | request_out_wait [rob_id] = false; |
---|
[55] | 644 | |
---|
[69] | 645 | Tcontext_t ooo_engine_id = _ooo_engine_id [rob_id]; |
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[55] | 646 | |
---|
[69] | 647 | if (_param->_have_port_context_id) |
---|
| 648 | TEST(Tcontext_t ,out_RETIRE_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); |
---|
| 649 | if (_param->_have_port_front_end_id) |
---|
| 650 | TEST(Tcontext_t ,out_RETIRE_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); |
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| 651 | if (_param->_have_port_ooo_engine_id) |
---|
| 652 | TEST(Tcontext_t ,out_RETIRE_OOO_ENGINE_ID[i]->read(),ooo_engine_id); |
---|
| 653 | |
---|
| 654 | if (_read_ra [rob_id]) |
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| 655 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RA [i]->read(),_gpr[_num_reg_ra[rob_id]][ooo_engine_id]); |
---|
[55] | 656 | |
---|
[69] | 657 | if (_read_rb [rob_id]) |
---|
| 658 | TEST(Tgeneral_data_t ,out_RETIRE_DATA_RB [i]->read(),_gpr[_num_reg_rb[rob_id]][ooo_engine_id]); |
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[55] | 659 | |
---|
[69] | 660 | if (_read_rc [rob_id]) |
---|
| 661 | TEST(Tspecial_data_t ,out_RETIRE_DATA_RC [i]->read(),_spr[_num_reg_rc[rob_id]][ooo_engine_id]); |
---|
| 662 | |
---|
| 663 | // need_gpr [ooo_engine_id][_num_reg_ra[rob_id]]= true; |
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| 664 | // need_gpr [ooo_engine_id][_num_reg_rb[rob_id]]= true; |
---|
| 665 | // need_spr [ooo_engine_id][_num_reg_rc[rob_id]]= true; |
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[55] | 666 | } |
---|
| 667 | } |
---|
| 668 | |
---|
| 669 | SC_START(1); |
---|
| 670 | } |
---|
| 671 | } |
---|
| 672 | |
---|
| 673 | /******************************************************** |
---|
| 674 | * Simulation - End |
---|
| 675 | ********************************************************/ |
---|
| 676 | |
---|
| 677 | TEST_OK ("End of Simulation"); |
---|
| 678 | delete _time; |
---|
| 679 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
| 680 | |
---|
| 681 | delete in_CLOCK ; |
---|
| 682 | delete in_NRESET; |
---|
| 683 | |
---|
[69] | 684 | delete in_INSERT_VAL ; |
---|
| 685 | delete out_INSERT_ACK ; |
---|
| 686 | if (_param->_have_port_context_id) |
---|
| 687 | delete in_INSERT_CONTEXT_ID ; |
---|
| 688 | if (_param->_have_port_front_end_id) |
---|
| 689 | delete in_INSERT_FRONT_END_ID ; |
---|
| 690 | if (_param->_have_port_ooo_engine_id) |
---|
| 691 | delete in_INSERT_OOO_ENGINE_ID ; |
---|
| 692 | if (_param->_have_port_rob_id) |
---|
| 693 | delete in_INSERT_ROB_ID ; |
---|
| 694 | delete in_INSERT_OPERATION ; |
---|
| 695 | delete in_INSERT_TYPE ; |
---|
[76] | 696 | delete in_INSERT_STORE_QUEUE_PTR_WRITE; |
---|
[78] | 697 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 698 | delete in_INSERT_LOAD_QUEUE_PTR_WRITE ; |
---|
[69] | 699 | delete in_INSERT_HAS_IMMEDIAT; |
---|
| 700 | delete in_INSERT_IMMEDIAT ; |
---|
| 701 | //delete in_INSERT_READ_RA ; |
---|
| 702 | delete in_INSERT_NUM_REG_RA ; |
---|
| 703 | delete in_INSERT_DATA_RA_VAL ; |
---|
| 704 | delete in_INSERT_DATA_RA ; |
---|
| 705 | //delete in_INSERT_READ_RB ; |
---|
| 706 | delete in_INSERT_NUM_REG_RB ; |
---|
| 707 | delete in_INSERT_DATA_RB_VAL ; |
---|
| 708 | delete in_INSERT_DATA_RB ; |
---|
| 709 | //delete in_INSERT_READ_RC ; |
---|
| 710 | delete in_INSERT_NUM_REG_RC ; |
---|
| 711 | delete in_INSERT_DATA_RC_VAL ; |
---|
| 712 | delete in_INSERT_DATA_RC ; |
---|
| 713 | delete in_INSERT_WRITE_RD ; |
---|
| 714 | delete in_INSERT_NUM_REG_RD ; |
---|
| 715 | delete in_INSERT_WRITE_RE ; |
---|
| 716 | delete in_INSERT_NUM_REG_RE ; |
---|
[55] | 717 | |
---|
[69] | 718 | delete [] out_RETIRE_VAL ; |
---|
| 719 | delete [] in_RETIRE_ACK ; |
---|
| 720 | if (_param->_have_port_context_id) |
---|
| 721 | delete [] out_RETIRE_CONTEXT_ID ; |
---|
| 722 | if (_param->_have_port_front_end_id) |
---|
| 723 | delete [] out_RETIRE_FRONT_END_ID; |
---|
| 724 | if (_param->_have_port_ooo_engine_id) |
---|
| 725 | delete [] out_RETIRE_OOO_ENGINE_ID ; |
---|
| 726 | if (_param->_have_port_rob_id) |
---|
| 727 | delete [] out_RETIRE_ROB_ID ; |
---|
| 728 | delete [] out_RETIRE_OPERATION ; |
---|
| 729 | delete [] out_RETIRE_TYPE ; |
---|
[76] | 730 | delete [] out_RETIRE_STORE_QUEUE_PTR_WRITE; |
---|
[78] | 731 | if (_param->_have_port_load_queue_ptr) |
---|
[76] | 732 | delete [] out_RETIRE_LOAD_QUEUE_PTR_WRITE ; |
---|
[69] | 733 | delete [] out_RETIRE_HAS_IMMEDIAT; |
---|
| 734 | delete [] out_RETIRE_IMMEDIAT ; |
---|
| 735 | delete [] out_RETIRE_DATA_RA ; |
---|
| 736 | delete [] out_RETIRE_DATA_RB ; |
---|
| 737 | delete [] out_RETIRE_DATA_RC ; |
---|
| 738 | delete [] out_RETIRE_WRITE_RD ; |
---|
| 739 | delete [] out_RETIRE_NUM_REG_RD ; |
---|
| 740 | delete [] out_RETIRE_WRITE_RE ; |
---|
| 741 | delete [] out_RETIRE_NUM_REG_RE ; |
---|
[55] | 742 | |
---|
| 743 | delete [] in_GPR_WRITE_VAL ; |
---|
[69] | 744 | if (_param->_have_port_ooo_engine_id) |
---|
| 745 | delete [] in_GPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 746 | delete [] in_GPR_WRITE_NUM_REG ; |
---|
| 747 | delete [] in_GPR_WRITE_DATA ; |
---|
| 748 | |
---|
| 749 | delete [] in_SPR_WRITE_VAL ; |
---|
[69] | 750 | if (_param->_have_port_ooo_engine_id) |
---|
| 751 | delete [] in_SPR_WRITE_OOO_ENGINE_ID; |
---|
[55] | 752 | delete [] in_SPR_WRITE_NUM_REG ; |
---|
| 753 | delete [] in_SPR_WRITE_DATA ; |
---|
| 754 | |
---|
[69] | 755 | if (_param->_have_port_ooo_engine_id) |
---|
| 756 | delete [] in_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
[55] | 757 | delete [] in_BYPASS_WRITE_GPR_VAL ; |
---|
| 758 | delete [] in_BYPASS_WRITE_GPR_NUM_REG; |
---|
| 759 | delete [] in_BYPASS_WRITE_GPR_DATA ; |
---|
| 760 | delete [] in_BYPASS_WRITE_SPR_VAL ; |
---|
| 761 | delete [] in_BYPASS_WRITE_SPR_NUM_REG; |
---|
| 762 | delete [] in_BYPASS_WRITE_SPR_DATA ; |
---|
| 763 | |
---|
| 764 | delete [] in_BYPASS_MEMORY_VAL ; |
---|
[69] | 765 | if (_param->_have_port_ooo_engine_id) |
---|
| 766 | delete [] in_BYPASS_MEMORY_OOO_ENGINE_ID; |
---|
[55] | 767 | delete [] in_BYPASS_MEMORY_NUM_REG ; |
---|
| 768 | delete [] in_BYPASS_MEMORY_DATA ; |
---|
| 769 | #endif |
---|
| 770 | |
---|
| 771 | delete _Reservation_station; |
---|
| 772 | #ifdef STATISTICS |
---|
| 773 | delete _parameters_statistics; |
---|
| 774 | #endif |
---|
| 775 | } |
---|